Analysis and simulation of continuous-time digital signal processors

ARTICLE IN PRESS Signal Processing 89 (2009) 2013–2026

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Signal Processing journal homepage: www.elsevier.com/locate/sigpro

Analysis and simulation of continuous-time digital signal processors Bob Schell a,, Yannis Tsividis b,1 a b

Analog Devices, Somerset, NJ 08854, USA Electrical Engineering Department, Columbia University, New York, New York 10027, USA

a r t i c l e in fo

abstract

Article history: Received 23 October 2008 Received in revised form 1 April 2009 Accepted 3 April 2009 Available online 14 April 2009

Digital signal processors operating in continuous time are analyzed. We demonstrate, through analytical and simulation studies, that by operating without a sampling clock the in-band quantization error power is reduced compared to conventional discretetime systems. We present an equivalence that facilitates the study of continuous-time digital signal processors and we explore in detail the case of single sinusoid inputs as well as inputs with a Gaussian distribution. The in-band quantization error power is shown to be lower by up to 25 dB for an 8-bit system, compared to a classical, sampled one with the same resolution. & 2009 Elsevier B.V. All rights reserved.

Keywords: Continuous-time digital signal processors Continuous-time digital filters Quantization spectra Asynchronous digital systems Asynchronous digital signal processing

1. Introduction Conventional digital signal processors (DSPs) operate in discrete amplitude and discrete time. The discretization of amplitude is essential for making possible the use of digital hardware, handling only 0 and 1 s, thus affording noise immunity and programmability. It also makes possible handling by clocked digital hardware, as well as provides a finite number of samples which can then be stored in a digital medium. However, discretization of time is not a necessary condition for handling a discreteamplitude signal with digital hardware. We investigate DSPs that operate in continuous time (CT) [1], intended for real-time processing. Our main aim in this effort is to understand the principles involved in such processing, to assess their capabilities using analysis and simulation, and to compare them to discrete-time processors. Several papers have already appeared on hardware issues in CT DSPs. Thus, a preliminary laboratory confirmation of CT

 Corresponding author. 285 Davidson Ave. 4th Floor, Somerset NJ, 08854, USA. Tel.: +1732 868 7132. E-mail addresses: [email protected] (B. Schell), [email protected] (Y. Tsividis). 1 This material is based on work supported by National Science Foundation Grants CCR-02-09109 and CCF-07-01766.

0165-1684/$ - see front matter & 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.sigpro.2009.04.005

DSPs has been presented in [2], and a detailed experimental verification using a custom-designed VLSI chip has been presented in [3] with a detailed description in [4]. An extension of the CT DSP concept to wave digital filters has been presented in [5], whereas the utilization of the CT DSP concept in digital control loops has been described in [6]. Due to the increasing interest as of late in CT DSPs, in this paper we seek to provide a comprehensive view of the differences between conventional and CT processing and the benefits of the latter. The presentation will be carried forth with analytical as well as simulation results at the system level; the interested reader can consult the aforementioned references for implementation details (additional references will be given later in this paper where appropriate). A block diagram of a conventional system is shown in Fig. 1(a) with a clock (sampling) at frequency f S. This frequency defines a band of interest ½0 f S =2 which will be considered the only range of frequencies of interest. The system presented in this work involves not a clocked DSP, but a CT DSP. The use of a CT DSP implies the use of a CT analog-to-digital converter (ADC) [7–10] and a CT digitalto-analog converter (DAC). The entire combination of a CT ADC, CT DSP, and a CT DAC will be referred to in this paper using the term ‘CT ADC-DSP-DAC.’ A block diagram of a CT ADC-DSP-DAC is shown in Fig. 1(b).

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Fig. 1. (a) Block diagram of a general conventional DSP system, showing the sample-and-hold block, ADC, DSP, and DAC blocks. The DAC is assumed to be a zero-order-hold output DAC. In comparison, a CT ADCDSP-DAC which is the study of this work, is shown in (b).

Fig. 2. Principle of continuous-time analog-to-digital conversion. Shown are the input signal xðtÞ, its quantized version qðtÞ, and the binary representation of the latter. The bit waveforms bn ðtÞ are binary signals in continuous time.

Fig. 2, adapted from [1], shows one way that a CT analog signal can be converted to CT digital form for processing using the techniques analyzed in this paper. The input signal xðtÞ is passed directly through a quantizer without sampling it first, giving the signal qðtÞ. Note that, for a given quantizer characteristic q ¼ f ðxÞ, the times t j at which qðtÞ changes depend only on when the input signal crosses a quantizer level; t j can have any real value. Thus, qðtÞ is defined over the entire continuous-time variable, t.

Since the number of possible levels for q is finite, these levels can be represented by binary words; the individual bits for such words are shown at the bottom of the figure. This representation is digital, according to the common definition of this term: it consists of only 0 and 1 s. However, although classical digital signals and systems are defined in discrete time, our digital signals are defined in continuous time. Since the signal qðtÞ changes at the times tj at which the input crosses the quantizer levels, one could think of the system as sampling the input at times t j . However, the times tj are not specified by an independent sampling waveform, but rather by the input signal itself. For this reason, common theories of sampling (uniform or nonuniform) cannot be easily adapted to this case. There is instead a more convenient, equivalent way of viewing the process indicated in Fig. 2: the signal is passed through a memoryless non-linear system, the quantizer, defined by q ¼ f ðxÞ; the resulting output, qðtÞ ¼ f ðxðtÞÞ, is defined over all continuous time and can be viewed as a distorted version of xðtÞ, without involving sampling at all. This view will be adopted in the rest of the paper, and will be found advantageous in spectral analysis, as will be discussed. Our motivation in deciding to investigate CT DSPs originates from several attractive properties possessed by such systems. First, since no sampling is involved, there is no aliasing. Without aliasing, the spectra involved in CT DSPs are very different from those in discrete-time DSPs; for example, if the input is a sinusoid, the quantization error has frequency components only at harmonic frequencies, with no ‘quantization noise’ between those.2As a result, the quantization error of interest (that which resides ‘in-band’) in a CT DSP can be much lower than in the conventional case. We note that aliasing is an artifact of sampling and will not occur in a CT DSP even if the system is non-ideal. To see this, consider a CT DSP acting on a periodic input, with the output also periodic. Any imperfections in the output due to hardware will normally occur at the same portion of the waveform every time. Thus the imperfections will be periodic with the period of the input, and will only create frequency components that are harmonics of the input frequency. This differs from aliasing, which creates frequency components that are not harmonically related to the input. An important advantage of CT DSPs ensues if there is low or no signal activity. In such cases, as expected from Fig. 2, the number of switching events in a CT DSP decreases, and thus the power dissipation in a hardware implementation decreases as well. This can be important in several practical applications where power is provided by batteries, such as in hearing aids, certain remote sensor networks or neural prostheses using implantable electronics [11]. This property has been confirmed experimentally in [3]. Finally, an important property of CT DSPs is that, since there is no sampling, their output responds

2 In fact, the quantization noise in conventional DSPs under sinusoidal excitation can be shown to be equivalent to aliasing of harmonic components from around multiples of the sampling frequency [1]; in our case, since no sampling is involved, no such aliasing occurs.

ARTICLE IN PRESS B. Schell, Y. Tsividis / Signal Processing 89 (2009) 2013–2026

2015

Fig. 3. Two input–output equivalent CT ADC-DSP-DACs where the CT DSP is an FIR filter. (a) CT ADC-DSP-DAC operating with a pulse code modulated (PCM) format where each bit waveform from the CT ADC is filtered independently. (b) CT ADC-DSP-DAC using a delta modulator to encode the input xðtÞ. The delta modulator based scheme uses far fewer CT delay elements compared to the PCM encoded scheme, but requires proper initialization.

immediately to their input. This turns out to be important in digital control loops which need to react very fast [6]. In order to demonstrate these benefits experimentally, we had to confront several hardware issues. As it usually happens when new technologies are introduced, we were able to solve such issues at low speeds first, and have thus initially concentrated on low-frequency real-time processing.3 We do not propose, of course, to replace clocked DSPs in all applications, even at low frequencies; rather, we believe that the two approaches complement each other, each having different advantages. Certainly, there are some applications where the tradeoffs involved in moving to CT DSPs may be too costly (i.e., if a CT ADC is difficult to implement, or if the CT DSP requires large memory cache, etc.). However, already some applications have begun suggesting themselves, where the benefits of a CT DSP outweigh the complexity involved in moving to the new approach. One such application is fast digital control loops in power conversion [6]; we believe that another such application is biomedical devices, as suggested above. In [12] we provide results from a study of finite impulse response (FIR) CT DSP structures backed by simulation. In the present paper, after summarizing the main results of that study, (a) we expand them to include the case of delta modulation (single-bit implementations), (b) we show how the concepts can be extended to infinite impulse response (IIR) filters, (c) we develop an input– output equivalent model, and (d) we provide detailed simulations which quantify the advantages of CT digital signal processing over Nyquist-rate conventional processing for the case of a single sinusoidal input and a bandlimited input whose amplitude obeys a Gaussian probability density function (pdf). It should be noted that although two specific types of CT analog-to-digital conversion will be considered as examples in this paper, the CT DSP techniques that will be discussed are not limited only to processing signals resulting from those types. Any signal with a binary representation can be processed using the techniques

3 Due to the lack of a clock in a CT ADC-DSP-DAC, data storage, even temporary, is not a trivial hardware issue, and at present suggests that the technique is best suited to real-time processing.

we will discuss, including asynchronous sigma-delta signals [13], pulse duration modulated signals, and pulse position modulation signals. CT DSP can be used to process even sampled and held signals, such as those resulting from conventional ADCs. Indeed, since the input is considered for all time, any binary signal, clocked or not, can be processed in principle; however, it goes without saying that once the signal is sampled, conventional techniques are much more appropriate for processing it.

1.1. Alternative realizations We begin by examining a configuration that is especially well suited to CT ADC-DSP-DACs, namely digital filters [2,3]. One reason for this fit is the immediacy in processing the input without the need for long-term storage. Two possible FIR realizations are shown in Fig. 3. In Fig. 3(a) [12] the input signal, hereafter referred to as xðtÞ, is converted by a CT ADC into N binary waveforms bn ðtÞ, n 2 ½1 . . . N, t 2 R. The CT ADC (and all ADCs in this work) is assumed to have uniformly spaced thresholds, meaning the ADC is equivalent to a uniform quantizer. The bn ðtÞ waveforms collectively are the digital representation of xðtÞ at time t. Each bn ðtÞ waveform is processed by N identical CT FIR filters having tap weights ak , k 2 ½0 . . . K and CT delays T D . The N CT FIR filter outputs, sn ðtÞ, are combined in the CT weighted adder block and presented to the CT DAC, which constructs the output yðtÞ. The system output yðtÞ of Fig. 3(a) will be written by inspection assuming that there are no finite wordlength limitations in the DSP, and that the CT DAC’s resolution is sufficient to not truncate the CT adder output. Each FIR output is given by sn ðtÞ ¼

K X

ak  bn ðt  k  T D Þ

(1)

k¼0

The final output is the weighted sum of the sn ðtÞ waveforms: yðtÞ ¼

N X n¼1

2n

K X k¼0

ak  bn ðt  k  T D Þ

(2)

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delayed and weighted versions of the quantized representation of xðtÞ are formed in creating the g k ðtÞ signals:

Rearranging the order of summation: yðtÞ ¼

K X

ak

N X

2n  bn ðt  k  T D Þ

(3)

n¼1

k¼0

The order of summation in (3) beckons the definition of a new signal qðtÞ as qðtÞ ¼

N X

2n  bn ðtÞ

(4)

As the bn ðtÞ waveforms collectively are the digital representation of xðtÞ at time t, qðtÞ represents the output of an N-bit CT quantizer, or the back-to-back combination of an N-bit CT ADC and a CT DAC. Substituting (4) into (3): K X

ak  qðt  k  T D Þ

(5)

k¼0

It is clear from (5) that yðtÞ is indeed the FIR filter output, determined by tap weights ak and tap delays T D , of the quantized input. At no point in Fig. 3(a) is there a clock either sampling the input or synchronously moving the signals through the filter; all signals vary in continuous time. Taking Laplace transforms in (5) we obtain YðsÞ ¼ WðesT D ÞQ ðsÞ

(6)

with WðesT D Þ ¼

K YðsÞ X a ðesT D Þk ¼ Q ðsÞ k¼0 k

(7)

The frequency response, obtained by setting s ¼ jo, o real, in the above equation is going to be periodic in o, just like for a conventional digital filter. Eq. (6) is represented diagrammatically in Fig. 4, where it is clear that Fig. 3(a) represents the actions of quantizing the input and then filtering with the FIR transfer function. We next present an alternative realization of a CT ADCDSP-DAC in Fig. 3(b) [14], utilizing a CT delta modulator to encode the input xðtÞ into the digital domain [15]. Discrete-time DSPs based on delta modulation have been proposed before [16,17]. The delta modulator outputs information that indicates when xðtÞ moves up or down across an amplitude quantization boundary. The top UP/ DN counter block accumulates the sequence of ‘up’ and ‘down’ information by either adding a least significant bit (LSB) to, or subtracting an LSB from, its previous output value, respectively. The output of the counter is a digital word consisting of CT bit waveforms bn ðtÞ, which collectively represent a quantized representation qðtÞ of the input, where qðtÞ is the same as in (4); this is then multiplied by a tap weight a0 to form signal g 0 ðtÞ. Similar

(8)

The final output yðtÞ is the sum of the g k ðtÞ waveforms, or yðtÞ ¼

n¼1

yðtÞ ¼

g k ðtÞ ¼ ak  qðt  k  T D Þ

K X

g k ðtÞ

(9)

k¼0

Substituting (8) into (9) results in (5), showing that the input–output relationships of Fig. 3(a) and (b) are identical. It is noted that for the system shown in Fig. 3(b) to operate properly the UP/DN counters must be initialized. Appropriate initialization means that when xðtÞ is at its mid-range value, the first UP/DN counter (feeding into the a0 gain block) is at its mid-range value, and the UP/DN counter feeding into the ak gain block reaches its midrange values after k delays of T D . This added complexity is offset by the reduction in the number of CT delay elements. Fig. 3(a) uses K  N CT delays, while Fig. 3(b) uses only K. As an example, we plot in Fig. 5(a), (b), and (c) the spectra of xðtÞ, qðtÞ, and yðtÞ, respectively, as they appear in Fig. 3(b) using N ¼ 4 and a low-pass FIR filter for the DSP. The input is the sum of three sinusoids at frequencies 200, 400, and 1:8 kHz. We plot in Fig. 5(d)–(f) the corresponding spectra found when the system of Fig. 3(b) is replaced by a conventional DSP with a sampling clock rate of 4:33 kHz and the same frequency response as the CT DSP. Fig. 5(e) has aliased spurs at frequencies not related to the input tones, resulting in more in-band quantization error power (counting all components up to 2:165 kHz) compared to Fig. 5(b). The output spectra of each system, the CT ADC-DSP-DAC output plotted in Fig. 5(c) and the conventional DSP output plotted in Fig. 5(f), are filtered versions of Fig. 5(b) and (e), respectively. Although Fig. 3 shows implementations of FIR filters, other possible topologies for the CT DSP are possible. As a further example, a CT ADC-DSP-DAC where the CT DSP is an IIR filter is shown in Fig. 6. The output digital word is fed back through continuous-time delays and weighted and fed to the adder. Note that there is still a separation of the CT ADC, CT DSP and CT DAC. Although not explicitly shown, there is an unavoidable need for digital truncation in an IIR implementation. The reason is the same as for conventional DSPs, as the following argument will suggest. Consider a digital word feeding the CT DAC that is P bits wide and fed back and multiplied by digital coefficients (d1 and d2 in Fig. 6). The number of bits will increase at the input of the CT adder, but the CT adder output was already stated to be P bits wide. Thus in this implementation there needs to be a truncation at some point in the feedback loop. 1.2. Hardware considerations

Fig. 4. An input–output equivalent of the system in Fig. 3(a). The first block represents an N-bit quantizer and the second represents the FIR filter.

Both a CT ADC and a CT DAC are non-conventional blocks required for a CT ADC-DSP-DAC system. A CT ADC can be thought of as a ‘flash’-style ADC where the comparators are all free running. A CT DAC can be formed

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NON− SAMPLED 0

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Fig. 5. Views of the spectrum of the signal as it progresses through the system shown in Fig. 3(b) with N ¼ 4 using a DSP to filter out the highest frequency component. (a) Input spectrum for a CT system. (b) Spectrum of qðtÞ for a CT system. (c) Output spectrum for a CT system. (d), (e), and (f) correspond to (a), (b), and (c), respectively, where Fig. 3(b) has been replaced with a synchronous system (denoted by the ‘S’ subscript where appropriate) with a clock rate of 4:33 kHz using a sampled ADC and z1 elements in place of CT delays.

from a conventional Nyquist-rate DAC with an asynchronous latching signal that gates the incoming digital word. Several implementations of both of these blocks have been published by both these authors [3,4] and others [9,10,14]. The structure of the CT DSP can be derived by using a conventional DSP as a prototype. For example, this can be seen by examining Figs. 3 and 6, where examples of FIR and IIR CT digital filters parallel a conventional implementation. This is also illustrated in [5], where the implementation of wave digital filters, a conventional structure, was converted to a CT DSP, leading to performance improvements. Finally, in [3,14] CT FIR filters are created without the use of any digital multipliers by basing the designs on Fig. 3(b) and combining the UP/DN counter and series multiplier. Asynchronous gating techniques are used to properly handle the CT flow of digital

signals, see [4] for details. Theoretically, any conventional filter architecture can be implemented as a CT DSP by simply replacing conventional digital blocks with CT counterparts. Thus, the number of multipliers in the two approaches is generally the same. The conventional discrete-time delay blocks are replaced by corresponding CT delay blocks, as is seen for example in Fig. 3(a). The practical implementation of such CT delays has been studied at length, and has been addressed in [18]. There is only one implementation aspect for which the above correspondence between discrete-time and CT implementations breaks down: the clock. Whereas the clock is an essential part of any discrete-time implementation, in our CT approach there is no clock; instead, the processor is entirely signal-driven. This, as already mentioned in the Introduction, results in a power dissipation which decreases as the input activity decreases.

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Fig. 6. An example CT ADC-DSP-DAC implementation of a 2nd order IIR filter.

Further hardware implementation details are given elsewhere [3–5,9,10,14,18] and are outside the scope of this paper, which instead focuses on system-level analysis of the CT ADC-DSP-DAC approach. Although a few specific realizations were presented above as examples, the analysis that follows is general, and is not limited to the FIR and IIR filter shown above. Such general analysis is possible from the new viewpoint of an equivalent system, presented in the following section, which can be used to detail how finite wordlength effects (such as the required truncation in an IIR filter) are handled in a CT ADC-DSP-DAC, as well as to stress the effects of quantizers and to further the comparison to conventional DSPs. Our previous brief analysis in [12] of sinusoidal inputs and band-limited inputs whose amplitudes obey a Gaussian probability density function is reviewed and extended to greater detail in Sections 3 and 4, respectively. Section 5 discusses a two-tone input test.

2. CT ADC-DSP-DAC equivalent system Fig. 7(a) depicts the block diagram of a CT ADC-DSPDAC, showing the signal flowing from left to right first through an N-bit CT ADC and into a CT DSP. The signal emerges from the CT DSP as a P-bit word and is converted back to analog form with an M-bit CT DAC. The CT ADCDSP-DAC can be linear or non-linear, with or without memory. The resolution of the output CT DAC, M, may not match the resolution of the CT DSP output word P, and indicates possible truncation of the digital word. This is discussed more later. Fig. 7(a) matches topologically closest with Figs. 3(a) and 6, but as Fig. 3(a) and (b) have equivalent input–output relationships, this discussion is applicable to all three realizations, and is in fact more general. All blocks in Fig. 7(a) are continuous-time; in particular, there is no sampling in the CT ADC, and no clock moving bits through registers in the CT DSP. The resolution of each block is labeled in this figure.

Fig. 7. Four input–output equivalent representations of a CT ADC-DSPDAC. The top row shows an actual implementation of a CT ADC-DSP-DAC while the others are mathematical simplifications, resulting in a simple but equivalent system at the bottom. There is no clock in any of these systems.

The first step toward simplifying Fig. 7(a) is to recognize that any real M-bit CT DAC can be represented as the series combination of an ideal DAC (one with infinite resolution and perfect linearity) and a quantizer with M bits of resolution, as shown in Fig. 7(b). The

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input–output relationships are the same, both taking a Pbit wide digital input and yielding an analog signal whose amplitude is restricted to a finite number of levels, the number being related to the M bits of resolution. Looking at Fig. 7(b), the analog signal between the ideal DAC and the M-bit quantizer is also restricted to a finite number of levels, since it originates from the P-bit word input to the ideal DAC. If MXP the output quantizer may be dropped from this picture as it does not further limit the number of levels that the signal may occupy. However, if MoP then the output quantizer further restricts the signal, indicating truncation due to finite wordlength capabilities of the real M-bit CT DAC in Fig. 7(a). Before continuing, the input–output relationship of an ideal DAC will be discussed. It is important to recognize what the signals are at the input and output. Both are continuous in time; the input is the signal represented by a finite digital word and the output is an analog signal whose amplitude corresponds to the input value. An ideal DAC only changes the representation of the signal; the signal value itself is not changed. To then summarize the progression of signals through Fig. 7(b), the CT ADC outputs an N-bit wide digital word which is operated on by the CT DSP to produce a P-bit wide digital signal, whose output value is unchanged when moving through the ideal DAC to the input of the M-bit quantizer. Fig. 7(c) eliminates the digital input/digital output CT DSP of Fig. 7(b) using instead an analog input/analog output operator block that operates on the input according to the operator f ð Þ, and changes the order of the blocks as shown. The f ð Þ operator performs the same operations as the CT DSP but operates on different representations of signals: f ð Þ operates on analog inputs and produces analog outputs; the CT DSP operates on digital inputs and produces digital outputs. As the ideal DAC does not change the value of the signal, the input to the f ð Þ operator block in Fig. 7(c) has the same value as the digital signal input to the CT DSP block in Fig. 7(b). Since both the CT DSP in Fig. 7(b) and the f ð Þ block in Fig. 7(c) operate on their inputs in the same manner, the value of the output of each will be the same. As the ideal DAC in Fig. 7(b) does not change the value of the signal, the input to the M-bit quantizer in both Fig. 7(b) and (c) will have the same value. The final step in the simplification of Fig. 7 is to combine the N-bit input CT ADC with the ideal DAC that now follows it, which is done in Fig. 7(d). The output of the ideal DAC is a signal that is restricted in amplitude to a finite number of levels corresponding to the resolution of the N-bit CT ADC, so the overall behavior of the CT ADCDAC combination is that of an N-bit quantizer. Analysis of this last system (Fig. 7(d)) is much simpler than that of the original system (Fig. 7(a)). We now compare the above system to a conventional (discrete-time) DSP under similar manipulations that were shown in Fig. 7. The conventional system is comprised of an anti-aliasing filter, a sample-and-hold circuit, followed by an input quantizer and processing with a now discrete-time processor. The signal at the input to the output DAC will be different compared to that

2019

in a CT ADC-DSP-DAC due to the sampling process, but conversion back to the analog domain via the output DAC is common between the two. As the main effort is to develop a comparison between a CT ADC-DSP-DAC and a conventional system, the common output DAC is not a concern. Instead the focus will be on quantizing the input, as what follows after that is well understood. Differences between a signal passed through a quantizer (as occurs in a CT ADC-DSP-DAC) and a signal that is first sampled then passed through a quantizer (as in a conventional system) will be examined. Continuous-time digital signal processors exhibit finite wordlength effects, just as discrete-time ones do. Such effects have been discussed in the literature [19], so they will not be considered here.

3. CT quantizing of deterministic symmetric inputs As mentioned in Section 1, the band of interest for the conventional system, shown in Fig. 1(a), is ½0 f S =2. Thus the CT ADC-DSP-DAC system that the conventional system is compared against will have its output yðtÞ investigated over the same frequency range. The analysis of the previous section and Fig. 7(d) motivates the study of quantizing in CT as the first step in analyzing how a CT ADC-DSP-DAC operates on the input. Thus CT quantization will be investigated here with an attention to the spectrum of qðtÞ up to a given frequency (f S =2, to make the comparison to the conventional system). Although the process of going through a CT quantizer is non-linear, the output can be derived in closed form for certain categories of inputs. This section analyzes CT quantization of a specific category of deterministic symmetric inputs, described below, and focuses on single sinusoid inputs of arbitrary amplitude. Single sinusoid inputs have previously been addressed by Clavier et al. [20] by assuming that the amplitude of the input sinusoid is exactly an integer number of quantizer steps. The approach therein assumes that the input sinusoid amplitude is known and the N-bit quantizer is designed to exactly fit the sinusoid. However, this leads to an important restriction on the error waveform near the crests of the sinusoid, forcing the error to exactly zero at these times. Our previous results are quickly summarized below; the reader is referred to [12] for a detailed derivation. Note that the approach here differs from the use of Bessel functions as in [21,22] or more generalized characteristic functions as in [23]. The input–output relationship of a 3-bit uniform midtread quantizer is shown in Fig. 8. The quantizer has been normalized to a range of ½1 1 for both the input and output, and this normalization leads to a step size D ¼ 2=2N . Fig. 9 shows example waveforms at the input and output of a CT quantizer. The top plot in Fig. 9 is for a sinusoidal input; the bottom input also obeys the required symmetries, following eat  1 between t ¼ 0 and t ¼ T=4, where T ¼ 1 and a is some constant (shown here to emphasize generality, see [12] for details). The remainder of the waveform is formed by symmetry.

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In [12] the output from a CT mid-tread quantizer qðtÞ for this class of inputs was written as a one-sided Fourier sum:

Both input signals in Fig. 9 have an amplitude A ¼ xMAX where xMAX is the maximum amplitude that maintains odd symmetry in the transfer characteristic (see Fig. 8). For an N-bit uniform mid-tread quantizer normalized as in Fig. 8, xMAX is given by xMAX ¼



1

1

qðtÞ ¼

þ1 X

cðnÞ sinð2pð1=TÞn  tÞ

(11)

n¼1



where the Fourier coefficients are found to be given by

(10)

N

2

cðnÞ ¼

steps p  NX 4D sin n sinðdi  p  nÞ pn 2 i¼1

(12)

D is the step size of the mid-tread quantizer (see Fig. 8). Referring to Fig. 9, the rest of the quantities in (12) can be explained. Nsteps is the number of steps above 0 that are utilized in the first half-cycle of the input (in Fig. 9, N steps ¼ 3). This can be found in closed form (with intð Þ representing the ‘integer part’ operator):    A þ 0:5D (13) N steps ¼ min 2N1  1; int

D

The minð Þ operator is used in (13) to clamp the result to the maximum value in the event that the input amplitude is out of range of the quantizer and is required to attain the input–output relationship shown in Fig. 8. di is related to the duration of time that the input signal spends above the ith positive quantization level boundary when looking at the first half cycle of the input. The top plot of Fig. 9 annotates d1 and d3 to clarify the meaning. We note that the x-axis is normalized to one period. 3.1. Sinusoidal input The case of an N-bit quantizer output given a sinusoidal input of arbitrary amplitude A has been examined by the authors in [12]; it is revisited here as

Fig. 8. Input–output relationship for a 3-bit uniform mid-tread quantizer, showing the maximum input amplitude xMAX to keep odd symmetry. Note that the step size is defined here as D ¼ 2=2N .

1 ←

Amplitude

0.5 ←

0

d3 d1

→ →

−0.5 −1 0

0.25

0.5 Time / T

0.75

1

0

0.25

0.5 Time / T

0.75

1

1

Amplitude

0.5 0 −0.5 −1

Fig. 9. Behavior of a 3-bit quantizer output (in bold) given two symmetric inputs. The time axis is normalized to one period.

ARTICLE IN PRESS B. Schell, Y. Tsividis / Signal Processing 89 (2009) 2013–2026

the results are given in greater detail and lead to an expanded discussion. From [12], the di values for a sinusoid of amplitude A through an N-bit mid-tread quantizer of step size D are   1 1 ð2i  1ÞD di ¼  sin1 (14) 2A 2 p Eqs. (11)–(14) provide a complete description of the quantizer output given a sinusoidal input; an example is seen at the top of Fig. 9. The results of (11), (12) and (14) have the same form as those derived in [20]. The difference lies in the decoupling

Total Error

Sawtooth

Tip

N=4

0

0.25

0.5 0.75 Time over one period

1

20 log (Amplitude)

Fig. 10. Showing that the total error waveform is a sum of a ‘tip’ portion and the ‘sawtooth’ portion. All curves are constructed using (12) and (16) for A ¼ ð1  1:75=2N Þ and N ¼ 4.

2021

of amplitude A and quantizer step size D. The more general result presented here reduces to that of Clavier et al. by setting A ¼ ð2N1  1Þ  D, as this will result in Nsteps ¼ 2N1  1 and the error signal will be zero at the crests of the sinusoid. The utility of these equations comes when examining the SDR of qðtÞ for various input amplitudes A, as it will be shown that significant variation may occur for small variations in A. This may be done directly on the coefficients from (12). Before doing so, it is instructive to decompose the error waveform (difference between quantizer output and input) into ‘tip’ and ‘sawtooth’ waveforms as shown at the top and middle of Fig. 10, respectively. Note that these definitions are different from a similar breakdown used in [24]; here the term ‘sawtooth’ waveform is used to describe the total error waveform minus the ‘tip’ waveform, not just a subset of this. The ‘tip’ waveform can be analyzed directly by using the previous notation, since the maximum height of the quantized output is known to be N steps  D. With this in mind, the ‘tip’ waveform as a Fourier series akin to (11) can be derived; let the Fourier coefficients be ctip ðnÞ. The ‘tip’ waveform, in the first half cycle, is defined as being the portion of the error waveform eðtÞ ¼ A sin½2pð1=TÞt  qðtÞ but only during the time when the CT quantized output value is Nsteps  D. Due to symmetry, we only need to know when the input rises from 0 to N steps  D  D=2, the largest quantization level boundary to be crossed in the first half cycle of the input. The time from zero to when the input crosses this value is

t TIP ¼

  Nsteps  D  D=2 T sin1 A 2p

(15)

A = 1 − 1/2N

−50 −100 −150

Largest distortion component in total error waveform 3rd harmonic in ‘tip’ waveform Fourier decomposition 3rd harmonic in ‘sawtooth’ waveform Fourier decomposition

−200 −250

20 log (Amplitude)

3

4

5

6

7

8 N

9

10

11

12

13

12

13

A = 1 − 1.5/2N

−50 −100 −150

Largest distortion component in total error waveform 3rd harmonic in ‘tip’ waveform Fourier decomposition 3rd harmonic in ‘sawtooth’ waveform Fourier decomposition

−200 −250 3

4

5

6

7

8 N

9

10

11

Fig. 11. Examination of the largest distortion component in the total error waveform, comparing to the 3rd harmonic of both the ‘tip’ waveform and ‘sawtooth’ waveforms. Top: A ¼ 1  1=2N . Bottom: A ¼ 1  1:5=2N .

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B. Schell, Y. Tsividis / Signal Processing 89 (2009) 2013–2026

While the input is above Nsteps  D  D=2, qðtÞ ¼ Nsteps  D. Letting d ¼ ð14Þ  t TIP =T and finding the Fourier series for the complete ‘tip’ waveform over the entire period results in þ1 X

N=8

−45

DSR with sampling = −(1.76 + 6.02⋅8) ≈ −50 dB

−50

ctip ðnÞ sinð2pð1=TÞn  tÞ

DSR (dB)

etip ðtÞ ¼

−40

n¼1

with the ‘tip’ coefficients given by 1 0 A sinð2 p ð1  nÞ d Þ C B 2pð1  nÞ C B C p B A C B sinð2pð1 þ nÞdÞ C ctip ðnÞ ¼ 4 sin n B þ C 2pð1 þ nÞ 2 B C B A @ N steps  D  sinð2pndÞ pn

−55

Total distortion Sawtooth distortion

−60

Tip distortion

−65

(16)

−70 −75 0

With this known, the Fourier sum expression for the ‘sawtooth’ portion of the error waveform can be quickly found: the error signal is the difference between the input and qðtÞ, and the ‘sawtooth’ waveform is the difference between the error signal and the ‘tip’ waveform. The expressions derived above were used to independently create the ‘tip’, the ‘sawtooth’ and the total error waveforms in Fig. 10. The above results can also be used to examine the spurious free dynamic range (SFDR) of a quantizer, where only the single largest distortion component is of interest. We plot in Fig. 11 not the SFDR, but simply 20  log10 ðamplitudeÞ of the largest harmonic component, along with the 3rd harmonic from each of the ‘tip’ and ‘sawtooth’ waveforms, for two slightly different amplitudes of the input sinusoid. In the upper plot, A ¼ 1  1=2N which is recalculated for each new value of N, and the data show that the ‘tip’ waveform contributes the dominant portion of energy to the total error waveform’s largest harmonic. This indicates that the ‘tip’ waveform is effectively setting the SFDR. The largest harmonic is seen to decrease by 9 dB=bit as the quantizer resolution is increased by one, agreeing with the findings in [24]. The bottom plot of Fig. 11 shows a similar investigation where the amplitude has been slightly decreased, to A ¼ 1  1:5=2N (for each N) and tells a different story for larger values of N. In this bottom plot, the ‘tip’ waveform has lost so much energy that the ‘sawtooth’ waveform dominates the contribution to the total error waveform’s largest harmonic. This indicates that in some instances the SFDR is determined by the ‘sawtooth’ portion of the total error waveform, not the ‘tip’ portion of total error waveform. Note that although the ‘tip’ waveform’s 3rd harmonic now decreases by 15 dB=bit of quantizer resolution, the largest distortion component still decreases in power by 9 dB=bit, as before. Instead of looking at just a few harmonics, Fig. 12 shows the contribution of the ‘tip’ and the ‘sawtooth’ waveforms to the total error power when including a wider band of distortion components. As previously stated, the conventional system that the CT ADC-DSPDAC system is compared against has a band of interest ½0 f S =2. As such, when considering ‘in-band’ distortion, the spectrum of qðtÞ is examined only up to some frequency. One means to represent this is to assume that

100 200 300 400 500 600 700 Number of harmonic components included in distortion power calculation

Fig. 12. DSR vs. number of terms included when calculating distortion power. A ¼ xMAX and N ¼ 8.

the CT quantizer is followed by an ideal low pass filter (LPF) that limits the waveforms to a finite number of terms in their Fourier construction, and the number of included terms forms the x-axis of Fig. 12. The y-axis shows distortion-to-signal ratio (DSR), or the negative (in dB) of the SDR. The lower three curves show DSR using for distortion: just the ‘tip’ portion, just the ‘sawtooth’ portion, and finally the total error waveform. As can be seen, with A ¼ xMAX (as is the case in the top plot of Fig. 11) the error power is dominated by contributions from the ‘tip’ waveform for lower bandwidths of the ideal LPF, and the ‘sawtooth’ waveform for higher bandwidths of the ideal LPF. The DSR increases asymptotically toward the uppermost curve, which is the DSR one achieves through sampling and then quantizing at the Nyquist rate [25]. This is because only if all frequency components of the error waveform are included in the distortion power, will that power equal the distortion power seen when sampling. From Fig. 12 there is an over 10 dB reduction in DSR (increase in SDR) when not sampling if the frequency range of the system only includes up to the 100th harmonic (always for N ¼ 8). In Fig. 12 with A ¼ xMAX the size of the ‘tip’ waveform is maximum. If the amplitude is changed slightly to reduce the size of the ‘tip’ waveform, the benefit of CT quantizing over a sampled system will increase. For example, consider Fig. 13, which shows the improvement in SDR of a CT quantizer over a Nyquist-rate sampled quantizer as the amplitude of the input sinusoid changes, for a midtread 8-bit quantizer. The input is a 1 kHz sinusoid in a system with a bandwidth limited to 26 kHz. For such a comparison, a relationship for the SDR of a Nyquist-rate sampled quantizer across input amplitude is required, and we alter the standard formula for the SDR of a uniform, Nyquist-rate N-bit sampled quantizer to include a dependence on amplitude A [25], assuming the signal spans at least half of the quantization steps: SDR ¼ 1:76 þ 6:02N þ 20 log10 ðAÞ

(17)

ARTICLE IN PRESS B. Schell, Y. Tsividis / Signal Processing 89 (2009) 2013–2026

components (as in Fig. 11 and noted in [24]) but also for a wider band of distortion components. However, if the system bandwidth is increased from the 26 kHz used the above example, then more harmonics will be included in the distortion power and the SDR per-bit improvement will fall back to 6 dB=bit, though the SFDR will continue to improve at 9 dB=bit. A justification for a 9 dB=bit improvement is given in the next section.

SDR improvement when using a CT quantizer over a Nyquist−rate sampled quantizer (dB)

40 35

N=8

30 25 20 15

4. CT quantizing of Gaussian inputs

10 5 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 A

Fig. 13. The improvement in SDR of an 8-bit CT quantizer over a Nyquistrate sampled quantizer acting on a 1 kHz sinusoid with a bandwidth of 26 kHz as a function of amplitude.

40 SDR improvement when using a CT quantizer over a Nyquist−rate sampled quantizer (dB)

2023

35

A = 1 − 1/2N for each N

30 25 20 15 10 5 6

8

10

12

14

16

N Fig. 14. Improvement found using a CT quantizer over a Nyquist-rate sampled quantizer, showing an advantage that increases by approximately 3 dB=bit. The input is a 1 kHz sinusoid with a system bandwidth of 26 kHz. The amplitude A was adjusted to be 1  1=2N for each N.

A more complex class of signals to consider are those with a Gaussian probability density function in amplitude that is band-limited to frequency f o [12]. Bennett [26] found the exact description of band-limited Gaussian white noise passed through an N-bit CT quantizer. He defines the size of the quantizer’s non-overload region to be 4 times the rms magnitude of the input, making the probability of overload very small [27]. His analysis of inputs with a flat power spectrum can be extended to included all band-limited Gaussian inputs. The resulting expression for the normalized psd of the CT quantizer output is (see [12] for details and an explanation of terms) sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi " #   2 þ1 f 32 32 X 1 8f ¼ N (18) Oo exp 2 fo 4 p3 4N pjv3 j n¼1 n3 4N n2 p2 f o v3 Only in-band quantization distortion is of interest, where f of o . Over this range, the infinite sum in (18) is a weak function of N and the normalized psd is approximately proportional to 8N . This dependence gives a reduction of in-band distortion by 9 dB every time the number of bits in the quantizer is increased by one for any band-limited input whose amplitude obeys a Gaussian pdf. This improvement has been verified in simulation with results plotted in Fig. 15. Band-limited Gaussian signals were passed through a CT quantizer as well as a Nyquistrate sampled quantizer. The y-axis shows the ratio of the in-band distortion power in these two cases for various N. Although the input signal is more complex than a single sinusoid, the benefits of using a CT quantizer compared to

Fig. 13 shows an improvement of at least 10 dB to over 35 dB for large A. The rapid variations in the curve are due to the ‘tip’ waveform changing rapidly as the amplitude is varied, which greatly affects the SDR as previously illustrated. The improvement in SDR may be alternately viewed as a function of N. This is plotted in Fig. 14 where for each value of N the amplitude A was adjusted to A ¼ 1  1=2N using the same input and bandwidth as in Fig. 13. Fig. 14 shows the improvement of CT quantizing over Nyquistrate sampling and quantizing as the quantizer resolution is changed. The improvement increases by approximately 3 dB for each additional bit of quantizer resolution. Thus, whereas for Nyquist-rate sampled quantizers each additional bit of quantizer resolution yields a 6 dB=bit improvement in SDR [21], for CT quantizers each additional bit yields a 9 dB=bit improvement in SDR. Improvement of 9 dB=bit is seen not just for the first few distortion

Improvement in in−band distortion power of a CT quantizer over a Nyquist−rate sampled quantizer (dB)

30

25

20

15

10

5 3

4

5

6

7

8

N Fig. 15. Simulated improvement of in-band distortion for CT quantizers compared to Nyquist-rate sampling-and-quantizing vs. N for bandlimited Gaussian inputs.

ARTICLE IN PRESS B. Schell, Y. Tsividis / Signal Processing 89 (2009) 2013–2026

Amplitude of error signal for a CT quantizer output

2024

0.5

0

−0.5

Amplitude of error signal for a Nyquist−rate sampled quantizer output

0.05

0.055

0.06

0.065 Time (s)

0.07

0.075

0.08

0.055

0.06

0.065 Time (s)

0.07

0.075

0.08

0.5

0

−0.5 0.05

Fig. 16. Plot of error waveforms at the output of a 5-bit CT quantizer (top) and 5-bit Nyquist-rate sampled quantizer (bottom) given the same Gaussian input band-limited to 1 kHz.

a Nyquist-rate sampled quantizer remain. A visual illustration for this is shown in Fig. 16, which plots the error waveforms out of a CT quantizer and out of a Nyquist-rate sampled quantizer given the same Gaussian band-limited input, assuming that the output of the latter is held for the sampling period. As can be seen, the frequency content of the CT quantizer error waveform is significantly higher than that of the Nyquist-rate sampled quantizer, indicating that much of the error power at the output of a CT quantizer is out of band. Also, the error signal from a CT quantizer is limited in amplitude to within D=2, while the error from a sampled quantizer may have a much larger amplitude. Thus when comparing in-band distortion powers, a CT quantizer performs better than a Nyquist-rate sampled quantizer, having less inband distortion power, just as in the case of a single sinusoidal input. In light of (18) the 9 dB=bit improvement, now seen for both sinusoidal inputs as well as Gaussian inputs, can be traced to getting 6 dB=bit by halving the amplitude of the error signal, with the remaining 3 dB=bit traced to pushing the error power to frequencies beyond the band of interest. 5. Two-tone input A demonstration of a two-tone test is shown in Fig. 17 with the purpose to demonstrate yet another comparison in which the output spectra may be intuitively understood. Putting two tones at frequencies f 1 and f 2 through a non-linearity results in output tones at mf 1  nf 2 for integer m and n [22]. The top plot of Fig. 17 presents the output spectrum of a 4-bit CT quantizer given an input of tones at 1 and 1:1 kHz. The common period is 10 ms, corresponding to a frequency of 100 Hz, and it is seen that 100 Hz is the common tone spacing at the output.

The performance is compared to a sampled quantizer with a sampling rate slightly larger than the Nyquist rate; the output spectrum is given in the bottom plot of Fig. 17. Due to a sampling rate of 2:33 kHz that is non-harmonically related to either of the input tones, the output spectrum has many frequency spurs at 10 Hz spacing. The sampled quantizer output has a total in-band distortion power that is nearly 4 times larger than the total in-band distortion power in the CT quantizer output. Note that the frequency axis goes beyond f S =2, verifying the lack of aliasing in the CT quantizer, while aliases are present in the sampled quantizer spectrum. 6. Conclusions In this paper, we have presented an analysis of digital signal processors operating in continuous time. We have quantified the reduction of in-band quantization error comparing a CT ADC-DSP-DAC to a Nyquist-rate sampled system for certain inputs. The reduction of in-band error stems from a lack of sampling, and therefore lack of aliasing, in the proposed CT ADC-DSP-DAC. We have derived an equivalent system to simplify the analysis of a CT ADC-DSP-DAC system. The simplification reduces the comparison to conventional DSP systems to the study of quantizers and their output spectra over a given frequency range of interest. For single sinusoids the reduction of in-band quantization error varies depending on the amplitude, though for an 8-bit system the improvement is at least 10 dB for large amplitudes and relatively high frequencies, when few distortion components fall in-band. For Gaussian inputs, when appropriately scaled to fit the input range of the CT ADC, the reduction of in-band quantization error power for a system with an 8-bit CT ADC is near 25 dB. These

ARTICLE IN PRESS B. Schell, Y. Tsividis / Signal Processing 89 (2009) 2013–2026

2025

0 Rel. Power (dB)

−10

N=4

CT quantizer

−20 −30 −40 −50 −60 −70 0

200

400

600

800 1000 1200 Frequency (Hz)

1400

1600

1800

2000

Rel. Power (dB)

0 −10

N=4

Sampled quantizer Sampling freq. = 2.33 kHz

−20 −30 −40 −50 −60 −70 0

200

400

600

800 1000 1200 Frequency (Hz)

1400

1600

1800

2000

Fig. 17. Spectrum of CT quantizer output with N ¼ 4 for two-tone test using xðtÞ ¼ 0:15 sinð2p  1000tÞ þ 0:31 sinð2p  1100tÞ as input. Top: CT quantizer. Bottom: Sampled quantizer with f S ¼ 2:33 kHz. Note that this figure plots beyond f S =2 in frequency.

improvements stem from a CT ADC-DSP-DAC’s precise sensing of when the input crosses quantization level boundaries. Although the results presented used continuous-time PCM and Delta modulation versions of analog-to-digital converters, the processing techniques investigated are applicable to any continuous-time binary signals.

Acknowledgment The authors would like to thank Anuranjan Jha and Frank Zhang for helpful discussions. References [1] Y. Tsividis, Digital signal processing in continuous time: a possibility for avoiding aliasing and reducing quantization error, in: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. II, 2004, pp. 589–592. [2] Y. Tsividis, Continuous-time signal processing, Electronics Letters 39 (21) (October 2003) 1551–1552. [3] B. Schell, Y. Tsividis, A clockless ADC/DSP/DAC system with activitydependent power dissipation and no aliasing, ISSCC Digest of Technical Papers, San Francisco, February 2008, pp. 550–551. [4] B. Schell, Y. Tsividis, A continuous-time ADC/DSP/DAC system with no clock and with activity-dependent power dissipation, IEEE Journal of Solid-State Circuits 43 (11) (November 2008) 2472–2481. [5] D. Bruckmann, Design and realization of continuous-time wave digital filters, in: IEEE International Symposium on Circuits and Systems, Seattle WA, May 18–21, 2008, pp. 2901–2904. [6] Z. Zhao, V. Smolyakov, A. Prodic, Continuous-time digital signal processing based controller for high-frequency DC-DC converters, in: IEEE Applied Power Electronics Conference, Anaheim, February 2007, pp. 882–886. [7] H. Inose, T. Aoki, K. Watanabe, Asynchronous delta-modulation system, Electronics Letters 2 (3) (March 1966) 95–96. [8] J. Foster, T.-K. Wang, Speech coding using time code modulation, in: Proceedings of the IEEE SoutheastCon, vol. 2, 1991, pp. 861–863.

[9] E. Allier, G. Sicard, L. Fesquet, M. Renaudin, A new class of asynchronous A/D converters based on time quantization, in: Proceedings of the Ninth IEEE International Symposium on Asynchronous Circuits and Systems, Vancouver, May 2003, pp. 196–205. [10] F. Akopyan, R. Manohar, A.B. Apsel, A level-crossing flash asynchronous analog-to-digital converter, in: IEEE International Symposium on Asynchronous Circuits and Systems, March 13–15, 2006. [11] M.D. Lindermann, et al., Signal processing challenges for neural prostheses, IEEE Signal Processing Magazine (January 2008) 18–28. [12] B. Schell, Y. Tsividis, Analysis of continuous-time digital signal processors, in: IEEE International Symposium on Circuits and Systems, May 2007, pp. 2232–2235. [13] C.J. Kikkert, D.J. Miller, Asynchronous delta sigma modulation, in: Proceedings of the IREE, vol. 36, April 1975, pp. 83–87. [14] Y. Li, K. Shepard, Y. Tsividis, A continuous-time programmable digital FIR filter, in: Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, Vancouver, March 2005, pp. 138–143. [15] R. Steele, Delta Modulation Systems, Wiley, New York, 1975. [16] G. Lockhart, Digital encoding and filtering using delta modulation, The Radio and Electronic Engineer 42 (12) (December 1972) 547–551. [17] A. Peled, B. Liu, A new approach to the realization of nonrecursive digital filters, IEEE Transactions on Audio and Electroacoustics AU21 (6) (December 1973) 477–484. [18] B. Schell, Y. Tsividis, A low power tunable delay element suitable for asynchronous delays of burst information, IEEE Journal of SolidState Circuits 43 (4) (May 2008) 1227–1234. [19] L.B. Jackson, On the interaction of roundoff noise and dynamic range in digital filters, Bell System Technical Journal 49 (February 1970) 159–184. [20] A.G. Clavier, P.F. Panter, D.D. Grieg, Distortion in a pulse count modulation system, AIEE Transactions 66 (July 1947) 989–1005. [21] R.M. Gray, Quantization noise spectra, IEEE Transactions on Information Theory 36 (6) (November 1990) 1220–1244. [22] N. Blachman, The intermodulation and distortion due to quantization of sinusoids, IEEE Transactions on Acoustics, Speech, and Signal Processing 33 (6) (December 1985) 1417–1426. [23] B. Widrow, I. Kollar, M.-C. Liu, Statistical theory of quantization, IEEE Transactions on Instrumentation and Measurements 45 (April 1996) 353–361.

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[24] H. Pan, A. Abidi, Spectral spurs due to quantization in Nyquist ADCs, IEEE Transactions on Circuits and Systems—I 51 (8) (August 2004) 1422–1439. [25] N.S. Jayant, P. Noll, Digital Coding of Waveforms, Prentice-Hall, Englewood Cliffs, NJ, 1984.

[26] W.R. Bennett, Spectra of quantized signals, Bell System Technical Journal 27 (1948) 446–472. [27] A. Gersho, Principles of quantization, IEEE Transactions on Circuits and Systems CAS-25 (7) (July 1978) 427–436.