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Analysis of faults of integrated circuits with the JENATECH-inspection microscope
1008
World Abstracts on Microelectronics and Reliability
while the components are mounted on the bare side and soldered to the circuitry via unplated through-holes. Such soldered joints suffer from cracking whenever the board is exposed to a thermal cycling because of different thermal expansion.
Edge passivation and related electrical stability in silicon power devices. S. SALKALACHEN,N. H. KRISHNAN, S. KRISHNAN, H. B. SATYAMURTHYand K. S. SRINIVAS.IEEE Trans. Semiconductor Mfg 3(1), 12 (1990). Factors governing longterm stability of silicon power devices are discussed with particular reference to a major failure mechanism observed in a thyristor device. Analysis of I - V characteristics measured under various conditions of temperature and applied bias indicate that surface passivation procedures have a strong influence on leakage current. By employing an orthogonal array experiment, the curing process for edge passivant used on the silicon element was identified as a significant factor. When the optimized process parameters were used, remarkable improvements were observed in electrical stability and manufacturing yield of this device in conformance with postulated results. Inspection and data measurements for solder quality process control. J. ADAMS. Circuit Wld 16(1), 19 (1989). Solder quality is a critical issue in circuit board production. However, the manufacturing process of today has few built-in controls to ensure good solder quality. Instead, attention is only paid when a defect is found. The solution lies in the integration of inspection, test and process control. Now a new method, Scanned-Beam Laminography, takes 3-dimensional X-ray slices of solder joints, enabling thorough inspection of each joint. Special software algorithms measure and report the solder joint conditions, creating a system which provides real-time process control. Test chip based approach to automated diagnosis of CMOS yield problems. WES LUKASZEK, KAI G. GRAMBOW and WILLIE J. YARBROUGH. IEEE Trans. Semiconductor Mfg 3(1), 18 (1990). The following describes a design approach 3. C I R C U I T
AND
SYSTEMS
RELIABILITY,
RADC initiatives in CAE for reliability and maintainability. ANTHONY COPPOLA. Proc. Reliab. Maintainab. CAE Workshop, 6 (1988). Efforts by the USAF Rome Air Development Center in computer-aided engineering (CAE) for reliability and maintainability include the contracted development of CAE modules concerned with testability (the ability to detect and isolate failures), the in-house development and use of reliability analysis programs, and the development of software for computer-aided support of electronic modules. High-speed automatic test equipment enhances audio/video prgduction lines. TAMIO SAKAI. J. Electron. Engng, Jpn, 56 (September 1989). In the R&D field, automatic measuring systems that process large amounts of data have been used widely. These systems fulfil some engineering functions and are contributing to labor savings and industrial rationalization. In the production line as well, installation of automatic measuring systems has been keenly studied with an eye to saving labor in inspection and adjustment procedures. The Measure Corn system has proved to be particularly effective in the automatic measurement of audio and video equipment. Feedback approach to quality monitoring of a manufacturing process. JOHN R. ENGLISH, MURALI KRISHNAMURTHI and TEP SASTRI. Comput. ind. Engng 17(1-4), 303 (1989). This research represents a unique approach to quality monitoring of a process when data are autocorrelated. The effect of autocorrelated data is evaluated by modelling the manufacturing process as an autoregressive model of order one or
of, and experimental results obtained from, a unique test chip developed for the purpose of automated diagnosis of random defect dominated yield problems of CMOS ICs. Unlike test chips comprised of ad hoc collections of test structures, the test chip described here is based on the notion of systematic structural decomposition, employed to ensure complete sets of structures required for unambiguous identification of all structural features associated with electrical faults. Considerations related to test structure selection, sizing, layout, testing, and data analysis are discussed, and examples from rejected wafers are presented to illustrate the direct and straightforward way in which unambiguous diagnoses are obtained. Conclusions related to implementation of an expert system for automated CMOS process problem diagnosis employing the data obtained from this test chip are also summarized.
Analysis of faults of integrated circuits with the JENATECHinspection microscope. Uoo MUTZE. Jena Rev. 3, 118 (1989). This paper reports on experience made with the JENATECH-inspection in laboratory-based fault analysis during the development of IC fabrication processes. The wafer patterning process comprises several runs of the following sequence of operation: Cleaning--layer deposition--resist coating--aligning and exposure through contact or projection masks--resist development--etching-resist stripping. The various levels of an integrated circuit consist of semiconductor, insulating and metal films having thicknesses between 10 and 2.000 nm, so that thin-film interferences play a major part. At a thickness below 500 nm, even a silicon film is transparent and produces strong interference on insulators. Likewise, thickness irregularities of organic resist coats show up by their interference brightness. Circuit patterns and their defects may be regarded as a combination of different types of optical objects: • Amplitude objects (spectral reflectivity, film interferences) • Phase objects (relief surface, material phase jumps) • Polarization objects (textured films). MAINTENANCE
AND
REDUNDANCY
two. Statistical process control is utilized and evaluated as a technique to detect known process disturbance. Due to the observed weaknesses of the statistical process control techniques, the Kalman filter is proposed as a technique to eliminate the autocorrelation from the process data. A SIMNET simulation model for estimating system reliability. HAMDY A. TAHA and PABLO NUNO DE LA PARRA. Comput. ind. Engng 17(1-4), 317 (1989). A general SIMNET simulation model is developed for estimating system reliability. The input data to the model are comprised of the minimal cut sets of the block diagram representing the system. The time-to-failure of the (parallel-series) components may be described by different distributions. The model can be readily extended to include repair and maintenance of the components.
Quality function deployment (QFD) processes in an integrated quality information system. CHIA-HAO CHANG. Cornput. ind. Engng 17(1-4), 311 (1989). A general design of an integrated total quality information system involving the quality function deployment process is proposed in this paper. Data flow diagram is used to illustrate the structure of the information system. Within it, the quality function deployment process is discussed in detail. Bivariate mean residual life. K. R. MURALIDHARANNAIR and N. UNNIKRISHNAN NAIR. IEEE Trans. Reliab. 38(3), 362 (1989). This paper overviews some of the theoretical results concerning the mean residual life function used in reliability
World Abstracts on Microelectronics and Reliability
while the components are mounted on the bare side and soldered to the circuitry via unplated through-holes. Such soldered joints suffer from cracking whenever the board is exposed to a thermal cycling because of different thermal expansion.
Edge passivation and related electrical stability in silicon power devices. S. SALKALACHEN,N. H. KRISHNAN, S. KRISHNAN, H. B. SATYAMURTHYand K. S. SRINIVAS.IEEE Trans. Semiconductor Mfg 3(1), 12 (1990). Factors governing longterm stability of silicon power devices are discussed with particular reference to a major failure mechanism observed in a thyristor device. Analysis of I - V characteristics measured under various conditions of temperature and applied bias indicate that surface passivation procedures have a strong influence on leakage current. By employing an orthogonal array experiment, the curing process for edge passivant used on the silicon element was identified as a significant factor. When the optimized process parameters were used, remarkable improvements were observed in electrical stability and manufacturing yield of this device in conformance with postulated results. Inspection and data measurements for solder quality process control. J. ADAMS. Circuit Wld 16(1), 19 (1989). Solder quality is a critical issue in circuit board production. However, the manufacturing process of today has few built-in controls to ensure good solder quality. Instead, attention is only paid when a defect is found. The solution lies in the integration of inspection, test and process control. Now a new method, Scanned-Beam Laminography, takes 3-dimensional X-ray slices of solder joints, enabling thorough inspection of each joint. Special software algorithms measure and report the solder joint conditions, creating a system which provides real-time process control. Test chip based approach to automated diagnosis of CMOS yield problems. WES LUKASZEK, KAI G. GRAMBOW and WILLIE J. YARBROUGH. IEEE Trans. Semiconductor Mfg 3(1), 18 (1990). The following describes a design approach 3. C I R C U I T
AND
SYSTEMS
RELIABILITY,
RADC initiatives in CAE for reliability and maintainability. ANTHONY COPPOLA. Proc. Reliab. Maintainab. CAE Workshop, 6 (1988). Efforts by the USAF Rome Air Development Center in computer-aided engineering (CAE) for reliability and maintainability include the contracted development of CAE modules concerned with testability (the ability to detect and isolate failures), the in-house development and use of reliability analysis programs, and the development of software for computer-aided support of electronic modules. High-speed automatic test equipment enhances audio/video prgduction lines. TAMIO SAKAI. J. Electron. Engng, Jpn, 56 (September 1989). In the R&D field, automatic measuring systems that process large amounts of data have been used widely. These systems fulfil some engineering functions and are contributing to labor savings and industrial rationalization. In the production line as well, installation of automatic measuring systems has been keenly studied with an eye to saving labor in inspection and adjustment procedures. The Measure Corn system has proved to be particularly effective in the automatic measurement of audio and video equipment. Feedback approach to quality monitoring of a manufacturing process. JOHN R. ENGLISH, MURALI KRISHNAMURTHI and TEP SASTRI. Comput. ind. Engng 17(1-4), 303 (1989). This research represents a unique approach to quality monitoring of a process when data are autocorrelated. The effect of autocorrelated data is evaluated by modelling the manufacturing process as an autoregressive model of order one or
of, and experimental results obtained from, a unique test chip developed for the purpose of automated diagnosis of random defect dominated yield problems of CMOS ICs. Unlike test chips comprised of ad hoc collections of test structures, the test chip described here is based on the notion of systematic structural decomposition, employed to ensure complete sets of structures required for unambiguous identification of all structural features associated with electrical faults. Considerations related to test structure selection, sizing, layout, testing, and data analysis are discussed, and examples from rejected wafers are presented to illustrate the direct and straightforward way in which unambiguous diagnoses are obtained. Conclusions related to implementation of an expert system for automated CMOS process problem diagnosis employing the data obtained from this test chip are also summarized.
Analysis of faults of integrated circuits with the JENATECHinspection microscope. Uoo MUTZE. Jena Rev. 3, 118 (1989). This paper reports on experience made with the JENATECH-inspection in laboratory-based fault analysis during the development of IC fabrication processes. The wafer patterning process comprises several runs of the following sequence of operation: Cleaning--layer deposition--resist coating--aligning and exposure through contact or projection masks--resist development--etching-resist stripping. The various levels of an integrated circuit consist of semiconductor, insulating and metal films having thicknesses between 10 and 2.000 nm, so that thin-film interferences play a major part. At a thickness below 500 nm, even a silicon film is transparent and produces strong interference on insulators. Likewise, thickness irregularities of organic resist coats show up by their interference brightness. Circuit patterns and their defects may be regarded as a combination of different types of optical objects: • Amplitude objects (spectral reflectivity, film interferences) • Phase objects (relief surface, material phase jumps) • Polarization objects (textured films). MAINTENANCE
AND
REDUNDANCY
two. Statistical process control is utilized and evaluated as a technique to detect known process disturbance. Due to the observed weaknesses of the statistical process control techniques, the Kalman filter is proposed as a technique to eliminate the autocorrelation from the process data. A SIMNET simulation model for estimating system reliability. HAMDY A. TAHA and PABLO NUNO DE LA PARRA. Comput. ind. Engng 17(1-4), 317 (1989). A general SIMNET simulation model is developed for estimating system reliability. The input data to the model are comprised of the minimal cut sets of the block diagram representing the system. The time-to-failure of the (parallel-series) components may be described by different distributions. The model can be readily extended to include repair and maintenance of the components.
Quality function deployment (QFD) processes in an integrated quality information system. CHIA-HAO CHANG. Cornput. ind. Engng 17(1-4), 311 (1989). A general design of an integrated total quality information system involving the quality function deployment process is proposed in this paper. Data flow diagram is used to illustrate the structure of the information system. Within it, the quality function deployment process is discussed in detail. Bivariate mean residual life. K. R. MURALIDHARANNAIR and N. UNNIKRISHNAN NAIR. IEEE Trans. Reliab. 38(3), 362 (1989). This paper overviews some of the theoretical results concerning the mean residual life function used in reliability