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Analysis of surface mount thermal and thermal stress performance
806
World Abstracts on Microelectronics and Reliability
contamination probably accelerate the general corrosion tendencies of the fluoride contaminated aluminum metallization. Combinations of various techniques for removing the fluorine such as oxygen plasma treatment, ultraviolet/ozone treatment, and deionized water rinsing were evaluated with no success.
More than a decade of the non-saturating autoclave as a highly accelerated stress technique for evaluating the reliability of nonhermetic microelectronic components. N. SINNADURAL Microelectron. Reliab. 23 (5), 833 (1983). By virtue of its capacity for highly accelerated ageing, the non-saturating autoclave may be regarded as an economically attractive reliability assessment technique. It is apparent that experiments employing the technique are proceeding at. various locations and will in due course add to the information on its scope and limitations. Effects of accelerated temperature testing on the low-frequency noise of planar NPN transistors. N. D. STOJADINOVIC.Microelectron. Reliab. 23 (5), 899 (1983). In a recent paper, Khobare has concluded that accelerated temperature testing of planar NPN transistors does not affect the low-frequency noise. However, the present experimental evidence shows that this conclusion is not valid when planar NPN transistors comprise emitter edge dislocations created in emitter phosphorus diffusion. Namely, in this case accelerated temperature testing of planar NPN transistors may cause catastrophical increase of the low-frequency noise, thus leading to failures. Test bar checks reliability of STL semicustom logic arrays. JOEL P. LEBLANC, JR. Electronics, 155 (1 December 1983). Special integrated circuit with built-in worst-case conditions checks Schottky TTL process steps and IC parameters. Printed board assembly cleanliness--standards, practice and reliability considerations. J. R. TAYLOR. Circuit World 10 (2), 4 (1984). The transition to complex printed board assemblies in modern high technology equipment is described. These low voltage, densely packed PBAs with their decreasing insulation paths, manufactured for greatest speed with highly activated solder fluxes, demand both awareness and action to achieve the degree of cleanliness compatible with reliability requirements. This paper sets forth activities under way in Australia to define and adopt cleanliness Standards for use throughout the nation's manufacturing industry. It identifies and defines cleanliness and methods used to achieve and measure contamination that is introduced during PBA manufacture. Fatigue life of leadless chip carrier solder joints during power cycling. WERNER ENGELMAIER. IEEE Trans, Components Hybrids Mfy Technol. Chmt-6 (3), 232 (September 1983). An analytical method is described which provides estimates to first order of the number of either power or environmental cycles leading to solder joint failure. Various parameter variations such as solder joint height, ceramic chip carrier (CCC) size, printed circuit substrate (PCS) material, etc. are investigated and discussed and sample estimates for a 0.65 x 0.65-in CCC are given. The effect of high dissipation components on the solder joints of ceramic chip carriers attached to thick film alumina substrates. JIM T. LYNCH, M. R. FORD and ALBERTOBOETTI. IEEE Trans. Components Hybrids Mfg Technol. Chmt-6 (3), 237 (September 1983). The effects of power cycling and powered high temperature storage on chip carriers solder attached to thick film alumina substrates are compared with those of conventional temperature cycling and high temperature storage. Although the high temperature storage tests gave a similar deterioration in torque strength compared with unstressed controls, power cycling produced dramatically lower values than chamber temperature cycling with the
same upper temperature. The power cycling failure mechanism is seen to be a direct result of the thermal gradient changes between the chip carrier and the substrate resulting in plastic deformation and subsequent fatigue cracking. Possible solutions to the problem are reviewed.
Analysis of surface mount thermal and thermal stress performance. DEBRA L. WALLER,LESLIER. FOX and ROBERTJ. HANNEMANN.I EEE Trans. Components Hybrids Mfq Technol. Chmt-6 (3), 257 (September 1983). Ongoing analysis of leadless ceramic devices surface mounted to epoxy-glass is described. Finite element (FE) model results for thermal resistance as a function of airspeed, carrier size and spacing, and heatsinking are given. An overview of the thermal stress problem, emphasizing fatigue test design, is presented. The rationales used in choosing thermal cycle amplitudes, methods of heat transfer, definitions of failure, test frequency, and desired cycles to failure are compared to current industry practice and discussed in the context of their impact on test results. Updating of CMOS reliability. P. BRAMBILLA,F. FANTINI and G. MATTANA.Microelectron. Reliab. 23 (4), 761 (1983). Updated results of massive life tests on CMOS are reported. The failure rate derived from laboratory conditions is extrapolated for long life use and compared with field results. Failure mechanism distribution is also reported. Printed-circuit-board assembly picks up on automation. CHARLES-HENRIMANGINand NALVATORED'AGOSTINO.Electronics 171 (12 January 1984). New developments in robotics, controllers, and integration software make flexible totally automated assembly economical for pc-board stuffing. Defect analysis system speeds test and repair of redundant memories. M. TARR, D. BOUDREAUand R. MURPHY. Electronics 175 (12 January 1984). Algorithms can efficiently pinpoint fault sites for repair as well as weed out unrepairable chips early in the test. Investigation of information loss mechanisms in EPROMs. D. BERTOTTI, F. FANTINI and C. MORANDI. Microelectron. Reliab. 23 (4), 717 (1983). The paper reports the results of accelerated life tests on p- and n-channel EPROMs, and compares the indication thus obtained with data from the field. The results of our experiments demonstrate that, even in recent production, contaminant diffusion significantly affects device reliability. The presence of this mechanism invalidates any effort to draw reliability information from lognormal plots of the cumulative distribution of the times to failure of all the bits in a device or in a set of devices: only the times to first bit failure for the devices of a batch should be considered. Furthermore, charge loss and contaminant diffusion seem to be uncorrelated processes. From the point of view of reliability it seems reasonable to conclude that, in spite of their increased complexity, 16 K n-channel EPROMs promise to be more reliable than 2 K devices, thanks probably to the improved technology. Effect of HCI and CI2 on Pd inlay coupons and Pd connector contacts. EDWARD S. SPROLES,JR. and SATYA P. SHARMA. IEEE Trans. Components Hybrids Mfg Technol. Chmt-6 (3), 343 (September 1983). Field exposure studies indicate that a resistive palladium chloride film may grow on Pd coupons when the ambient contains both high relative humidity (RH) and chlorine. This behaviour raises a concern about the use of palladium in separable connectors. Most connectors are shielded systems, and the contacts are subject to wipe on mating. Therefore contact resistance probe measurements on coupon surfaces may not be representative of the behaviour of connector contacts. A study on a moderately shielded connector system was initiated to compare the effects of
World Abstracts on Microelectronics and Reliability
contamination probably accelerate the general corrosion tendencies of the fluoride contaminated aluminum metallization. Combinations of various techniques for removing the fluorine such as oxygen plasma treatment, ultraviolet/ozone treatment, and deionized water rinsing were evaluated with no success.
More than a decade of the non-saturating autoclave as a highly accelerated stress technique for evaluating the reliability of nonhermetic microelectronic components. N. SINNADURAL Microelectron. Reliab. 23 (5), 833 (1983). By virtue of its capacity for highly accelerated ageing, the non-saturating autoclave may be regarded as an economically attractive reliability assessment technique. It is apparent that experiments employing the technique are proceeding at. various locations and will in due course add to the information on its scope and limitations. Effects of accelerated temperature testing on the low-frequency noise of planar NPN transistors. N. D. STOJADINOVIC.Microelectron. Reliab. 23 (5), 899 (1983). In a recent paper, Khobare has concluded that accelerated temperature testing of planar NPN transistors does not affect the low-frequency noise. However, the present experimental evidence shows that this conclusion is not valid when planar NPN transistors comprise emitter edge dislocations created in emitter phosphorus diffusion. Namely, in this case accelerated temperature testing of planar NPN transistors may cause catastrophical increase of the low-frequency noise, thus leading to failures. Test bar checks reliability of STL semicustom logic arrays. JOEL P. LEBLANC, JR. Electronics, 155 (1 December 1983). Special integrated circuit with built-in worst-case conditions checks Schottky TTL process steps and IC parameters. Printed board assembly cleanliness--standards, practice and reliability considerations. J. R. TAYLOR. Circuit World 10 (2), 4 (1984). The transition to complex printed board assemblies in modern high technology equipment is described. These low voltage, densely packed PBAs with their decreasing insulation paths, manufactured for greatest speed with highly activated solder fluxes, demand both awareness and action to achieve the degree of cleanliness compatible with reliability requirements. This paper sets forth activities under way in Australia to define and adopt cleanliness Standards for use throughout the nation's manufacturing industry. It identifies and defines cleanliness and methods used to achieve and measure contamination that is introduced during PBA manufacture. Fatigue life of leadless chip carrier solder joints during power cycling. WERNER ENGELMAIER. IEEE Trans, Components Hybrids Mfy Technol. Chmt-6 (3), 232 (September 1983). An analytical method is described which provides estimates to first order of the number of either power or environmental cycles leading to solder joint failure. Various parameter variations such as solder joint height, ceramic chip carrier (CCC) size, printed circuit substrate (PCS) material, etc. are investigated and discussed and sample estimates for a 0.65 x 0.65-in CCC are given. The effect of high dissipation components on the solder joints of ceramic chip carriers attached to thick film alumina substrates. JIM T. LYNCH, M. R. FORD and ALBERTOBOETTI. IEEE Trans. Components Hybrids Mfg Technol. Chmt-6 (3), 237 (September 1983). The effects of power cycling and powered high temperature storage on chip carriers solder attached to thick film alumina substrates are compared with those of conventional temperature cycling and high temperature storage. Although the high temperature storage tests gave a similar deterioration in torque strength compared with unstressed controls, power cycling produced dramatically lower values than chamber temperature cycling with the
same upper temperature. The power cycling failure mechanism is seen to be a direct result of the thermal gradient changes between the chip carrier and the substrate resulting in plastic deformation and subsequent fatigue cracking. Possible solutions to the problem are reviewed.
Analysis of surface mount thermal and thermal stress performance. DEBRA L. WALLER,LESLIER. FOX and ROBERTJ. HANNEMANN.I EEE Trans. Components Hybrids Mfq Technol. Chmt-6 (3), 257 (September 1983). Ongoing analysis of leadless ceramic devices surface mounted to epoxy-glass is described. Finite element (FE) model results for thermal resistance as a function of airspeed, carrier size and spacing, and heatsinking are given. An overview of the thermal stress problem, emphasizing fatigue test design, is presented. The rationales used in choosing thermal cycle amplitudes, methods of heat transfer, definitions of failure, test frequency, and desired cycles to failure are compared to current industry practice and discussed in the context of their impact on test results. Updating of CMOS reliability. P. BRAMBILLA,F. FANTINI and G. MATTANA.Microelectron. Reliab. 23 (4), 761 (1983). Updated results of massive life tests on CMOS are reported. The failure rate derived from laboratory conditions is extrapolated for long life use and compared with field results. Failure mechanism distribution is also reported. Printed-circuit-board assembly picks up on automation. CHARLES-HENRIMANGINand NALVATORED'AGOSTINO.Electronics 171 (12 January 1984). New developments in robotics, controllers, and integration software make flexible totally automated assembly economical for pc-board stuffing. Defect analysis system speeds test and repair of redundant memories. M. TARR, D. BOUDREAUand R. MURPHY. Electronics 175 (12 January 1984). Algorithms can efficiently pinpoint fault sites for repair as well as weed out unrepairable chips early in the test. Investigation of information loss mechanisms in EPROMs. D. BERTOTTI, F. FANTINI and C. MORANDI. Microelectron. Reliab. 23 (4), 717 (1983). The paper reports the results of accelerated life tests on p- and n-channel EPROMs, and compares the indication thus obtained with data from the field. The results of our experiments demonstrate that, even in recent production, contaminant diffusion significantly affects device reliability. The presence of this mechanism invalidates any effort to draw reliability information from lognormal plots of the cumulative distribution of the times to failure of all the bits in a device or in a set of devices: only the times to first bit failure for the devices of a batch should be considered. Furthermore, charge loss and contaminant diffusion seem to be uncorrelated processes. From the point of view of reliability it seems reasonable to conclude that, in spite of their increased complexity, 16 K n-channel EPROMs promise to be more reliable than 2 K devices, thanks probably to the improved technology. Effect of HCI and CI2 on Pd inlay coupons and Pd connector contacts. EDWARD S. SPROLES,JR. and SATYA P. SHARMA. IEEE Trans. Components Hybrids Mfg Technol. Chmt-6 (3), 343 (September 1983). Field exposure studies indicate that a resistive palladium chloride film may grow on Pd coupons when the ambient contains both high relative humidity (RH) and chlorine. This behaviour raises a concern about the use of palladium in separable connectors. Most connectors are shielded systems, and the contacts are subject to wipe on mating. Therefore contact resistance probe measurements on coupon surfaces may not be representative of the behaviour of connector contacts. A study on a moderately shielded connector system was initiated to compare the effects of