Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions

Microelectronics Journal 43 (2012) 358–363

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Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions Dheeraj Sharma, Santosh Kumar Vishvakarma n Nanoscale Devices, VLSI/ULSI Circuit and System Design Lab., Electrical Engineering Discipline, School of Engineering, Indian Institute of Technology (IIT), Indore 452017, Madhya Pradesh, India

a r t i c l e i n f o

a b s t r a c t

Article history: Received 1 November 2011 Received in revised form 8 February 2012 Accepted 9 February 2012 Available online 6 March 2012

In this paper, we have introduced an analytical subthreshold and strong inversion 3D potential model for rectangular gate (RecG) gate-all-around (GAA) MOSFET. The subthreshold and strong inversion potential distribution in channel region of a RecG MOSFET is obtained respectively by solving 3D Laplace and 3D Poisson equations. The assumed parabolic potential distribution along the z-axis in channel direction is appropriately matched with 3D device simulator after consideration of z-depended characteristic length in subthreshold region. For accurate estimation of short channel effects (SCE), the electrostatics near source and drain is corrected. The precise gate-to-gate potential distribution is obtained after consideration of higher order term in assumed parabolic potential profile. The model compares well with numerical data obtained from the 3D ATLAS as a device simulator and deckbuild as an interactive runtime of Silvaco Inc. & 2012 Elsevier Ltd. All rights reserved.

Keywords: Rectangular gate (RecG) Gate-all-around (GAA) MOSFET Potential Characteristic length Subthreshold and strong inversion regions

1. Introduction The single gate bulk metal oxide semiconductor field effect transistor (MOSFET) is almost at the end of the roadmap because as scaling the close proximity between source and drain reduces the capability of gate electrode to control the potential distribution and the bulk-silicon transistor is facing serious issues such as short channel effects (SCE) that start plaguing the bulk MOSFETs technology [1]. The main short channel effects are threshold voltage roll-off (due to charge sharing), degradation of subthreshold swing and drain induced barrier lowering (DIBL) effect. As a result, the off state current increases and the ON–OFF current ratio are degraded [2]. Therefore, the device performance is worsened and it seems to replace bulk single gate MOSFET by multigate nanoscale MOSFETs. The multiple-gate MOSFETs (MuGFETs) offer superior control of channel due to multiple gates that suppress SCE and leakage currents [3]. This opens the opportunity for further down scaling of device and supply voltage by multigate transistor [4]. The use of strained silicon, a metal gate and high-k dielectric as the gate insulator can further enhance the current drive of the device. The natural length can be reduced by decreasing the gate oxide

n

Corresponding author. E-mail addresses: [email protected] (D. Sharma), [email protected], [email protected] (S. Kumar Vishvakarma). 0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2012.02.001

thickness, by using high-k gate dielectric instead of SiO2. The circuit performance also benefits from novel gate stack material, reduces parasitic capacitance and hole mobility improvement. Therefore, the MuGFETs are strong candidates for replacing conventional single gate MOSFET in future [5]. The gate-all-around (GAA) device such as circular gate (CirG) [6–8], square gate (SqG) [9–11] and rectangular gate (RecG) offers excellent electrostatic control of the channel and robustness against SCE. The GAA device has higher current drivability, ideal subthreshold swing and mobility enhancement at a certain crystal orientation are achieved. The improvement in performance of device is due to gate electrode wrapped around four sides of device [12], which gives volume inversion, carriers are not confined near to Si/SiO2 interface [13], no floating body effect, larger number of equivalent number of gate (ENG) and reduced natural length as compare to single gate and double gate MOSFETs [14]. The disadvantage of the GAA device is the small drain current drivability because the wire channel width is very narrow. To overcome the problem of small drain current, the multiple surrounding gate channels can be stacked on top of one another, while sharing common gate, source and drain. Therefore, the current drive per unit will be enhanced [15]. An analytical modeling for 3D potential distribution in subthreshold and strong inversion regions is presented for lightly doped RecG GAA MOSFET. The circular gate (CirG), square gate (SqG) and ti(ple)-gate MOSFET can be considered as a special case of modeled RecG MOSFET. The paper is organized as follows: in

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Section 2, we describe the device electrostatics. We deal with long channel, short-channel and precise gate-to-gate potential modeling in Section 3. For intact range of operation modeling of strong inversion region is presented in Section 4. Finally, the main conclusions will be drawn in Section 5.

2. Device electrostatics The proposed RecG device modeled in this paper has gate length L¼ 30 nm, oxide thickness tox ¼1.5 nm, silicon height h¼24 nm, silicon width w ¼12 nm and oxide relative dielectric constant Eox ¼ 7. The doping density of the p-type silicon body is NA ¼ 1015 cm3 . The gate material has near-midgap metal work function 4.53 eV. The Schottky contacts have work function of 4.17 eV (near to that of n þ silicon) assumed for source and drain. To facilitate the modeling, the gate insulator is replaced by an electrostatically equivalent silicon layers with thickness t 0ox ¼ t ox Esi =Eox , where Esi is the relative permittivity of silicon [16]. Figs. 1 and 2 show the cross-sectional and 3D ATLAS [17] views of RecG MOSFET, where the middle yellow portion is silicon having w as a width and h as a height. The blue portion of figure is SiO2 having thickness of t 0ox wrapped around the silicon portion. The extended portion of channel act as the Schottky contacts. In figures, x-axis, y-axis and z-axis are the axis of coordinates and origin (0,0,0) is situated at source end of channel length as indicated in diagram, where x-axis in the direction of width, y-axis in the direction of height and z-axis is perpendicular to the (x,y) plane in the direction of channel length, where a ¼ w þ 2t 0ox is a width of extended body including the gate insulator, and b ¼ hþ 2t 0ox is a height of extended body including the gate insulator.

3. Subthreshold potential distribution The analysis of effect created by source and drain electric field in channel region is very important in subthreshold region as continuous reduction in dimensions of transistors. In subthreshold domain, we are dealing with negligible body charge density and 3D Laplace equation for potential distribution [18]. To account for short channel effect, additional functional form is used near source and drain.

y-axis

Fig. 2. 3D view of rectangular gate (RecG) GAA MOSFET. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)

3.1. Long channel potential distribution In the presented model, we have taken the assumption of parabolic potential distribution in the directions perpendicular to the gates in the middle portion of channel. Therefore, the potential distribution in channel region, not too close to the source and drain, can be written as "   #"   # 2x 2 2y 2 ^ fðx,y,zÞ ¼ f ð0; 0,zÞ 1 ð1Þ 1 þ V gs V FB , a b where x, y, and z are the axis of coordinates, Vgs is a gate-to-source ^ ð0; 0,zÞ ¼ fð0; 0,zÞV gs þ V voltage, VFB is flat band voltage and f FB is potential distribution along the z-axis. As we know that the 3D 2 Laplace equation can be written as r ðfðx,y,zÞÞ ¼ 0. Taking the second derivatives of Eq. (1) with respect to x, y, z in 3D Laplace equation, we obtained " # 2 ^ ð0; 0,zÞ @2 f 32ðx2 þ y2 Þ8ða2 þb Þ ^ ð0; 0,zÞ ¼ 0: ð2Þ þ f 2 2 @z2 a2 b 4ðx2 b þ y2 a2 Þ þ 16x2 y2 To obtain the potential distribution along the z-axis using x¼0 and y¼0 in (2), we got ^ ð0; 0,zÞ f ^ ð0; 0,zÞ @2 f  ¼ 0: 2 @z l2

b

x-axis

h (0,0,0) w

a Fig. 1. Cross-sectional diagram of rectangular gate (RecG) GAA MOSFET. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)

ð3Þ

In (3) l is the characteristic length of field penetration from source/ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi drain into the device body and is given as l ¼ b= 8ð1 þ AR2 Þ, where AR ¼ ðb=aÞ is the aspect ratio of device. Using boundary conditions, f^ ð0; 0,0Þ ¼ V bi V gs þV FB and f^ ð0; 0,LÞ ¼ V bi V gs þV FB þ V ds , where Vbi is the built-in voltage at the two contacts and Vds is the drain-tosource voltage. After solving the differential equation (3), the following solution for center potential given as:   hzi Lz þ ðV bi V gs þ V FB þ V ds Þ sinh ðV bi V gs þ V FB Þ sinh l l   f^ ð0; 0,zÞ ¼ : L sinh l ð4Þ

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0.85 Model Model 3D ATLAS ATLAS 3D

Potential (V)

0.75

ForH=24nm H=24nm For 0.65 For For H=12nm H=12nm 0.55

0.45 0

5

10

15 Distance (nm)

20

25

30

Fig. 3. Comparison of modeled and numerical simulation of potential distribution along the z-axis.

Fig. 4. Comparison of modeled and numerical simulation of potential distribution along the z-axis.

Combined with (1), expression (4) gives full 3D potential distribution in the device body for long channel. Fig. 3 shows potential distribution along the z-axis and our analysis found that the difference between modeled and 3D ATLAS with few millivolts throughout the channel length. The effect is enhanced when width and height is comparable to channel length as shown in figure. To overcome this issues related to SCE, we introduce z-dependent l in the following section.

3.2. Short-channel potential distribution The long channel potential model for the potential is only valid for long channel device, even though it is obtained from the 3D Laplace equation. This arise from the fact that the parabolic approximation assumed to solve (1) is not appropriate assumption especially close to the source and drain contacts where the potential starts to flatten out in the (x,y) plane. Hence, we got a mismatch along the source and drain axis. To rectify this error, we have introduced two auxiliary boundaries condition by introducing a z-dependent l 

lðzÞ ¼ lc þ a z

 L 2 , 2

ð5Þ

where lc and a are the bias-dependent parameters derived from ^ ð0; 0,L=2Þ and the electrical field E at the the center potential f s c center of the source (0,0,0) as follows:

lc ¼ l

  L ¼ 2

2

L

3 V ds V V þ V þ gs FB bi 1 6 2 7 7  2 cosh 6 4  5 L ^ f 0; 0, V gs þ V FB 2

ð6Þ

and

a¼

   2 V bi V gs þ V FB lc : L Es

^ ð0; 0,L=2Þ and the electrical field E was obtained The value of f s c from the conformal technique [19]. Hence, the expression for potential distribution along the z-axis considered the effect of

Fig. 5. Effect of scaling on device center potential distribution.

z on l is     Lz z þ ðV bi V gs þ V FB þ V ds Þ sinh ðV bi V gs þV FB Þ sinh lðzÞ lðzÞ   : f^ ð0; 0,zÞ ¼ L sinh lðzÞ

ð7Þ ^ ð0; 0,zÞ in (1) and taking x ¼ y ¼ 0 Using the expression (7) of f gives the fð0; 0,zÞ along the z-axis. In Fig. 4 the excellent agreement has been achieved for potential distribution along the z-direction at different values of Vds and Vgs. Fig. 5 shows the effect of channel length variation on center potential obtained from conformal mapping techniques. It is observed that the center potential is constant for channel length greater than 60 nm and variation is occurred for channel length lesser than 60 nm. The quite satisfactory agreement was obtained with the 3D ATLAS. 3.3. Precise gate-to-gate potential modeling for RecG GAA MOSFET The center potential distribution from (7) can be used in (1) to obtain the gate-to-gate potential distribution. But, the obtained gate-to-gate potential distribution by proposed model does not

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exactly follow the parabolic distribution along the gate-to-gate direction. For more precise gate-to-gate distribution, we need to consider higher order term in (1). Therefore, the precise gate-togate potential distribution can be modeled as "  2 !  2 ! 2x 2y fðx,y,zÞ ¼ f^ ð0; 0,zÞ bsub 1 1 a b  4 !  4 !# 2x 2y 1 þ ðV gs V FB Þ: þ gsub 1 ð8Þ a b

device center (0,0,L/2) for V ds ¼ V gs ¼ 0 V is simulated and modeled in Fig. 6. Fig. 6 shows modeled and numerical simulation of potential distribution along the direction of x-axis and y-axis, when we have considered the precise gate-to-gate potential modeling for RecG MOSFET.

Note that in expression (8), we have included only the fourth order term in the assumed potential distribution given in expression (1), where bsub and gsub are constant. To estimate the numerical value of bsub and gsub , use the 3D Laplace equation r2 ðfðx,y,zÞÞ ¼ 0. At center point (0,0,z) the value of bsub þ gsub ¼ 1. Now, the bsub can be obtained from (8) and 3D Laplace equation as  1 0 10 ! ^ 0; 0, L   @2 f 2 2 B CB 1 a b 2 C B 1 C: CB ð9Þ bsub ¼ A 2 @ L A@ 8 @z2 a2 þ b ^ f c 0; 0, 2

The approximation of parabolic potential distribution is not applicable near to source and drain due to flattening of potential in (x,y) cross-sectional. This flattening of potential occurred up to characteristic distance of source and drain that can be defined as ls ¼ lð0Þ ¼ lc þ aðL=2Þ2 and shown by equipotential (gray) area in upper left cross-section of Fig. 7. The flattening of potential in the (x,y) plane along the x-axis follow up to width a0 ðzÞ ¼ w½1ðz=ls Þ near to source and a0 ðzÞ ¼ w½1ððLzÞ=ls Þ near to drain. In the case of flattening of potential in the (x,y) plane along the y-axis follow up to width b0 ðzÞ ¼ h½1ðz=ls Þ near to source and b0 ðzÞ ¼ h½1ððLzÞ=ls Þ near to drain. Hence, the modified potential distribution for z o ls and z 4Lls can be expressed as follows fðx,y,zÞ ¼ fð0; 0,zÞ in equipotential (gray) area, and outside this equipotential (gray) area the potential profile of (1) need to suitably scaled such that it exactly match with potential profile of gray area. After scaling the potential distribution can be written as

Now, the second derivative of central potential can be obtained from (4) as  1 0 ^ 0; 0, L @2 f B þ V FB Þ 2 C B C ¼ ðV bi V gs  : ð10Þ @ A L @z2 2 l cosh 2l

3.4. Potential distribution near to source and drain

From (9) and (10) the expression for bsub can be obtained as 0 10 1 !   2 B CBV bi V gs þV FB C 1 a2 b 1 B  CB  C : ð11Þ bsub ¼ 2 @ L A@ 2 L A 8 a2 þ b f^ c 0; 0, l cosh 2 2l

3 2 4ðx2 b þ y2 a2 Þ 16x2 y2 1 þ 6 2 7 2 2 a2 b 7 a b fðx,y,zÞ ¼ f^ ð0; 0,zÞ6 6 7 þ ðV gs V FB Þ: 4 5 a0 ðzÞb0 ðzÞ 1 1 ab

For short channel device, taking z-dependent l expression from (5) to (7) and then the expression of bsub for V ds ¼ 0 can be written as 0 10 1 !   2 2 B C B C 1 a b B 1 B V bi V gsþ V FB C C bsub ¼ A@ 2 A 2 @ 2 L L 8 a þb f^ c 0; 0, lc cosh 2 2lc       L L  coth : ð12Þ 1 þ aL 2 coth

However, in the central device region defined as ls rz r Lls , the expression from (1) to (7) will be applicable as shown by equipotential area in upper right cross-section of Fig. 7. Fig. 8 shows matching of modeled and numerical simulation of potential distribution along gate-to-gate direction when the distance along the z-axis is less than characteristic distance of device obtained from (5). The flattening of potential in the (x,y) plane follows up to the width a0 ðzÞ ¼ w½1ðz=ls Þ along the x-axis and b0 ðzÞ ¼ h½1ðz=ls Þ along the y-axis near to source and after that the potential distribution follows parabolic nature of expression (13).

lc

lc

The value of gsub can be obtained from bsub þ gsub ¼ 1 for both the cases. The calculated value of bsub and gsub from (12) gives precise gate-to-gate potential distribution along the gate-to-gate direction. The potential distribution along the x-axis and y-axis at

Fig. 6. Comparison of modeled and numerical simulation of potential distribution along gate-to-gate.

2

ð13Þ

Fig. 7. Longitudinal cross-section of the device along the channel axis with schematic contours plot in two different (x,y) planes.

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Potential(V) tential(V) V) Potential(V)

1 Model

0.95 0.95

3D ATLAS

0.9 0.9

0.85 0.85 x axis x iaxis 0.8 0.8

Fig. 8. Comparison of modeled and numerical simulation of potential distribution near to source at L=8.

y axis y axis

0.75 -12

-8

-4

0 Distance (nm)

4

8

12

Fig. 9. Comparison of modeled and numerical simulation of potential distribution along gate-to-gate at L=2 and Vgs ¼ 0.7 V.

4. Strong inversion modeling To model the device in strong inversion region, we need to deal with 3D Poisson equation instead of 3D Laplace equation. The charge density comprises electrons, holes, positively and negatively ionized immobile ions (donor and acceptor). This concentration of charge depends on the impurity doping level. The highly doped body (N A 51016 cm3 [20]) has adverse effect on mobility [21] and random dopant density fluctuation [22]. Therefore, we consider a lightly doped silicon body for RecG MOSFET. For simplicity of derivation, we choose only electron density as mobile charge. The electrostatics potential in device is considered as "  2 !  2 ! 2x 2y fðx,y,zÞ ¼ f^ ð0; 0,zÞ bstr 1 1 a b ! !#  4  4 2x 2y 1 þ ðV gs V FB Þ: þ gstr 1 ð14Þ a b Further, in (14) we have assumed the parabolic potential distribution, where bstr and gstr are constant. At center point (0,0,z) the value of bstr þ gstr ¼ 1. The 3D Poisson equation along the Si body takes the following form with only charge (electron) term: " # qn2i eðfðx,y,zÞ=V Th Þ , ð15Þ r2 ðfðx,y,zÞÞ ¼ NA Esi where VTh is the thermal potential, ni is the silicon intrinsic concentration. The body doping, NA, is taken as 1015 cm3 which is much smaller than ni eðfðx,y,zÞ=V Th Þ . We consider only the n-MOSFET with ðfðx,y,zÞ=V Th Þ b1, so the density of hole is negligible ^ ð0; 0,zÞ=@z2 ¼ 0 [23]. In strong inversion, we can assume that @2 f for center region of device. From Eq. (15) at (x,y,z) ¼(0,0,z) the value of bstr can be obtained as !  ðf^ ð0;0,zÞ þ V gs V FB Þ=V ! 2  Th qn2i a2 b 1 e bstr ¼ : ð16Þ 2 ^ 2 N A Esi 8ða þ b Þ f ð0; 0,zÞ

written as 2

d fðx,zÞ 2

dx

"

# qn2i eðfðx,zÞ=V Th Þ : ¼ NA Esi

ð18Þ

Integrating (18) once with symmetry boundary condition dfðx,zÞ= dx9x ¼ 0 ¼ 0, we obtain sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 dfðx,zÞ 2kTni qfðx,zÞ=kT qfð0,zÞ=kT ¼7 ðe e Þ, ð19Þ dx Esi NA where the positive sign applies for 0 r x r w=2 and the negative sign for w=2 r x r0. Here, fð0,zÞ is the potential at the center of the silicon film. Integrating again then the potential along the x-axis is obtained as 0 0sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 11 q2 n2i 2kT @ ðq f ð0,zÞ=2kTÞ ð20Þ ln cos@ e fðx,zÞ ¼ fð0,zÞ xAA: q 2Esi kTN A The potential at x ¼ w=2 can be written as 0 0sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 11 w  q2 n2i 2kT @ w ln cos@ eqfð0,zÞ=2kT AA: f ,z ¼ fð0,zÞ 2 q 2 2Esi kTN A The boundary condition at the Si–SiO2 interfaces w  V gs V FB f ,z d f ðx,zÞ 2 Eox ¼ 7 Esi : dx t ox w

ð21Þ

ð22Þ

x¼ 72

Here VFB is the work function difference between the gate electrode and intrinsic silicon. The center potential obtained as 0.77 V from (20) to (21) is nicely matched with the 3D ATLAS. Fig. 9 shows matching of modeled and numerical simulation of potential distribution along the x-axis and y-axis in strong inversion region at z ¼ ðL=2Þ and V gs ¼ 0:7 V.

^ ð0; 0,zÞ can be written as The value of f

f^ ð0; 0,zÞ ¼ fð0; 0,zÞV gs þ V FB :

ð17Þ

Using the fact that the electric field at the mid-plane is zero for symmetric common gate FET and flattening of potential along the z-axis. The central potential can be obtained by same as that of the lightly doped double-gate (DG) MOSFET [23]. For a lightly doped body, the body doping can be neglected. Therefore, the 1D Poisson equation (along the (x,z) plane) for the silicon region with only the mobile charge (electron) density for y¼0 can be

5. Conclusion In this work an analytical model is developed for 3D potential distribution of RecG MOSFET in subthreshold and strong inversion regions. Further, we are in process of modeling square crosssection, circular cross-section GAA MOSFET using rectangular cross-section as a unified model. The present model is depended on assumption of parabolic potential distribution in the central region of device. The modeling of device electrostatics is based on

D. Sharma, S. Kumar Vishvakarma / Microelectronics Journal 43 (2012) 358–363

the 3D Laplace and 3D Poisson equations, where the gate oxide is replaced by an electrostatically equivalent silicon layer. For consideration of SCE the expression of long channel potential distribution is modify by taking the effect of z on l. The approximation of parabolic potential distribution in subthreshold region is not applicable near to source and drain due to flattening of potential in (x,y) cross-sectional. Therefore, the modified expression is presented near to source and drain. The model predicts the potential distribution in the transverse and longitudinal direction in subthreshold region and strong inversion region with good accuracy. The small deviation in strong inversion region is due to consideration of electron only as a charge carriers in the 3D Poisson equation. Acknowledgments The authors would like to thank to Tor A. Fjeldly, Professor in Department of Electronic and Telecommunication, Norwegian University of Science and Technology (NTNU) and Adjunct Professor in University Graduate Center (UNIK) Kjeller, Norway for his helpful discussions. References [1] S. Bangsaruntip, G.M. Cohen, A. Majumdar, J.W. Sleight, Universality of shortchannel effects in undoped-body silicon nanowire MOSFETs, IEEE Trans. Electron Devices 31 (9) (2010) 903–905. [2] T. Skotnicki, G. Merckel, T. Pedron, The voltage-doping transformation and new approach to the modeling of MOSFETs short-channel effects, IEEE Trans. Electron Devices 9 (3) (1988) 109–112. [3] H.A. El Hamid, J.R. Guitart, B. Iniguez, Two dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double gate MOSFETs, IEEE Trans. Electron Devices 54 (6) (2007) 1402–1408. [4] X. Sun, Q. Lu, V. Moroz, H. Takeuchi, G. Gebara, J. Wetzel, S. Ikeda, C. Shin, T.-J. King Liu, Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap, IEEE Trans. Electron Devices 29 (5) (2008) 491–493. [5] B. yu, H. Lu, M. Liu, Y. Taur, Explicit continuous models for double gate and surrounding gate MOSFETs, IEEE Trans. Electron Devices 56 (11) (2009) 2720–2725. [6] Y.-S. Wu, P. Su, Analytical quantum confinement model for short channel gate all around MOSFETs under subthreshold region, IEEE Trans. Electron Devices 56 (11) (2009) 2720–2725.

363

[7] H.A. Elhamid, B. Iniguez, D. Jimenez, J. Roig, J. Pallares, L.F. Marsal, Two dimensional analytical threshold voltage roll-off and subthreshold swing models for undoped cylindrical gate all around MOSFET, Solid-State Electron. 50 (2006) 805–812. [8] S.K. Vishvakarma, U. Monga, T.A. Fjeldly, Unified analytical modeling of GAA nanoscale MOSFETs, in: 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010, pp. 1733–1736. [9] E. Moreno, J.B. Roldan, F.G. Ruiz, D. Barrera, A. Godoy, F. Gamiz, An analytical model for square GAA MOSFETs including quantum effects, Solid-State Electron. 54 (2010) 1463–1469. [10] Md. Gaffar, Md. Mushfiqul Alam, S. Ashraf Mamun, Md. Abdul Matin, Modeling of threshold voltage of a quadruple gate transistor, Microelectron. J., 2011. [11] S.K. Vishvakarma, U. Monga, T.A. Fjeldly, Analytical modeling of the subthreshold electrostatics of nanoscale GAA square gate MOSFETs, in: Proceedings NSTI Nanotech Conference, Workshop on Compact Modeling, vol. 2, Anaheim, CA, USA, June 21–25, 2010, pp. 789–792. [12] C. Li, Y. Zhuang, R. Han, Cylindrical surrounding-gate MOSFETs with electrically induced source drain extension, Orig. Res. Artic. Microelectron. J. 42 (2) (2011). [13] B. Iniguez, D. Jimenez, J. Roig, H.A. Hamid, Explicit continuous model for long channel undoped surrounding gate MOSFETs, IEEE Trans. Electron Devices 52 (8) (2005) 1868–1872. [14] J.P. Colinge, From gate-all-around to nanowire MOSFETs, Semiconductor Conference, vol. 1, September 2007, pp. 11–17. [15] D. Jimenez, B. Iniguez, L.F. Marsal, Continuous analytical I–V model for surrounding gate MOSFETs, IEEE Electron Device Lett. 25 (8) (2004). [16] H. Borli, S. Kolberg, T.A. Fjeldly, Precise modeling framework for shortchannel double-gate and gate-all-around MOSFETs, IEEE Trans. Electron Devices 55 (10) (2008) 2678–2686. [17] Silvaco Int, ATLAS User’s Manual A 2D–3D Numerical Device Simulator, /http://www.silvaco.comS. [18] S. Wang, X. Guo, L. Zhang, C. Zhang, F. He, M. Chan, Analytical subthreshold channel potential model of asymmetric gate underlap gate-all-around MOSFET, in: IEEE International Conference on Electron Devices and Solid State Circuit, 2010, pp. 1–4. [19] H. Boli, S. Kolberg, T.A. Fjeldy, B. Iniguez, Precise modeling framework for short-channel double gate and gate-all-around MOSFETs, IEEE Trans. Electron Devices 55 (110) (2008) 2678–2686. [20] Y. Taur, Analytic solution of charge and capacitance in symmetric and asymmetric double-gate MOSFETs, IEEE Trans. Electron Devices 48 (12) (2001) 2861–2869. [21] T. Ghani, K. Mistry, P.Packan, S. Tyagi, M. Bohr, Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors, in: Proceedings of IEEE International Symposium on VLSI Technology, 2000, pp. 174–175. [22] X. Tang, V.K. De, J.D. Meindl, Intrinsic MOSFETs parameter fluctuations due to random dopant placement, IEEE Trans. VLSI Technol. 5 (1997) 369–376. [23] Y. Taur, An analytical solution to a double gate MOSFET with undoped body, IEEE Electron Device Lett. 21 (5) (2000).