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Analyzes of field effect devices based on poly(3-octylthiophene)
Synthetic Metals 139 (2003) 501–509
Analyzes of field effect devices based on poly(3-octylthiophene) S. Scheinert∗ , W. Schliefke Department of Solid State Electronics, Technical University of Ilmenau, PF 100565, D-98684 Ilmenau, Germany Received 24 February 2003; accepted 29 April 2003
Abstract Poly(3-octylthiophene) (P3OT) based MOS capacitors and transistors have been prepared. The spin-coated P3OT-layers have been investigated by ellipsometry. The measured index of refraction and the gap energy are n = 1.8 and EG = 2 eV, respectively. The layer thickness has been varied by the technological parameters of the deposition process from 65 nm down to about 10 nm. Quasi-static and dynamic capacitance voltage measurements on the capacitors prove an unintentional p-doping and indicate that layers up to about 30 nm are fully depleted. An unintentional doping concentration of approximately 5 × 1017 , . . . , 2 × 1018 cm−3 has been estimated by analytical approximations and comparison with numerical two-dimensional (2D) simulations. Both types of devices show hysteresis effects which have been already observed and analyzed for devices based on arylamino-poly-(p-phenylene-vinylene) and also reported for poly(3-hexylthiophene). The hysteresis is formally described by different flat band voltages for the sweep from positive to negative bias and the reverse direction. The dependence of the hysteresis on measuring and geometrical parameters allows for a qualitative discussion of the possible origin of the hysteresis. The analysis of the impedance measurements on the capacitors by estimations from the dielectric relaxation and comparison with 2D simulations is complemented by proposing an appropriate equivalent circuit. The extracted mobility perpendicular to the layer is as low as ≈ 5 × 10−8 cm2 /V s. The thin film transistors have a subthreshold slope of S ≈ 200 mV/dec which is rather good for an organic device. This value is in accordance with simulations and analytical calculations provided there are effectively no rechargeable trap states neither at the interface nor in the bulk. The mobilities estimated for the parallel transport are with ≈ 2×10−5 cm2 /V s almost three orders of magnitude larger than for the perpendicular transport. The influence of ageing and subsequent annealing has been investigated. The results support the assumption that the high unintentional doping is at least to some extent caused by oxidation. © 2003 Elsevier B.V. All rights reserved. Keywords: Organic field effect transistor; Conjugated polymer; Deep trap
1. Introduction Organic field effect transistors (OFET) are very attractive for low-cost and low-performance applications, such as active matrix organic displays [1] and all-polymer integrated circuits [2]. However, to realize low-cost devices, solution processable polymers are necessary which generally have a lower mobility as evaporated materials [3]. Furthermore, uniform films have to be prepared for transistors. Promising materials for such applications are regioregular poly(3-alkylthiophene)s [4,5]. But, in spite of present success there remain many open problems. First off all, usually there occur hysteresis effects, although they have been ignored in most cases. A rather detailed characterization of such effects has been presented by us [6,7] for devices based on arylamino-poly-(p-phenylene-vinylene). Brown et al. [8] described hysteresis effects for MIS capacitors based on
∗ Corresponding author. Tel.: +49-3677-693222; fax: +49-367-693777. E-mail address: [email protected] (S. Scheinert).
0379-6779/$ – see front matter © 2003 Elsevier B.V. All rights reserved. doi:10.1016/S0379-6779(03)00205-4
poly(3-hexylthiophene) and attributed them to carrier trapping or migration of dopants. Traps and defects also cause a non-optimal behavior of the transistors [9,10]. Another problem arises from the inverse subthreshold slope which should be small for realizing devices with low supply voltage. At present, in most of the OFETs this slope is with S ≈ 1 V/dec or higher [11–13] discontenting large. Recently, we investigated OFETs with regioregular poly(3-dodecylthiophene) (P3DDT) as the active layer and as an organic gate insulator poly-4-vinylphenol (P4VP) [14,15]. It has been shown by numerical simulations, that two observed peculiarities, an extremely high inverse subthreshold slope of S ≈ 7 V/dec, and a drain voltage dependence of the subthreshold current can be caused by recharging of traps either at the interface between the organic insulator and active layer or possibly also in the bulk of the active layer. In this article we report on thin film transistors and MOS capacitors with P3OT as the active layer which have been prepared by spin coating. Here again the hybrid design is chosen with silicon dioxide as gate insulator avoiding in this manner additional effects arising from an organic–organic
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interface. The material and layer characterization have been done by spectral ellipsometry. The design of the devices is the same as described in [7]. The devices have been characterized by the quasi-static and dynamic capacitance measurements, impedance measurements and transfer and output characteristics. The data are analyzed by analytical estimations, two-dimensional (2D) simulations and an appropriate equivalent circuit for the capacitor.
2. Experimental 2.1. Preparation and material characterization For the field effect devices a highly n-doped silicon substrate with a 50 nm thermally grown oxide film was used as gate electrode. The schematic cross sections of the MOS capacitors and thin film transistors are depicted in Fig. 1. Thin films of P3OT were prepared by spin-coating from 0.2 or 0.5 wt.% solution in CHCl3 under ambient atmosphere. The revolutions speed has been varied in the range 1000, . . . , 8500 rpm. With 1000 rpm layer thickness of 65 nm have been produced and with 8000 rpm about 30, . . . , 35 nm. The thicker layer are rather inhomogeneous with formation of stripes and did not lead to functioning devices. For the transistors, due to unintentional high doping, thinner layers are needed. With a less viscose solution and a revolutions speed of 8500 rpm layers as thin as 11 nm have been prepared. The spin-coating process was followed by a subsequent heating process under N2 at 120◦ C for 2 h. The index of refraction and the extinction coefficient have been determined by spectral ellipsometry (photon energies from 1.2 to 2.8 eV). They are depicted in Fig. 2 for two P3OT layers of different thickness which have been spin-coated on pure silicon. The thickness dependence is a result of the optical anisotropy of the layers as shown in [16]. From the low photon energy limit of the index of refraction n ≈ 1.8 the static dielectric constant εr = n2 ≈ 3.24 is obtained. For the gap energy the data yield about EG ≈ 2 eV. Both values are used below in the numerical simulations. From the spectral ellipsometry, besides the thickness, an extremely small roughness and an anisotropic complex dielectric function have been determined [16].
Fig. 2. Index of refraction and extinction coefficient for two P3OT layers of different thickness (sample 1: 33 nm, sample 2: 61 nm).
After annealing, circular contacts of 2r = 4 mm diameter (area A = πr2 ) for the capacitors and source and drain contacts for transistors have been evaporated using a hard mask. Transistors with a channel width of w = 1 mm and a channel length of L = 50 and 100 m, respectively have been prepared. For the separation of the devices from each other plasma etching common in semiconductor technology has been employed. 2.2. Measuring methods The capacitance of the MOS capacitors have been measured both in the quasi-static and in the dynamic (frequency dependent) regime. For the quasi-static measurements a HP 4140B pA-Meter/dc V source has been used which allows for a variation of the linear voltage ramp from 1 mV/s to 1 V/s. In most cases 0.5 V/s has been used. The initial voltage of the ramp has been fixed for the hold time of th = 180 s. The dynamic measurements have been carried out with the Solartron impedance/gain-phase analyzer 1260 A in the frequency range from 10 to 105 Hz. The voltage is increased stepwise. But due to the instrumentation in the dynamic measurements the initial hold time th and the delay time tD after each voltage step are the same. In general, the magnitude of the voltage step (usually 0.1 or 0.2 V) or the ramp rate, and tD and th are variable parameters in the measurements. The drain current of the transistors has been measured also with the HP 4140B. The choice of the delay time depends on the characteristics to be measured. For the OFET output characteristics short delay times (tD = 1 s) are possible whereas larger delay times (tD = 10 s) are required for transfer characteristics.
3. Electrical device characterization and analyzes of results 3.1. MOS capacitors Fig. 1. Schematic cross sections of the fabricated MOS capacitors and thin film transistors.
For consistency checks and for the analysis of the measurements, from the area of the gold dots and the thicknesses
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of the oxide and the P3OT layers, one can calculate the expected maximum and minimum capacitances. The oxide capacitance Cmax = Cox =
ε0 εox A = 8.46 nF dox
(1)
is the maximum value of the total MOS capacitance measured in accumulation. The minimum capacitance Cmin =
Cox CP3OT,min , Cox + CP3OT,min
CP3OT,min =
ε0 εr A lmax
(2)
is determined by the achievable minimum of the semiconductor capacitance CP3OT,min which in turn is determined by the maximum extension lmax of the depletion region. For a thick layer, defined by √ dP3OT > ldep , this is the depletion length łmax = ldep = (2ε0 εr |2ϕb |/eNA ) (the bulk potential ϕb is the difference between the bulk intrinsic potential and the Fermi potential). In this case one can determine the doping concentration NA from the minimum capacitance (2). However, for a thin layer (dP3OT < ldep ) one has łmax = dP3OT and one can estimate only a maximum value of the doping level. For the prepared layers with small thickness dP3OT (needed for the transistors, see later) of about 30 nm (or 11 nm) we expect lmax = dP3OT and hence according to Eq. (2) a minimum capacitance Cmin = 4.9 nF (6.7 nF). 3.1.1. Capacitance–voltage measurements Typical results for quasi-static and dynamic capacitance– voltage (CV) measurements of a capacitor with a 30 nm thick layer are depicted in Fig. 3. Accumulation (maximum capacitance) for negative voltage indicates (unintentional) p-doping of the material as expected for P3OT which is easily oxidized. The two ramp rates of the quasi-static measurements (Fig. 3a) give practically the same result. For each ramp rate four cycles have been measured from depletion (20 or 15 V) to accumulation (−10 V), and back after a further hold time. For lower ramp rates (R ≤ 0.1 V/s) noise becomes to large. Noticeable is the large hysteresis of the CV curves reported also e.g. for arylamino-poly-(p-phenylenevinylene) in [7,6] and poly(3-hexylthiophene) (P3HT) [8]. The starting minimum capacitance is close to the estimated Cmin = 4.9 nF. The maximum capacitance is a little larger than the oxide capacitance of 8.5 nF and the sweep from accumulation to depletion can hardly be analyzed. The quality of the dynamic curves (Fig. 3b) is much better. Again the hysteresis is conspicuous, and in depletion the minimum capacitance of 4.9 nF is close to the estimated one. The maximum capacitance of 8.5 nF is close to the theoretical value. However, this value is reached only for lower frequencies (≤100 Hz). Since for the formation of the accumulation layer the frequency must be lower than the corresponding reciprocal relaxation time, this indicates a low conductivity as will be discussed below in more detail. In the sweep from depletion to accumulation the quasi-static curves (Fig. 3a) are shifted to positive voltage
Fig. 3. Quasi-static (th = 180 s) (a) and dynamic CV curves (th = tD = 5 s) (b) of an capacitor on wafer OS1 (30 nm).
compared to the dynamic measurement (Fig. 3a) indicating the presence of negative interface charges in the case of the quasi-static measurements. However, the hold time before each sweep is different in both cases. The smaller hold time in the case of the dynamic measurements (here we have tD = th ) might be not sufficient for the formation of such interface charge. Thus, in Fig. 4a the influence of the hold time on the dynamic CV curve is demonstrated. Indeed, the hysteresis increases with increasing hold time whereby the sweep from depletion to accumulation is strongly shifted to larger positive voltage and the reverse sweep slightly to larger negative voltage. It is also visible that the slope of the curves in the transition region between depletion and accumulation is much smaller for the sweep from accumulation to inversion. For the thinner layer with a larger minimum capacitance (Fig. 4b), increasing hold time also increases the hysteresis. In this case the curves for both sweep directions are shifted in the same direction, however again the curves for the sweep from accumulation to depletion are much less shifted than the other ones. A further difference to the thicker layer is, that here the slope in the transition region is almost the same for both sweep directions. In general, a shift of the CV curve can be described by the formation of interface charges, which in our case depend first of all on the sweep direction which leads to the hysteresis, but also on the hold time at the beginning of each sweep. A comparison of the dynamic CV curves given in Fig. 4a and b shows that the hysteresis is larger for the thicker layer and for this layer also the slope of the transition between depletion and accumulation depends on the sweep direction.
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Fig. 4. Dynamic CV curves (10 Hz) for different hold times (th = tD ) for a capacitor on wafer OS1 (30 nm) (a) and on OS6 (11 nm) (b).
The maximum capacitance is in both cases in accordance with the estimations given above and also the minimum capacitance is in both cases that one of a thin completely depleted layer (dP3OT < ldep ). For the thinner layer(11 nm) one gets CP3OT,min = 32.9 nF and hence the minimum capacitance of Cmin = 6.7 nF which is almost the same as the measured value (Fig. 4b). Due to the complete depletion it is not possible to determine the doping from the minimum capacitance. But the maximum doping obtained in this manner is 5 × 1018 cm−3 for the thinner layer and 6.7 × 1017 cm−3 for the thicker layer. Analytical modeling and 2D simulation show that the slope of the curves in the transition region between depletion and accumulation depends sensitively on the doping level. A comparison of such calculations with the measured curves is depicted for the case of the thicker layer in Fig. 5a. Parameters in the calculations are the gap and dielectric constant as given earlier, the affinity χ = 3 eV (we use the value for the similar material P3HT [17]), the effective densities of states 1021 cm−3 [18,19] and the work function of the gold contact ΦAu = 5.1 eV. The analytical model does not account for the layer thickness and also for the generation of inversion charges, therefore the inversion region is calculated which cannot be measured due to the large generation time of the wide gap organic material. Apart from a shift of the flat band voltage the slope is described at best for 5×1017 cm−3 for the sweep from depletion to accumulation. This value has been used in the 2D simulation (using the program ATLAS [20]) of the dynamic curve for a frequency of 10 Hz. The simulation yield a somewhat larger minimum capaci-
Fig. 5. Dynamic CV curves (10 Hz) (a) for wafer OS1 (30 nm) compared to the analytical model and 2D simulation for estimation of doping and (b) for wafer OS6 (11 nm) compared to analytical model with a variation of doping and flat band voltage.
tance. This might be due to a depletion layer also in the silicon substrate which in the simulations have been treated as a n+ -poly-silicon contact. The simulations have been done also for a neutral contact instead of using the above mentioned gold work function. The resulting difference is small. To summarize, from these comparison we conclude that a reasonable estimate for the (unintentional) doping level is 5 × 1017 cm−3 for the thicker layer. Similarly, for the thinner layer (Fig. 5b) comparison with the analytical model with varying doping leads to the best agreement for a doping of 2 × 1018 cm−3 . Here both sweep directions are described well by introducing different shifts of the flat band voltage, namely for the sweep from depletion to accumulation VFB = −2.6 V and VFB = −5.6 V for the reverse sweep. These shifts of the flat band voltage correspond to interface charges, which are positive in this case, with areal density of 1012 cm−2 and 2.5 × 1012 cm−2 , respectively. As already mentioned, without speculations, these measurements give numbers but neither an information on the physico-chemical nature of these charges nor on the mechanism which leads to the switching between the two values of the interface charge within seconds when the sweep direction is reversed. One can think of mobile ions or traps as the cause for the formation of interface charges [8]. Numerical 2D simulations carried out by us have shown that traps lead to another form of the hysteresis and must be ruled out as origin for the observed hysteresis. As already in [7,6], also the present result indicate that one single process as,
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Fig. 6. Frequency response of the capacitance at different voltages for the 30 nm layer (wafer OS1) and one simulated dependence (−15 V, µ = 5 × 10−8 cm2 /V s). Symbols: values from the CV curves at different frequencies from Fig. 3b.
e.g. migration of dopants cannot account for the diversity of the observed effect. More detailed experimental information and comparison with simulations including such interface charges or states are needed and will be the matter of future work. 3.1.2. Frequency dependence of the capacitance Further information is obtained from frequency dependent impedance measurements. In Fig. 6 the results for the capacitance of the thicker layer are presented for three voltages. For all three voltages these values are close to those ones measured in the CV measurements in the sweep direction from accumulation to depletion. Since the voltage is fixed during the frequency dependent measurement, in the CV curve this sweep direction seems to be nearer to equilibrium than the other sweep direction. For higher frequencies the material cannot respond and the capacitance decreases, though not to the geometrical capacitance. The transition frequency is rather low, about fc ≈ 2 kHz at a voltage of −15 V. Using this transition frequency of the dielectric relaxation and the doping concentration determined in the preceding section, we obtain from τR = 1/(2πfc ) = ε0 εR /(eNA µ) the very low mobility (perpendicular to the layer) µ = 4.5 × 10−8 cm2 /V s. Alternatively, 2D simulations of this curve were carried out with the following parameters EG = 2 eV, ni = 1.5 × 104 cm−3 , χ = 3 eV, εr = 3.24, NA = 5 × 1017 cm−3 and φAu = 5.1 eV (gate). For a good fit of the measured transition frequency a mobility of µ = 5 × 10−8 cm2 /V s is necessary in accordance with the estimation given above. It is visible also that the measured transition is much broader indicating a distribution of relaxation times. The corresponding results of these measurements for the thinner layer are shown in Fig. 7. Here the transition seems to be smeared out even more and it becomes questionable to find out relevant transition frequencies. Indeed, more infor-
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Fig. 7. Frequency response of the capacitance at different voltages for the 11 nm layer (wafer OS6).
mation about characteristic frequencies is obtained from the imaginary part of the modulus function. Actually, what one measures is the reciprocal of the complex impedance Z, the admittance Z−1 = Y = Gp + jωCp . The modulus is defined as M = jωCgeo Z = jωCgeo Y −1 with Cgeo as the geometrical capacitance of the whole MOS structure. The real part of M −1 = ' is proportional to the capacitance discussed so far and the second quantity of interest is its imaginary part. Fig. 8 shows this quantity at a voltage in accumulation of −8 V which, evidently, exhibits more structure than the corresponding capacitance in Fig. 7. The frequency dependence of Im(M) cannot be described with the common model for the MOS structure consisting of the oxide capacitance and a parallel RC-term for the semiconductor. Actually, one has to include all elements of the equivalent circuit depicted in Fig. 9: the lead resistance Rl , the oxide capacitance Cox , the resistance and capacitance of the bulk (Rb , Cb ) layer and the resistance (Rif ) in parallel with a capacitance (Cif ) accounting for the accumulation layer (and/or interface states). The
Fig. 8. Imaginary part of the modulus function for the 11 nm layer (wafer OS6) at −8 V.
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Fig. 9. Equivalent circuit of the MOS capacitor in accumulation.
imaginary part of the modulus is then given by Rif Rb Im(M) = ωCgeo + + R l . 1+(ωCif Rif )2 1 + (ωCb Rb )2 (3) The fit (Fig. 8) results in two maxima at frequencies of 104 and 10 Hz. One obtains fb = 104 Hz = 1/(2πRb Cb ) and consequently for the bulk conductivity σb = ε0 εr 2πfb ≈ 1.7 × 10−8 S/cm which is slightly larger than in the thicker layer due to the higher doping. Indeed, with the above mentioned doping concentration one gets for the mobility µ ≈ 5.3 × 10−8 cm2 /V s almost the same as for the thicker layer. No direct insight into transport quantities can be obtained from the interface term in the equivalent circuit. 3.1.3. Temperature dependence of the capacitance Further measurements have been done to investigate the hysteresis effect. In Fig. 10 CV curves (at 10 Hz) and the frequency response of the capacitance (at −15 V) in dependence on the temperature are shown. It is visible (Fig. 10a)
Fig. 10. CV curve at 10 Hz for both sweep directions (a) and the frequency dependent capacitance at VGB = −15 V (b) for different temperatures, capacitor on wafer OS1 (30 nm).
that the hysteresis increases with increasing temperature which could be hardly understood as caused only by mobile ions as already stated for the PPV devices in [7]. The increased hysteresis is principally caused by the large shift of the flat band voltage for the sweep from accumulation to depletion (which should be that one nearer to equilibrium as discussed in connection with Fig. 6). Hence the change of the corresponding interface charge as a near-equilibrium quantity is strongly affected by the temperature. The slope in the depletion region is nearly constant. For the sweep from depletion to accumulation a smearing out does occur but no considerable shift. Finally, from both the CV and the frequency dependence (Fig. 10a and b) one learns that the capacitance in accumulation decreases strongly with increasing temperature whereas the transition frequency does not vary remarkably. Such a behavior is not known for inorganic semiconductors. These first investigations confirm that one is confronted with phenomena which cannot be understood fully in terms of conventional semiconductor physics. Extended models could include e.g. not only transport of mobile ions but also their reactions with the polymer with presumably large time constants, or even the formation of bipolarons. 3.2. Thin film transistors Transistors prepared on the wafer with the thicker layer (30 nm) were not functioning due to inhomogeneous layer deposition. However, on wafers with slightly thicker layers of about 35 nm the prepared transistors led to output characteristic which did not show saturation up to a drain voltage of −15 V. This means that the layer is not yet fully depleted in the inhomogeneous channel near drain and thinner layers have to be used as a consequence of the unintentional high doping. With the thinner layers (11 nm) the organic transistors are prepared with a channel width and length of 1 mm and 50 m, respectively. One example for a measured output characteristics is depicted in Fig. 11. The measurement has been done in ascending order with the gate voltage.
Fig. 11. Output characteristics of a transistor with the 11 nm layer (wafer OS6). The hold and delay times are th = 180 s and tD = 1 s, respectively.
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is usually rather large in the organic devices [11–13]. But it should be sufficiently small to achieve at low operation voltage large on–off ratios of the current. With the present preparation we achieved values as low as S ≈ 200 mV/dec (extracted from Fig. 12b). The approximate analytical expression for this quantity is [21]. Cd + Cit UT ln 10 (4) S = 1+ Cis
Fig. 12. Transfer characteristics of the transistor of Fig. 11 for drain voltages of −1 and −5 V (a) linear scale, (b) logarithmic scale. The hold and delay times are th = 180 s and tD = 10 s, respectively.
Obviously, the characteristics are similar to those ones of a conventional transistor with the transition into saturation already at low drain voltages. Low operation voltage is actually an important requirement for future applications of OFETs. However, there is a shift at repeated measurements as also observed for PPV devices. Such shifts are clearly connected with the flat band voltage shifts in the MOS capacitors described above. From the output characteristics one can approximately determine the mobility parallel to the layer using the simple Shockley equation. The resulting value of µ ≈ 2 × 10−5 cm2 /V s is about three orders of magnitude higher than the values estimated above from the frequency response of the MOS capacitor. This indicates an extreme anisotropy of the charge transport vertical and lateral to the interface. This means that there is a preferential orientation of the polymer chains parallel to the interface. The same conclusion has been drawn from the measurements of the optical properties of the P3OT layers. Detailed information on the threshold voltage and subthreshold region of these transistors are obtained from the transfer characteristics (Fig. 12) . The experimental curves for up and down sweep are measured at drain voltages of −1 and −5 V. As in the MOS capacitors one has a hysteresis, with larger drain currents for the sweep from depletion to accumulation (more pronounced visible in the linear scale, Fig. 12a). This dependence of the current on the sweep direction is caused by the threshold voltage V which is about 2.5 V when the measurements are beginning in depletion and which is shifted to 0.8 to 0 V for the reverse sweep. A further characteristics is the inverse subthreshold slope S which
where UT is the temperature voltage, Cis the insulator capacitance. Cit is a capacitance associated with interface traps whose recharging has been simulated numerically in [14,15] for P3DDT devices with an organic gate insulator. Cd = εr ε0 A/ ldep is the depletion capacitance including the influence of bulk traps. From this expression with the material and geometry parameters and the doping level given earlier (estimated depletion length ldep ≈ 20, . . . , 25 nm), one obtains approximately the same value as measured without supposing traps. That means we have neither in the bulk of the P3OT layer nor at the interface to the silicon dioxide a high concentration of traps at energies suitable for recharging. Consequently, it seems to be implausible that traps are causing the hysteresis. In order to quantify the shift of the threshold voltage, 2D simulations have been carried out with the mobility (determined from the Shockley equation) and the above mentioned parameters. They are compared with the measured transfer characteristics for −5 V drain voltage in Fig. 13. Different values for the doping concentration and interface charge are used to describe the measured curves by the simulations. The supposed doping is of the order as determined above from the capacitance measurements although slightly different values are needed for the two sweep directions. The shift of the threshold voltage between the two sweep directions can be described by a variation of the interface charge density of the order of 1012 cm−2 . Finally, the influence of ageing during storage in air and an interim additional annealing in Ar is demonstrated in Fig. 14. The second measurement is done after storage in
Fig. 13. Transfer characteristics of the transistor of Fig. 11 for a drain voltage of −5 V. Symbols: measurements for up and down sweep, lines: 2D simulations with different doping and fixed interface charges (Qf ).
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supposition that the unintentional high doping is connected with the oxidation of the P3OT. Since the mobility increases with the doping level one needs high doping for large currents and high cut-off frequency of the transistor. Although oxidation acts in this direction, it is hardly controllable. Therefore, alternative doping methods should be aspired.
4. Conclusions
Fig. 14. Transfer characteristics (VDS = −5 V) (a) and output characteristics (VGS = −3 and −7 V) (b) (transistor T2 on wafer OS6 (11 nm) with ω/L = 20) before and after annealing in Argon (th = 180 s and tD = 10 s).
air for 6 days. Then the additional annealing in Ar has been carried out and the next measurement on the next day. The last measurement was again 2 days later. Comparison between the first and second and between third and fourth measurements show the influence of ageing and comparison between the second and third one the influence of the annealing process. There is a strong reduction of the current by annealing, visible in the transfer characteristics (Fig. 14a), such that the corresponding output characteristics is not included in Fig. 14b. This decrease of the current is accompanied by a strong increase of the hysteresis. After both storage times ageing led to an increase of the current. Thereby, after the first storage period, as estimated from the low drain voltage slope of the output characteristics, the mobility is essentially unaffected (µ ≈ 3 × 10−5 cm2 /V s). Therefore the increase of the current should be caused again by a threshold voltage shift due to additional negative interface charges. They are at least partly removed during the annealing. Thereby also the mobility is strongly reduced by almost two orders of magnitude (µ ≈ 5 × 10−7 cm2 /V s). But in disordered organic materials the mobility depends strongly on the doping level [22,23]. That means, not only the interface charges are removed during the annealing process but also additional charges in the bulk. During the second storage period in air the mobility increases again, up to µ ≈ 6 × 10−6 cm2 /V s. These observations back the
MOS capacitors and thin film transistors with P3OT active layers of different thickness and silicon dioxide as insulator have been prepared. From spectral ellipsometry the layer thicknesses of 30 and 11 nm, respectively, the refraction index n = 1.8 and the gap energy of 2 eV have been obtained. Furthermore, an extremely small roughness and an anisotropic complex dielectric function have been determined. The measured current characteristics of the OFET show that unintentional high doping of the P3OT, probably by oxygen, requires layers of only ≈ 10 nm thickness to switch-off the transistor current. This unintentional p-doping is confirmed by quasi-static and dynamic capacitance voltage measurements on the capacitors. The homogeneous channel of the MOS capacitors can be depleted fully for layers up to about 30 nm. From analytical estimates based on the minimum and maximum capacitance and numerical (2D) simulations the doping concentration of 5 × 1017 cm−3 for the thicker layer and 2 × 1018 cm−3 for the thinner one have been estimated. As in PPV based devices, in the capacitance measurements on P3HT capacitors, hysteresis effects do occur. They can be described formally by a variation of an interface charge of the order of 1012 cm−2 which depends on the sweep direction. They must be connected with the oxidation of the polymer. Mobile ions could be a possible origin of the variation of interface charges at different voltages. However, the measured temperature dependence of the CV curves shows an increase of the hysteresis increasing the temperature indicating also other causes for this effect. It is suggested that transport of a low mobility species in connection with at least some reaction must be taken into account. A detailed and quantitative description is still missing. Traps as the origin of the hysteresis can be ruled out. The measured frequency response of the capacitance shows a low cut-off frequency of fc ≈ 10 Hz. To describe this value by means of the 2D simulation for the given doping concentration, a mobility of µ ≈ 5 × 10−8 cm2 /V s is necessary for the transport of the carriers vertical to the oxide interface. In addition analytical estimations and an appropriate equivalent circuit have been used to analyze the impedance data in accordance with the simulation. The operating voltage of the transistor is low (<10 V) because of the small oxide thickness of 50 nm. The subthreshold slope could be reduced to S ≈ 200 mV/dec which is rather good for an organic device. This value is
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in accordance with simulations and analytical calculations supposing the absence of rechargeable trap states both at the interface and in the bulk. From the measured current characteristics a mobility of µ ≈ 2 × 10−5 cm2 /V s for the transport lateral to the interface have been estimated confirming the high anisotropy of the layer indicating a regularity of the arrangement of the polymer chains even in the spin-coating deposition of the layer.
Acknowledgements Part of the work has been supported by the Deutsche Forschungsgemeinschaft and by the TITK Rudolstadt. Optical measurements have been performed by U.S. Zhokhavets, R. Goldhahn, and G. Gobsch. Solutions of P3OT have been provided by M. Schrödner, H.K. Roth, and S. Sensfuß. Discussions with G. Paasch and technical assistance from S. Klaube are acknowledged.
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[6] S. Scheinert, G. Paasch, S. Pohlmann, H.-H. Hörhold, R. Stockmann, in: Proceedings of the ESSDERC’99, 29th European Solid-State Device Research Conference, 13–15 September 1999, Editions Frontiers, Leuven/Belgium, 1999, p. 704. [7] S. Scheinert, G. Paasch, S. Pohlmann, H.-H. Hörhold, R. Stockmann, Solid State Electron. 44 (2000) 845. [8] P.J. Brown, H. Sirringhaus, M. Harrison, M. Shkunov, R.H. Friend, Phys. Rev. B 63 (2001) 125204. [9] Y.S. Yang, S.H. Kim, J.L. Lee, H.Y. Chu, L. Do, H. Lee, J. Oh, T. Zyung, M.K. Ryu, M.S. Jang, Appl. Phys. Lett. 80 (2002) 1595. [10] G. Horowitz, Ph. Delannoy, J. Appl. Phys. 70 (1991) 469. [11] D.J. Gundlach, L. Jia, T.N. Jackson, IEEE Trans. Electr. Dev. Lett. 22 (12) (2001) 571. [12] D.J. Gundlach, J.A. Nichols, L. Zhou, T. N Jackson, Appl. Phys. Lett. 80 (16) (2002) 2925. [13] R.A. Street, D. Knipp, A.R. Völkel, Appl. Phys. Lett. 80 (9) (2002) 1658. [14] S. Scheinert, G. Paasch, M. Schrödner, H.K. Roth, S. Sensfuß, Th. Doll, J. Appl. Phys. 92 (2002) 330. [15] S. Scheinert, G. Paasch, Th. Doll, Synth. Metals, submitted for publication. [16] U.S. Zhokhavets, R. Goldhahn, S. Scheinert, G. Gobsch, Verhandl, DPG VI 1 (2001) 220. [17] P. Barta, J. Sanetra, P. Grybos, S. Niziol, M. Trznades, Synth. Metals 94 (1998) 115. [18] G. Paasch, P.H. Nguyen, S.-L. Drechsler, Synth. Metals 97 (1998) 255. [19] P.H. Nguyen, S. Scheinert, S. Berleb, W. Brütting, G. Paasch, Organic Electron. 2 (2001) 105. [20] ATLAS User’s Manual: Device Simulation Software, SILVACO International, Santa Clara 1998. [21] S.M. Sze, Physics of Semiconductor Devices, Second ed., Wiley, 1981. [22] A.R. Brown, D.M. de Leeuw, E.E. Havinga, A. Pomp, Synth. Metals 68 (1994) 65. [23] G. Paasch, T. Lindner, S. Scheinert, Synth. Metals 132 (2002) 97.
Analyzes of field effect devices based on poly(3-octylthiophene) S. Scheinert∗ , W. Schliefke Department of Solid State Electronics, Technical University of Ilmenau, PF 100565, D-98684 Ilmenau, Germany Received 24 February 2003; accepted 29 April 2003
Abstract Poly(3-octylthiophene) (P3OT) based MOS capacitors and transistors have been prepared. The spin-coated P3OT-layers have been investigated by ellipsometry. The measured index of refraction and the gap energy are n = 1.8 and EG = 2 eV, respectively. The layer thickness has been varied by the technological parameters of the deposition process from 65 nm down to about 10 nm. Quasi-static and dynamic capacitance voltage measurements on the capacitors prove an unintentional p-doping and indicate that layers up to about 30 nm are fully depleted. An unintentional doping concentration of approximately 5 × 1017 , . . . , 2 × 1018 cm−3 has been estimated by analytical approximations and comparison with numerical two-dimensional (2D) simulations. Both types of devices show hysteresis effects which have been already observed and analyzed for devices based on arylamino-poly-(p-phenylene-vinylene) and also reported for poly(3-hexylthiophene). The hysteresis is formally described by different flat band voltages for the sweep from positive to negative bias and the reverse direction. The dependence of the hysteresis on measuring and geometrical parameters allows for a qualitative discussion of the possible origin of the hysteresis. The analysis of the impedance measurements on the capacitors by estimations from the dielectric relaxation and comparison with 2D simulations is complemented by proposing an appropriate equivalent circuit. The extracted mobility perpendicular to the layer is as low as ≈ 5 × 10−8 cm2 /V s. The thin film transistors have a subthreshold slope of S ≈ 200 mV/dec which is rather good for an organic device. This value is in accordance with simulations and analytical calculations provided there are effectively no rechargeable trap states neither at the interface nor in the bulk. The mobilities estimated for the parallel transport are with ≈ 2×10−5 cm2 /V s almost three orders of magnitude larger than for the perpendicular transport. The influence of ageing and subsequent annealing has been investigated. The results support the assumption that the high unintentional doping is at least to some extent caused by oxidation. © 2003 Elsevier B.V. All rights reserved. Keywords: Organic field effect transistor; Conjugated polymer; Deep trap
1. Introduction Organic field effect transistors (OFET) are very attractive for low-cost and low-performance applications, such as active matrix organic displays [1] and all-polymer integrated circuits [2]. However, to realize low-cost devices, solution processable polymers are necessary which generally have a lower mobility as evaporated materials [3]. Furthermore, uniform films have to be prepared for transistors. Promising materials for such applications are regioregular poly(3-alkylthiophene)s [4,5]. But, in spite of present success there remain many open problems. First off all, usually there occur hysteresis effects, although they have been ignored in most cases. A rather detailed characterization of such effects has been presented by us [6,7] for devices based on arylamino-poly-(p-phenylene-vinylene). Brown et al. [8] described hysteresis effects for MIS capacitors based on
∗ Corresponding author. Tel.: +49-3677-693222; fax: +49-367-693777. E-mail address: [email protected] (S. Scheinert).
0379-6779/$ – see front matter © 2003 Elsevier B.V. All rights reserved. doi:10.1016/S0379-6779(03)00205-4
poly(3-hexylthiophene) and attributed them to carrier trapping or migration of dopants. Traps and defects also cause a non-optimal behavior of the transistors [9,10]. Another problem arises from the inverse subthreshold slope which should be small for realizing devices with low supply voltage. At present, in most of the OFETs this slope is with S ≈ 1 V/dec or higher [11–13] discontenting large. Recently, we investigated OFETs with regioregular poly(3-dodecylthiophene) (P3DDT) as the active layer and as an organic gate insulator poly-4-vinylphenol (P4VP) [14,15]. It has been shown by numerical simulations, that two observed peculiarities, an extremely high inverse subthreshold slope of S ≈ 7 V/dec, and a drain voltage dependence of the subthreshold current can be caused by recharging of traps either at the interface between the organic insulator and active layer or possibly also in the bulk of the active layer. In this article we report on thin film transistors and MOS capacitors with P3OT as the active layer which have been prepared by spin coating. Here again the hybrid design is chosen with silicon dioxide as gate insulator avoiding in this manner additional effects arising from an organic–organic
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interface. The material and layer characterization have been done by spectral ellipsometry. The design of the devices is the same as described in [7]. The devices have been characterized by the quasi-static and dynamic capacitance measurements, impedance measurements and transfer and output characteristics. The data are analyzed by analytical estimations, two-dimensional (2D) simulations and an appropriate equivalent circuit for the capacitor.
2. Experimental 2.1. Preparation and material characterization For the field effect devices a highly n-doped silicon substrate with a 50 nm thermally grown oxide film was used as gate electrode. The schematic cross sections of the MOS capacitors and thin film transistors are depicted in Fig. 1. Thin films of P3OT were prepared by spin-coating from 0.2 or 0.5 wt.% solution in CHCl3 under ambient atmosphere. The revolutions speed has been varied in the range 1000, . . . , 8500 rpm. With 1000 rpm layer thickness of 65 nm have been produced and with 8000 rpm about 30, . . . , 35 nm. The thicker layer are rather inhomogeneous with formation of stripes and did not lead to functioning devices. For the transistors, due to unintentional high doping, thinner layers are needed. With a less viscose solution and a revolutions speed of 8500 rpm layers as thin as 11 nm have been prepared. The spin-coating process was followed by a subsequent heating process under N2 at 120◦ C for 2 h. The index of refraction and the extinction coefficient have been determined by spectral ellipsometry (photon energies from 1.2 to 2.8 eV). They are depicted in Fig. 2 for two P3OT layers of different thickness which have been spin-coated on pure silicon. The thickness dependence is a result of the optical anisotropy of the layers as shown in [16]. From the low photon energy limit of the index of refraction n ≈ 1.8 the static dielectric constant εr = n2 ≈ 3.24 is obtained. For the gap energy the data yield about EG ≈ 2 eV. Both values are used below in the numerical simulations. From the spectral ellipsometry, besides the thickness, an extremely small roughness and an anisotropic complex dielectric function have been determined [16].
Fig. 2. Index of refraction and extinction coefficient for two P3OT layers of different thickness (sample 1: 33 nm, sample 2: 61 nm).
After annealing, circular contacts of 2r = 4 mm diameter (area A = πr2 ) for the capacitors and source and drain contacts for transistors have been evaporated using a hard mask. Transistors with a channel width of w = 1 mm and a channel length of L = 50 and 100 m, respectively have been prepared. For the separation of the devices from each other plasma etching common in semiconductor technology has been employed. 2.2. Measuring methods The capacitance of the MOS capacitors have been measured both in the quasi-static and in the dynamic (frequency dependent) regime. For the quasi-static measurements a HP 4140B pA-Meter/dc V source has been used which allows for a variation of the linear voltage ramp from 1 mV/s to 1 V/s. In most cases 0.5 V/s has been used. The initial voltage of the ramp has been fixed for the hold time of th = 180 s. The dynamic measurements have been carried out with the Solartron impedance/gain-phase analyzer 1260 A in the frequency range from 10 to 105 Hz. The voltage is increased stepwise. But due to the instrumentation in the dynamic measurements the initial hold time th and the delay time tD after each voltage step are the same. In general, the magnitude of the voltage step (usually 0.1 or 0.2 V) or the ramp rate, and tD and th are variable parameters in the measurements. The drain current of the transistors has been measured also with the HP 4140B. The choice of the delay time depends on the characteristics to be measured. For the OFET output characteristics short delay times (tD = 1 s) are possible whereas larger delay times (tD = 10 s) are required for transfer characteristics.
3. Electrical device characterization and analyzes of results 3.1. MOS capacitors Fig. 1. Schematic cross sections of the fabricated MOS capacitors and thin film transistors.
For consistency checks and for the analysis of the measurements, from the area of the gold dots and the thicknesses
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of the oxide and the P3OT layers, one can calculate the expected maximum and minimum capacitances. The oxide capacitance Cmax = Cox =
ε0 εox A = 8.46 nF dox
(1)
is the maximum value of the total MOS capacitance measured in accumulation. The minimum capacitance Cmin =
Cox CP3OT,min , Cox + CP3OT,min
CP3OT,min =
ε0 εr A lmax
(2)
is determined by the achievable minimum of the semiconductor capacitance CP3OT,min which in turn is determined by the maximum extension lmax of the depletion region. For a thick layer, defined by √ dP3OT > ldep , this is the depletion length łmax = ldep = (2ε0 εr |2ϕb |/eNA ) (the bulk potential ϕb is the difference between the bulk intrinsic potential and the Fermi potential). In this case one can determine the doping concentration NA from the minimum capacitance (2). However, for a thin layer (dP3OT < ldep ) one has łmax = dP3OT and one can estimate only a maximum value of the doping level. For the prepared layers with small thickness dP3OT (needed for the transistors, see later) of about 30 nm (or 11 nm) we expect lmax = dP3OT and hence according to Eq. (2) a minimum capacitance Cmin = 4.9 nF (6.7 nF). 3.1.1. Capacitance–voltage measurements Typical results for quasi-static and dynamic capacitance– voltage (CV) measurements of a capacitor with a 30 nm thick layer are depicted in Fig. 3. Accumulation (maximum capacitance) for negative voltage indicates (unintentional) p-doping of the material as expected for P3OT which is easily oxidized. The two ramp rates of the quasi-static measurements (Fig. 3a) give practically the same result. For each ramp rate four cycles have been measured from depletion (20 or 15 V) to accumulation (−10 V), and back after a further hold time. For lower ramp rates (R ≤ 0.1 V/s) noise becomes to large. Noticeable is the large hysteresis of the CV curves reported also e.g. for arylamino-poly-(p-phenylenevinylene) in [7,6] and poly(3-hexylthiophene) (P3HT) [8]. The starting minimum capacitance is close to the estimated Cmin = 4.9 nF. The maximum capacitance is a little larger than the oxide capacitance of 8.5 nF and the sweep from accumulation to depletion can hardly be analyzed. The quality of the dynamic curves (Fig. 3b) is much better. Again the hysteresis is conspicuous, and in depletion the minimum capacitance of 4.9 nF is close to the estimated one. The maximum capacitance of 8.5 nF is close to the theoretical value. However, this value is reached only for lower frequencies (≤100 Hz). Since for the formation of the accumulation layer the frequency must be lower than the corresponding reciprocal relaxation time, this indicates a low conductivity as will be discussed below in more detail. In the sweep from depletion to accumulation the quasi-static curves (Fig. 3a) are shifted to positive voltage
Fig. 3. Quasi-static (th = 180 s) (a) and dynamic CV curves (th = tD = 5 s) (b) of an capacitor on wafer OS1 (30 nm).
compared to the dynamic measurement (Fig. 3a) indicating the presence of negative interface charges in the case of the quasi-static measurements. However, the hold time before each sweep is different in both cases. The smaller hold time in the case of the dynamic measurements (here we have tD = th ) might be not sufficient for the formation of such interface charge. Thus, in Fig. 4a the influence of the hold time on the dynamic CV curve is demonstrated. Indeed, the hysteresis increases with increasing hold time whereby the sweep from depletion to accumulation is strongly shifted to larger positive voltage and the reverse sweep slightly to larger negative voltage. It is also visible that the slope of the curves in the transition region between depletion and accumulation is much smaller for the sweep from accumulation to inversion. For the thinner layer with a larger minimum capacitance (Fig. 4b), increasing hold time also increases the hysteresis. In this case the curves for both sweep directions are shifted in the same direction, however again the curves for the sweep from accumulation to depletion are much less shifted than the other ones. A further difference to the thicker layer is, that here the slope in the transition region is almost the same for both sweep directions. In general, a shift of the CV curve can be described by the formation of interface charges, which in our case depend first of all on the sweep direction which leads to the hysteresis, but also on the hold time at the beginning of each sweep. A comparison of the dynamic CV curves given in Fig. 4a and b shows that the hysteresis is larger for the thicker layer and for this layer also the slope of the transition between depletion and accumulation depends on the sweep direction.
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Fig. 4. Dynamic CV curves (10 Hz) for different hold times (th = tD ) for a capacitor on wafer OS1 (30 nm) (a) and on OS6 (11 nm) (b).
The maximum capacitance is in both cases in accordance with the estimations given above and also the minimum capacitance is in both cases that one of a thin completely depleted layer (dP3OT < ldep ). For the thinner layer(11 nm) one gets CP3OT,min = 32.9 nF and hence the minimum capacitance of Cmin = 6.7 nF which is almost the same as the measured value (Fig. 4b). Due to the complete depletion it is not possible to determine the doping from the minimum capacitance. But the maximum doping obtained in this manner is 5 × 1018 cm−3 for the thinner layer and 6.7 × 1017 cm−3 for the thicker layer. Analytical modeling and 2D simulation show that the slope of the curves in the transition region between depletion and accumulation depends sensitively on the doping level. A comparison of such calculations with the measured curves is depicted for the case of the thicker layer in Fig. 5a. Parameters in the calculations are the gap and dielectric constant as given earlier, the affinity χ = 3 eV (we use the value for the similar material P3HT [17]), the effective densities of states 1021 cm−3 [18,19] and the work function of the gold contact ΦAu = 5.1 eV. The analytical model does not account for the layer thickness and also for the generation of inversion charges, therefore the inversion region is calculated which cannot be measured due to the large generation time of the wide gap organic material. Apart from a shift of the flat band voltage the slope is described at best for 5×1017 cm−3 for the sweep from depletion to accumulation. This value has been used in the 2D simulation (using the program ATLAS [20]) of the dynamic curve for a frequency of 10 Hz. The simulation yield a somewhat larger minimum capaci-
Fig. 5. Dynamic CV curves (10 Hz) (a) for wafer OS1 (30 nm) compared to the analytical model and 2D simulation for estimation of doping and (b) for wafer OS6 (11 nm) compared to analytical model with a variation of doping and flat band voltage.
tance. This might be due to a depletion layer also in the silicon substrate which in the simulations have been treated as a n+ -poly-silicon contact. The simulations have been done also for a neutral contact instead of using the above mentioned gold work function. The resulting difference is small. To summarize, from these comparison we conclude that a reasonable estimate for the (unintentional) doping level is 5 × 1017 cm−3 for the thicker layer. Similarly, for the thinner layer (Fig. 5b) comparison with the analytical model with varying doping leads to the best agreement for a doping of 2 × 1018 cm−3 . Here both sweep directions are described well by introducing different shifts of the flat band voltage, namely for the sweep from depletion to accumulation VFB = −2.6 V and VFB = −5.6 V for the reverse sweep. These shifts of the flat band voltage correspond to interface charges, which are positive in this case, with areal density of 1012 cm−2 and 2.5 × 1012 cm−2 , respectively. As already mentioned, without speculations, these measurements give numbers but neither an information on the physico-chemical nature of these charges nor on the mechanism which leads to the switching between the two values of the interface charge within seconds when the sweep direction is reversed. One can think of mobile ions or traps as the cause for the formation of interface charges [8]. Numerical 2D simulations carried out by us have shown that traps lead to another form of the hysteresis and must be ruled out as origin for the observed hysteresis. As already in [7,6], also the present result indicate that one single process as,
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Fig. 6. Frequency response of the capacitance at different voltages for the 30 nm layer (wafer OS1) and one simulated dependence (−15 V, µ = 5 × 10−8 cm2 /V s). Symbols: values from the CV curves at different frequencies from Fig. 3b.
e.g. migration of dopants cannot account for the diversity of the observed effect. More detailed experimental information and comparison with simulations including such interface charges or states are needed and will be the matter of future work. 3.1.2. Frequency dependence of the capacitance Further information is obtained from frequency dependent impedance measurements. In Fig. 6 the results for the capacitance of the thicker layer are presented for three voltages. For all three voltages these values are close to those ones measured in the CV measurements in the sweep direction from accumulation to depletion. Since the voltage is fixed during the frequency dependent measurement, in the CV curve this sweep direction seems to be nearer to equilibrium than the other sweep direction. For higher frequencies the material cannot respond and the capacitance decreases, though not to the geometrical capacitance. The transition frequency is rather low, about fc ≈ 2 kHz at a voltage of −15 V. Using this transition frequency of the dielectric relaxation and the doping concentration determined in the preceding section, we obtain from τR = 1/(2πfc ) = ε0 εR /(eNA µ) the very low mobility (perpendicular to the layer) µ = 4.5 × 10−8 cm2 /V s. Alternatively, 2D simulations of this curve were carried out with the following parameters EG = 2 eV, ni = 1.5 × 104 cm−3 , χ = 3 eV, εr = 3.24, NA = 5 × 1017 cm−3 and φAu = 5.1 eV (gate). For a good fit of the measured transition frequency a mobility of µ = 5 × 10−8 cm2 /V s is necessary in accordance with the estimation given above. It is visible also that the measured transition is much broader indicating a distribution of relaxation times. The corresponding results of these measurements for the thinner layer are shown in Fig. 7. Here the transition seems to be smeared out even more and it becomes questionable to find out relevant transition frequencies. Indeed, more infor-
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Fig. 7. Frequency response of the capacitance at different voltages for the 11 nm layer (wafer OS6).
mation about characteristic frequencies is obtained from the imaginary part of the modulus function. Actually, what one measures is the reciprocal of the complex impedance Z, the admittance Z−1 = Y = Gp + jωCp . The modulus is defined as M = jωCgeo Z = jωCgeo Y −1 with Cgeo as the geometrical capacitance of the whole MOS structure. The real part of M −1 = ' is proportional to the capacitance discussed so far and the second quantity of interest is its imaginary part. Fig. 8 shows this quantity at a voltage in accumulation of −8 V which, evidently, exhibits more structure than the corresponding capacitance in Fig. 7. The frequency dependence of Im(M) cannot be described with the common model for the MOS structure consisting of the oxide capacitance and a parallel RC-term for the semiconductor. Actually, one has to include all elements of the equivalent circuit depicted in Fig. 9: the lead resistance Rl , the oxide capacitance Cox , the resistance and capacitance of the bulk (Rb , Cb ) layer and the resistance (Rif ) in parallel with a capacitance (Cif ) accounting for the accumulation layer (and/or interface states). The
Fig. 8. Imaginary part of the modulus function for the 11 nm layer (wafer OS6) at −8 V.
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Fig. 9. Equivalent circuit of the MOS capacitor in accumulation.
imaginary part of the modulus is then given by Rif Rb Im(M) = ωCgeo + + R l . 1+(ωCif Rif )2 1 + (ωCb Rb )2 (3) The fit (Fig. 8) results in two maxima at frequencies of 104 and 10 Hz. One obtains fb = 104 Hz = 1/(2πRb Cb ) and consequently for the bulk conductivity σb = ε0 εr 2πfb ≈ 1.7 × 10−8 S/cm which is slightly larger than in the thicker layer due to the higher doping. Indeed, with the above mentioned doping concentration one gets for the mobility µ ≈ 5.3 × 10−8 cm2 /V s almost the same as for the thicker layer. No direct insight into transport quantities can be obtained from the interface term in the equivalent circuit. 3.1.3. Temperature dependence of the capacitance Further measurements have been done to investigate the hysteresis effect. In Fig. 10 CV curves (at 10 Hz) and the frequency response of the capacitance (at −15 V) in dependence on the temperature are shown. It is visible (Fig. 10a)
Fig. 10. CV curve at 10 Hz for both sweep directions (a) and the frequency dependent capacitance at VGB = −15 V (b) for different temperatures, capacitor on wafer OS1 (30 nm).
that the hysteresis increases with increasing temperature which could be hardly understood as caused only by mobile ions as already stated for the PPV devices in [7]. The increased hysteresis is principally caused by the large shift of the flat band voltage for the sweep from accumulation to depletion (which should be that one nearer to equilibrium as discussed in connection with Fig. 6). Hence the change of the corresponding interface charge as a near-equilibrium quantity is strongly affected by the temperature. The slope in the depletion region is nearly constant. For the sweep from depletion to accumulation a smearing out does occur but no considerable shift. Finally, from both the CV and the frequency dependence (Fig. 10a and b) one learns that the capacitance in accumulation decreases strongly with increasing temperature whereas the transition frequency does not vary remarkably. Such a behavior is not known for inorganic semiconductors. These first investigations confirm that one is confronted with phenomena which cannot be understood fully in terms of conventional semiconductor physics. Extended models could include e.g. not only transport of mobile ions but also their reactions with the polymer with presumably large time constants, or even the formation of bipolarons. 3.2. Thin film transistors Transistors prepared on the wafer with the thicker layer (30 nm) were not functioning due to inhomogeneous layer deposition. However, on wafers with slightly thicker layers of about 35 nm the prepared transistors led to output characteristic which did not show saturation up to a drain voltage of −15 V. This means that the layer is not yet fully depleted in the inhomogeneous channel near drain and thinner layers have to be used as a consequence of the unintentional high doping. With the thinner layers (11 nm) the organic transistors are prepared with a channel width and length of 1 mm and 50 m, respectively. One example for a measured output characteristics is depicted in Fig. 11. The measurement has been done in ascending order with the gate voltage.
Fig. 11. Output characteristics of a transistor with the 11 nm layer (wafer OS6). The hold and delay times are th = 180 s and tD = 1 s, respectively.
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is usually rather large in the organic devices [11–13]. But it should be sufficiently small to achieve at low operation voltage large on–off ratios of the current. With the present preparation we achieved values as low as S ≈ 200 mV/dec (extracted from Fig. 12b). The approximate analytical expression for this quantity is [21]. Cd + Cit UT ln 10 (4) S = 1+ Cis
Fig. 12. Transfer characteristics of the transistor of Fig. 11 for drain voltages of −1 and −5 V (a) linear scale, (b) logarithmic scale. The hold and delay times are th = 180 s and tD = 10 s, respectively.
Obviously, the characteristics are similar to those ones of a conventional transistor with the transition into saturation already at low drain voltages. Low operation voltage is actually an important requirement for future applications of OFETs. However, there is a shift at repeated measurements as also observed for PPV devices. Such shifts are clearly connected with the flat band voltage shifts in the MOS capacitors described above. From the output characteristics one can approximately determine the mobility parallel to the layer using the simple Shockley equation. The resulting value of µ ≈ 2 × 10−5 cm2 /V s is about three orders of magnitude higher than the values estimated above from the frequency response of the MOS capacitor. This indicates an extreme anisotropy of the charge transport vertical and lateral to the interface. This means that there is a preferential orientation of the polymer chains parallel to the interface. The same conclusion has been drawn from the measurements of the optical properties of the P3OT layers. Detailed information on the threshold voltage and subthreshold region of these transistors are obtained from the transfer characteristics (Fig. 12) . The experimental curves for up and down sweep are measured at drain voltages of −1 and −5 V. As in the MOS capacitors one has a hysteresis, with larger drain currents for the sweep from depletion to accumulation (more pronounced visible in the linear scale, Fig. 12a). This dependence of the current on the sweep direction is caused by the threshold voltage V which is about 2.5 V when the measurements are beginning in depletion and which is shifted to 0.8 to 0 V for the reverse sweep. A further characteristics is the inverse subthreshold slope S which
where UT is the temperature voltage, Cis the insulator capacitance. Cit is a capacitance associated with interface traps whose recharging has been simulated numerically in [14,15] for P3DDT devices with an organic gate insulator. Cd = εr ε0 A/ ldep is the depletion capacitance including the influence of bulk traps. From this expression with the material and geometry parameters and the doping level given earlier (estimated depletion length ldep ≈ 20, . . . , 25 nm), one obtains approximately the same value as measured without supposing traps. That means we have neither in the bulk of the P3OT layer nor at the interface to the silicon dioxide a high concentration of traps at energies suitable for recharging. Consequently, it seems to be implausible that traps are causing the hysteresis. In order to quantify the shift of the threshold voltage, 2D simulations have been carried out with the mobility (determined from the Shockley equation) and the above mentioned parameters. They are compared with the measured transfer characteristics for −5 V drain voltage in Fig. 13. Different values for the doping concentration and interface charge are used to describe the measured curves by the simulations. The supposed doping is of the order as determined above from the capacitance measurements although slightly different values are needed for the two sweep directions. The shift of the threshold voltage between the two sweep directions can be described by a variation of the interface charge density of the order of 1012 cm−2 . Finally, the influence of ageing during storage in air and an interim additional annealing in Ar is demonstrated in Fig. 14. The second measurement is done after storage in
Fig. 13. Transfer characteristics of the transistor of Fig. 11 for a drain voltage of −5 V. Symbols: measurements for up and down sweep, lines: 2D simulations with different doping and fixed interface charges (Qf ).
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supposition that the unintentional high doping is connected with the oxidation of the P3OT. Since the mobility increases with the doping level one needs high doping for large currents and high cut-off frequency of the transistor. Although oxidation acts in this direction, it is hardly controllable. Therefore, alternative doping methods should be aspired.
4. Conclusions
Fig. 14. Transfer characteristics (VDS = −5 V) (a) and output characteristics (VGS = −3 and −7 V) (b) (transistor T2 on wafer OS6 (11 nm) with ω/L = 20) before and after annealing in Argon (th = 180 s and tD = 10 s).
air for 6 days. Then the additional annealing in Ar has been carried out and the next measurement on the next day. The last measurement was again 2 days later. Comparison between the first and second and between third and fourth measurements show the influence of ageing and comparison between the second and third one the influence of the annealing process. There is a strong reduction of the current by annealing, visible in the transfer characteristics (Fig. 14a), such that the corresponding output characteristics is not included in Fig. 14b. This decrease of the current is accompanied by a strong increase of the hysteresis. After both storage times ageing led to an increase of the current. Thereby, after the first storage period, as estimated from the low drain voltage slope of the output characteristics, the mobility is essentially unaffected (µ ≈ 3 × 10−5 cm2 /V s). Therefore the increase of the current should be caused again by a threshold voltage shift due to additional negative interface charges. They are at least partly removed during the annealing. Thereby also the mobility is strongly reduced by almost two orders of magnitude (µ ≈ 5 × 10−7 cm2 /V s). But in disordered organic materials the mobility depends strongly on the doping level [22,23]. That means, not only the interface charges are removed during the annealing process but also additional charges in the bulk. During the second storage period in air the mobility increases again, up to µ ≈ 6 × 10−6 cm2 /V s. These observations back the
MOS capacitors and thin film transistors with P3OT active layers of different thickness and silicon dioxide as insulator have been prepared. From spectral ellipsometry the layer thicknesses of 30 and 11 nm, respectively, the refraction index n = 1.8 and the gap energy of 2 eV have been obtained. Furthermore, an extremely small roughness and an anisotropic complex dielectric function have been determined. The measured current characteristics of the OFET show that unintentional high doping of the P3OT, probably by oxygen, requires layers of only ≈ 10 nm thickness to switch-off the transistor current. This unintentional p-doping is confirmed by quasi-static and dynamic capacitance voltage measurements on the capacitors. The homogeneous channel of the MOS capacitors can be depleted fully for layers up to about 30 nm. From analytical estimates based on the minimum and maximum capacitance and numerical (2D) simulations the doping concentration of 5 × 1017 cm−3 for the thicker layer and 2 × 1018 cm−3 for the thinner one have been estimated. As in PPV based devices, in the capacitance measurements on P3HT capacitors, hysteresis effects do occur. They can be described formally by a variation of an interface charge of the order of 1012 cm−2 which depends on the sweep direction. They must be connected with the oxidation of the polymer. Mobile ions could be a possible origin of the variation of interface charges at different voltages. However, the measured temperature dependence of the CV curves shows an increase of the hysteresis increasing the temperature indicating also other causes for this effect. It is suggested that transport of a low mobility species in connection with at least some reaction must be taken into account. A detailed and quantitative description is still missing. Traps as the origin of the hysteresis can be ruled out. The measured frequency response of the capacitance shows a low cut-off frequency of fc ≈ 10 Hz. To describe this value by means of the 2D simulation for the given doping concentration, a mobility of µ ≈ 5 × 10−8 cm2 /V s is necessary for the transport of the carriers vertical to the oxide interface. In addition analytical estimations and an appropriate equivalent circuit have been used to analyze the impedance data in accordance with the simulation. The operating voltage of the transistor is low (<10 V) because of the small oxide thickness of 50 nm. The subthreshold slope could be reduced to S ≈ 200 mV/dec which is rather good for an organic device. This value is
S. Scheinert, W. Schliefke / Synthetic Metals 139 (2003) 501–509
in accordance with simulations and analytical calculations supposing the absence of rechargeable trap states both at the interface and in the bulk. From the measured current characteristics a mobility of µ ≈ 2 × 10−5 cm2 /V s for the transport lateral to the interface have been estimated confirming the high anisotropy of the layer indicating a regularity of the arrangement of the polymer chains even in the spin-coating deposition of the layer.
Acknowledgements Part of the work has been supported by the Deutsche Forschungsgemeinschaft and by the TITK Rudolstadt. Optical measurements have been performed by U.S. Zhokhavets, R. Goldhahn, and G. Gobsch. Solutions of P3OT have been provided by M. Schrödner, H.K. Roth, and S. Sensfuß. Discussions with G. Paasch and technical assistance from S. Klaube are acknowledged.
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