p-Si structure

Microelectronic Engineering 88 (2011) 573–577

Contents lists available at ScienceDirect

Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee

Annealing effect on the metal gate effective work function modulation for the Al/TiN/SiO2/p-Si structure Xiao-Rong Wang a, Yu-Long Jiang a,*, Qi Xie b, Christophe Detavernier b, Guo-Ping Ru a, Xin-Ping Qu a, Bing-Zong Li a a b

State Key Lab of ASIC and System, Department of Microelectronics, Fudan University, Shanghai 200433, China Department of Solid State Science, Ghent University, Krijgslaan 281/S1, B-9000 Ghent, Belgium

a r t i c l e

i n f o

Article history: Available online 23 June 2010 Keywords: Effective work function (EWF) Flat band voltage (VFB) Metal gate Aluminum (Al) Titanium nitride (TiN)

a b s t r a c t In this work, the thermal annealing effect on the metal gate effective work function (EWF) modulation for the Al/TiN/SiO2/p-Si(1 0 0) structure was investigated. Compared with the sample of TiN/SiO2/p-Si(1 0 0) structure, for the sample additionally capped with Al the flat band voltage has a very obvious shift as large as 0.54 V to the negative direction after forming gas annealing. It is also revealed that the thermal budget can effectively influence both the EWF of the gate electrode and the thickness of the gate dielectric layer when a post annealing at 600 °C with different soak times was applied to the samples with Al cap. Material characterization indicates that the diffusion of Al and the formation of Al oxide during annealing should be responsible for all the phenomena. The interface trap density Dit calculated from the high-frequency C–V and the laser-assisted high-frequency C–V curves show that the introduction of Al does not cause reliability problem in the Al/TiN/SiO2/p-Si structure. Ó 2010 Elsevier B.V. All rights reserved.

1. Introduction With the aggressive downscaling of complementary metal oxide semiconductor (CMOS) devices, metal gate technology is becoming essential especially for 45 nm node and beyond to replace the conventional poly-Si gate technology due to the issues such as poly-Si depletion effect, boron penetration, and Fermi level pinning with high-k gate dielectric [1,2]. However, some requirements on the new metal gate material must be satisfied, for instance, process integration with the traditional CMOS process flow, material compatibility, devices reliability and suitable work functions (4.05 eV for NMOS, 5.17 eV for PMOS), etc. Among various candidates TiN is widely studied [3,4] because of its chemical inertness, low resistivity and process compatibility. For a promising metal gate material, its work function should be able to be effectively modulated so that it can be applied to both NMOS and PMOS devices simultaneously. However, the reported work function of TiN is between 4.7 eV and 5.2 eV on the basis of different process condition, suitable for the gate material of PMOS. In order to use the TiN as the gate material of NMOS at the same time, some methods should be taken to modulate the effective work function (EWF) of TiN metal gate toward the edge of the conductance band of Si. There are many reported ways tuning the EWF of gate electrode, for example, dopant implantation and annealing, * Correponding author. Tel./fax: +86 21 65643768. E-mail address: [email protected] (Y.-L. Jiang). 0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.06.029

making variation of the metal–dielectric interface status, which could modulate the work function of the gate electrode effectively. In this work, the annealing effect on the EWF modulation for the TiN metal gate capped with Al was investigated, because it is very compatible with traditional CMOS process flow and will not likely introduce damage. The diffusion of Al in the TiN thin film and its effect on the work-function modulation for the Al/TiN/SiO2/ p-Si(1 0 0) structure was studied. 2. Experimental The device-level SiO2 layer with the thickness of 10, 20 and 30 nm was grown by dry oxidation on p-Si(1 0 0) substrate. Circular MOS capacitors with a structure of Al(40 nm)/TiN(20 nm)/SiO2/ p-Si(1 0 0) and TiN(60 nm)/SiO2/p-Si(1 0 0) were, respectively, fabricated by magnetron sputtering deposition and liftoff process. The circle area is 1:77  104 cm2 . Then thermal annealing at 600 °C for 15 s, 1 min, 5 min and 10 min in N2 ambient was respectively, performed for these capacitors. For comparison, circular MOS capacitors of TixAlyN1xy(60 nm)/SiO2/p-Si(1 0 0) with an area of 1:77  104 cm2 was also prepared by magnetron sputtering deposition and liftoff process. The TixAlyN1xy film was deposited by co-sputtering of Ti and Al in the N2 ambient. The content of Al can be controlled by changing the power on the Al target. Different power of 50 W, 75 W, 100 W, 125 W was, respectively, applied. Other conditions, such as the power on the Ti target and the ratio of N2/Ar, is the same as the pure TiN film deposition mentioned

574

X.-R. Wang et al. / Microelectronic Engineering 88 (2011) 573–577

Fig. 1. High-frequency C–V curves corrected with two-frequency method.

above. All the processed MOS capacitor samples have a last forming gas annealing (FGA) at 400 °C for 30 min in the N2/H2 = 10:1 ambient. High-frequency capacitance–voltage (C–V) and laser-assisted high-frequency C–V characteristics were measured for all the capacitors by an Agilent 4294A precision impedance analyzer. All the C–V curves will be corrected by the two-frequency method to minimize frequency dispersion in the accumulation region introduced by the parasitic effects as indicated in Fig. 1 [5]. X-ray diffraction (XRD) was used to analyze the change of the phase. Secondary ion mass spectroscopy (SIMS) and Auger electron spectroscopy (AES) were applied for elements diffusion analysis. Interface trap density Dit was calculated from the high-frequency and the laser-assisted high-frequency C–V curves. Fig. 2. The high-frequency C–V curves comparison of the TiN and Al/TiN metal gate (a) before and (b) after FGA.

3. Results and discussion As can be seen in Fig. 2a, the flat band voltage (VFB) for the asdeposited Al/TiN metal gate capacitor and the TiN metal gate capacitor is almost the same. However, a negative shift as large as 0.54 V after FGA was observed as shown in Fig. 2b, which indicates that the EWF of the annealed Al/TiN stack is significantly lowered. XRD and SIMS were carried out for these annealed samples. As can be seen in Figs. 3 and 4, Al has diffused through the TiN film, which should be responsible for the shift of the VFB. As one knows that the work function of Al is as low as 4.25 eV and the reported work function of TiN is between 4.7 eV and 5.2 eV [6,7]. Therefore, the more Al atoms appear at the TiN/SiO2 interface, the lower EWF of the metal gate will be achieved. Fig. 5a and b shows the high-frequency C–V curves for those samples having a higher annealing temperature of 600 °C with different soak times. For the TiN(60 nm)/SiO2/p-Si(1 0 0) structure, the VFB has a slight shift to the negative direction as the thermal budget increase. The nitrogen concentration or more accurate, the nitrogen vacancies, could be responsible for the variation in EWF that is observed [7]. Whereas, the samples of the Al(40 nm)/ TiN(20 nm)/SiO2/p-Si(1 0 0) structure undergoing the same process show a very different trend. As can be seen in Fig. 5b, VFB firstly shifts to the positive direction. Then it shifts to the negative direction again as the thermal budget increases. Comparing with TiN metal gate samples, the shift of VFB for the Al/TiN stack is obviously not due to the variation of the TiN structure. It should be attributed to the introduction of the Al. EWF is further extracted by the relationship of VFB versus the equivalent oxide thickness for various samples, i.e., Eq. (1),

Fig. 3. The XRD of the Al/TiN/SiO2/p-Si(1 0 0) structure as-deposited and after FGA.

V FB ¼

WM  WS Nf EOT  q qeo eox

ð1Þ

where WM, WS, Nf, eox, eo, EOT and q is the work function of metal gate, the work function of silicon substrate, the areal density of the fixed charges in SiO2 layer, the permittivity of the SiO2 layer, the vacuum permittivity, the equivalent oxide thickness and the electron charge, respectively. As shown in Figs. 6 and 7, the ex-

X.-R. Wang et al. / Microelectronic Engineering 88 (2011) 573–577

Fig. 4. SIMS profiles of Al species in the Al/TiN/SiO2/p-Si(1 0 0) structure after FGA.

575

Fig. 6. VFB versus EOT plot for EWF extraction for the Al/TiN/SiO2/p-Si(1 0 0) stack for all the different anneal condition, including the reference of TiN and Al metal gate.

Fig. 7. EWF of the different annealing time at 600 °C for the Al/TiN/SiO2/p-Si(1 0 0) stack, all the samples having a forming gas annealing, including the reference of TiN and Al metal gate.

Fig. 5. High-frequency C–V characteristics for (a) TiN/SiO2/p-Si(1 0 0) structure and (b) Al/TiN/SiO2/p-Si(1 0 0) structure for all the different anneal condition.

tracted EWF of the TiN metal gate is 4.98 eV after FGA, which is suitable for the gate material of PMOS. For the Al/TiN stack metal gate, the EWF is lowered to 4.44 eV after FGA. But it increases gradually as the anneal time increases from 15 s to 1 min at 600 °C. This should attribute to the formation of the interface Al–O–Si dipole arising from the further diffusion of Al to the TiN/SiO2 interface. The shift of EWF towards the Si valence band edge, ascribed to

the interface-dipole layer involving Al oxide formed at the gate– dielectric interface, has been reported by Chen et al. [8]. A similar EWF increase has also been reported and related to the Pauling electronegativity values for Al, O, and Si which are known to be around 1.61, 3.44, and 1.9, respectively [9]. It is believed that the existence of Al at the electrode side of the TiN/SiO2 interface could result in additional dipole formation (Al–O–Si), resulting in electron transfer from the Al due to lower electronegativity of Al with respect to Si and O. This could lead to the barrier-height increase resulting in an increase in the EWF. However, the samples only with FGA have a lower work function than TiN. It is speculated that the Al oxide cannot form in the forming gas ambient at a low temperature of 400 °C. So the work function of Al will play an important role in these samples. When the anneal time further increases, the EWF shifts to the Si conductance band again. The EOT also has a little increase at the same time as shown in Fig. 5b. Fig. 8a and b confirms the further diffusion of Al into the interface of TiN/SiO2 as the thermal budget increases, i.e., a large number of Al appearing at the TiN/SiO2 interface for the sample annealed at 600 °C with 10 min. With so many

576

X.-R. Wang et al. / Microelectronic Engineering 88 (2011) 573–577

Fig. 9. Interface trap density Dit of the Al/TiN/SiO2/p-Si stack with different anneal conditions calculated from both high-frequency C–V and photonic high-frequency C–V curves.

Fig. 8. AES profiles of Al species in the Al/TiN/SiO2/p-Si stack for different anneal conditions (a) only having FGA and (b) 600 °C 10 min anneal in N2 ambient and FGA.

Al atoms and the long enough annealing time at such a high temperature, a thin layer of Al oxide may form at the interface, which should be responsible for the increase of the EOT. This Al oxide layer may also stop the further oxidation of Al due to its special passivation property. Then it is the un-oxidized Al instead of the interface dipole that will influence the EWF of the Al/TiN gate stack, which makes the EWF decrease again due to the so low work function of Al. The comparison between high-frequency C–V and photon (laser)-assisted high-frequency C–V curves can be used to evaluate the interface state density Dit of the Al/TiN stack metal gate. Fig. 9 reveals that the introduction of Al does not increase the Dit around the midgap region of the Si substrate. Hence, it would not result in reliability problems in the Al/TiN/SiO2/p-Si structure. Since the introduction of Al in TiN by thermal annealing and diffusion can so effectively lower the EWF of the metal gate, the new experiments of TixNyAl1xy metal gate formation by direct cosputtering of Al and Ti target in Ar/N2 ambient is carried out. The content of Al was controlled by tuning the sputtering power on the Al target as 50 W, 75 W,100 W and 125 W, respectively. Since all the samples only had a single FGA at 400 °C, no Al oxide will likely form in the interface, then the work function of Al will play an important role. Fig. 10 demonstrates that the EWF gradually shifts to the conductance band edge of Si as the power on the Al target increases, which indicates the more Al atoms exist in the interface, the lower EWF can be obtained even without further thermal annealing.

Fig. 10. High-frequency C–V curves of the TixAlyN1xy/SiO2/p-Si(1 0 0) stack using the co-sputtering of Ti and Al in the N2 included ambient.

4. Conclusions The thermal annealing effect on the metal gate EWF modulation for the Al/TiN/SiO2/p-Si(1 0 0) structure was investigated in this paper. For the TiN metal gate, the EWF is proved to be as high as 4.98 eV, which is only suitable for the PMOS devices. For the Al/ TiN gate stack, the EWF can be modulated effectively to 4.4 eV simply by adjusting the annealing conditions. Material characterizations demonstrate that the Al diffusion into the interface between TiN and SiO2 should be responsible for the EWF modulation. It is further revealed that the annealing condition may determine the existent state of Al, i.e., the formation of Al–O–Si dipole or Al oxide, which will modulate the EWF to contrary directions. The experimental results also show that the introduction of Al does not cause reliability problem for the Al/TiN/SiO2/p-Si structure. The EWF of Al/TiN stack can be further optimized suitable for NMOS metal gate materials simply by adjusting the process conditions. Therefore, the TiN and Al/TiN stack can be used as gate materials for PMOS and NMOS devices, respectively, on the base of no process complication.

X.-R. Wang et al. / Microelectronic Engineering 88 (2011) 573–577

Acknowledgements The work was supported by Natural Science Foundation of China (NSFC-60976074, NSFC-90607018), Shanghai-Applied Materials Research and Development Fund (09700714200, 07SA06), Fok Ying Tong Education Foundation (114006), and International Research Training Group ‘‘Materials and Concepts for Advanced Interconnects”.

References [1] ITRS, International Technology Roadmap for Semiconductors, 2006 Update, .

577

[2] C. Hobbs, L. Fonsesca, V. Dhandapani, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, P. Tobin, in: Tech. Dig. VLSI Symp., 2003, p. 9. [3] Masaru Kadoshima, Takeo Matsuki, Seiichi Miyazaki, Kenji Shiraishi, Toyohiro Chikyo, Keisaku Yamada, Takayuki Aoyama, Yasuo Nara, Yuzuru Ohji, IEEE Electron Dev. Lett. 30 (2009) 466–468. [4] Jörgen Westlinder, Gustaf Sjöblom, Jörgen Olsson, Microelectron. Eng. 75 (2004) 389–396. [5] W.H. Wu, B.Y. Tsui, Y.P. Huang, F.C. Hsieh, M.C. Chen, Y.T. Hou, Y. Jin, H.J. Tao, S.C. Chen, M.S. Liang, IEEE Electron Dev. Lett. 27 (2006) 399–401. [6] Ch. Wenger, M. Lukosius, I. Costina, R. Sorge, J. Dabrowski, H.-J. Müssig, S. Pasko, Ch. Lohe, Microelectron. Eng. 85 (2008) 1762–1765. [7] J. Westlinder, T. Schram, L. Pantisano, E. Cartier, A. Kerber, G.S. Lujan, J. Olsson, G. Groeseneken, IEEE Electron Dev. Lett. 24 (2003) 550–552. [8] Bei Chen, Rashmi Jha, Veena Misra, IEEE Electron Dev. Lett. 27 (2006) 731–733. [9] R. Singanamalla, H.Y. Yu, B. Van Daele, S. Kubicek, K. De Meyer, IEEE Electron Dev. Lett. 28 (2007) 1089–1091.