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Application-Specific Integrated Circuits
31/1
31
ApplicationSpecific Integrated Circuits J Berry,BSc(Hons) LSI Logic Ltd
Contents 31.1 Introduction 31/3 31.2 Arrays and cells 31/3 31.2.1 Arrays 31/3 31.2.2 Cells 31/4 31.3 The reasons for choosing an ASIC 31/5 31.4 The design process 31/5 31.5 Selecting the ASIC 31/6 31.5.1 General considerations 31/6 31.5.2 System clock speed 31/6 31.5.3 Critical path performance, design architecture 31/7 31.5.4 Operating conditions 31/7 31.5.5 Gate count 31/7 31.5.6 Standard products and compiled functions and cells 31/7 31.5.7 On-chip storage requirements 31/8 31.5.8 Replicated logic blocks 31/8 31.5.9 Signal pins, partitioning and interfacing 31/8 31.5.10 Packaging requirements 31/9 31.5.11 Summary 31/9
Arrays and cells
31/3
31.1 Introduction
31.2 Arrays and cells
Integrated circuits destined for one specific application are termed ASICs—application-specific integrated circuits. These devices form one of the fastest growing sectors of the electronic market (see Figure 31.1). With well over 100 companies competing in this area, it is also the fastest evolving and most exciting segment. Figure 31.2 shows the changing technology and maximum complexity associated with the ASIC market. The proliferation of technologies and terms used to describe the various product offerings should not be a barrier to using and taking advantage of ASICs. This chapter defines what an ASIC is, the potential advantages ASICs offer over other design approaches, the method of design, how to choose an ASIC and the factors that must be considered when selecting both the most appropriate ASIC and the vendor of that product.
ASICs fall into two quite distinct groups—arrays and cells. Arrays, more frequently called gate arrays, are personalised by the final processing steps only. The other group consists of cellbased circuits often called standard cells. They differ from arrays in that all processing steps are used for personalisation. Figure 31.3 shows the two groups.
Figure 31.1 1987)
European consumption of ASICs (Source: SEMSTAT
31.2.1 Arrays Arrays were first conceived in the early 1970s when Ferranti introduced their ULAs* (uncommitted logic arrays). These chips * ULA is a registered trademark of Ferranti
Figure 31.2
Single chip complexity
cell-based processing Figure 31.3 Array- and cell-based processing
31/4
Application-specific integrated circuits
consist of a regular array of uncommitted (or unconnected) logic elements. A peripheral area surrounds the internal array structure to provide a signal interface and power supply connections. Figure 31.4 shows this arrangement, unchanged in principle to this day. Semi conductor die
each uncommitted 'gate' on all sides. An alternative is to produce rows or columns of uncommitted gates with dedicated routing channels between them, known as a channelled array. Routing is achieved in one direction in the 'routing channels'. The other direction is routed across the columns in unused routing slots. Additional routing can be made but at the expense of some gates. This approach to routing can be extended to both directions allowing the sea of gates or Channel-Free* architecture where no dedicated routing channels are included. Clearly gates are lost to routing but the extra gates gained using such an architecture far outweigh these losses. The most important factor is the actual number of usable gates. Interconnection between components and gates may be achieved using metal, poly silicon or diffusions. The most predictable is metal and this is certainly the most common today. In many cases two layers of metal are used, occasionally three. For designs up to about 50 MHz clock the various interconnection methods generally affect only utilisation (the maximum number of usable gates possible compared to the number available). Higher performance devices can require separate routing layers for clock and power and need a very full review before designing in detail.
31.2.2 Cells Figure 31.4
Basic array structure
Arrays are processed in high volumes up to the point at which personalisation begins and they are then stockpiled. Economies of scale result from this approach. The limited processing required for personalisation also results in minimal turnround time for array designs. Peripheral buffers surround the array elements and are used for several purposes. They can be used as power supply connections or as input buffers (also supplying electrical protection for the internal gates) or output buffers. Tristate capability is usually possible, as are bidirectional buffers. Different manufacturers will have specific rules as to possible options, electrical characteristics and the capabilities which may include pull ups, pull downs, and open drain (or source, collector). The internal array elements each consist of a number of components. The interconnection defines the final function of each element. An example for a CMOS array where each element consists of four transistors (two n-type and two p-type) is shown in Figure 31.5.
Cell-based designs do not really differ a great deal from arrays. The most major difference is that all layers are customised as opposed to just the top layers. This allows extra flexibility not possible for arrays. First only used gates are made (arrays usually have a number of unused transistors left over'). This allows a continuous spectrum of device sizes. However, the argument is complicated by being able to alter the size of transistors used in the gates. This produces a gate that uses less area than for arrays. Figure 31.6 shows the relationship between internal gate area and used gates with both fixed and variable transistor sizes.
Figure 31.6
Figure 31.5
Examples of element interconnections
The internal architectural arrangement of the gates has several possibilities. One is shown in Figure 31.4, with room around
Area usage curve
This reduced area of silicon can result in lower production costs, particularly at higher volumes. This is offset by the higher development cost for cells. Since all layers are customised, many more masks (about ten more) are required for cells than for arrays. This results in additional tooling costs. The additional processing steps also result in longer turnround times than for arrays. Figure 31.7 shows the comparative cost relationship for * Channel Free is a registered trademark of LSI Logic Corporation
The design process
31/5
Time to market The design automation possible with ASICs allows for very rapid design when compared with alternative approaches. The surety of getting good parts back in a short time after design completion (one week is quite possible from some vendors) allows early entry of the final product to the market place. The proprietory features are also well protected, ensuring that the competitive edge is retained for as long as possible.
31.4 The design process The essential steps of the design process are shown in Figure 31.8.
Figure 31.7 Comparative costs of array-based as opposed to cell-based designs
the total spend on a project, totalling the development cost and production costs across the lifetime of the product.
31.3 The reasons for choosing an ASIC The electronic part of a system can be implemented in a variety of different ways, each with its own set of advantages. ASICs offer advantages in cost, performance, time to market, power consumption, reliability and size. Cost The cost of manufacturing and maintenance are dramatically reduced because of fewer parts on smaller or fewer boards. This leads to less inventory, assembly and testing. The reduced power consumption also reduces costs of power supplies and cooling requirements whilst increasing reliability. An example of an actual product costing is given in Table 31.1. Table 31.1 ASIC costing example: typical 4000-gate system, 10 000 production volume
TTL-based system 65 SSI/MSI TTL ICs ($) Breadboarding Chip development PC board (20/sqin) Components Assembly ($2/part)
ASIC system one ASIC chip ($)
6000 0
0 45000
162000 390000 1300000
90000 300000 20000
1858 000
455 000
Source: EDN 1984, Advanced Technology Research 1986 and LSI Logic
Size When compared to standard product implementations the ASIC offers a greatly reduced size. Compare the external size of a 30-gate TTL MSI (medium scale integration) part to that of a microprocessor of 1000 or more times the complexity. This can result in significant weight savings as well. Performance The performance of an ASIC-based system can be dramatically improved over the standard product approach. Removal of buffers is a clear benefit. However, the ability to optimise the design, potentially with added features, also brings improvements to performance. Early access to the next generation of technology and reduction in power consumption increases performance still further.
Figure 31.8 The design and manufacturing process
The design concept is arrived at gradually. The method of implementation and technology chosen will affect the feasibility of the project. Software tools such as behavioural simulators allow a very high-level description of the design or entire system to be made. This description may be simulated to check the concept. The model can then be split into appropriate sections and the descriptive detail increased. Since each piece can be worked on separately the design effort is eased and design time reduced. Continuing this process leads to a fully described and optimally partitioned system. Design entry consists of conversion of the behavioural description to the ASIC vendor's library elements. Ideally the behavioural simulator allows these gate-level implementations to be substituted for their equivalent behavioural block allowing full proof of a correct conversion. Verification of this design can now proceed. Functionality, performance, testability and package must all be carefully verified against the original specification. Layout must now be completed, preferably by the ASIC vendor, with full checking after this process against the original specification. Production test patterns are extracted at this stage.
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Application-specific integrated circuits
After full approval has been given the prototypes are fabricated in the vendor's facility. The test sequence is then used on the wafers (to determine good devices) before the wafer is sawn into die. Good die are packaged to the required pinout and then fully tested against the production test patterns. On delivery the prototypes must be very carefully checked. It is only on this final acceptance that all the design details can be released to production. Vendors each have their own specific flow, but all adhere in general to these steps. Where the sequence is not followed the risk of design failure is greatly increased.
31.5 Selecting the ASIC With a wide range of different ASICs available it is important that a careful selection is made as to the most appropriate ASIC. Table 31.2 Product type comparison
Description
Advantages
Array products
Cell-based products
Metal programmable
Full custom diffused and metalised Full custom silicon
Pre-diffused masterslice Fastest development cycle Smallest feature size Lower development costs
Highest complexity Smallest die size Lower piece parts costs
This section describes the factors to be considered in that selection process. 31.5.1 General considerations Select array productsfirstand only move to cell-based products when a clear advantage exists. Array products provide access to the most recent technology and provide for very rapid product development. When product lifetimes are short and upgrades or redesigns are likely, the lower development cost is a benefit. Cell-based products are more suitable for designs that have a high-volume production requirement (when the smaller die size allows a lower piece part cost) or the degree of complexity exceeds that available on array products at the time of design definition. Table 31.2 compares the product types. A list of available products from LSI Logic is included in Table 31.3 as an example of the devices available from one vendor. 31.5.2 System clock speed A smaller MOS device geometry will produce shorter gate delays and improve device performance. Thus an approximate, but very rapid, assessment of the technology required can be made simply by using the system clock rate. Table 31.4 indicates the MOS technology geometries that will support a range of system clock rates. Once the selection of technology has been made a more detailed analysis of critical paths (see Section 31.5.3) is required to confirm the choice. The availability of such high-performance CMOS products minimises the design effort needed for high-performance chip design.
Table 31.3 Product range from LSI logic Device number
Estimated usable gates
Available gate complexity
Total pads
Max I/O pads
Channel-Free arrays LMA9000—micro array LMA9020 LMA9033 LMA9050 LMA9072 LMA9095 LMA9141 LMA9190 LMA9239 LMA9284
700 1200 1750 2500 3 300 5000 6700 8400 10000
1968 3286 4992 7238 9 504 14124 19000 23 908 28 388
44 58 70 86 98 118 138 154 168
41 55 67 80 92 110 130 144 158
LCA10000—compacted array LC A10026 LCA10038 LC A10051 LCA 10075 LCA 10100 LCA10129
10000 15000 20000 30000 40000 50000
25740 37 932 50904 74970 100182 129042
168 204 234 282 326 368
154 184 214 262 306 348
LCA100K—compacted array pl\us LCA100139 60000 80000 LCA100188 LCA 100237 100000
139104 187 748 236880
340 392 436
320 372 416
20
18
348
256
Cell-based LCB15—structured cell LCB1501
—
LCBÍ560
10Ò000
Selecting the ASIC Table 31.4 A guide to potential device technology
System clock rate (MHz)
Largest geometry (¿mi)
<25 <40 <60 <80 <100
Drawn
Effective
Typical relative gate delay (ns)
3.0 2.0 1.5 1.5 1.0
2.4 1.5 1.1 0.9 0.7
2.4 1.4 1.0 0.57 0.46
31/7
The use of a chip floorplanner is frequently advantageous to provide the designer the ability to pre-place critical hierarchical blocks to give optimum performance with minimum interconnect delays. This high-level approach is particularly useful for larger designs. 31.5.4 Operating conditions
The smaller the geometry used the lower the power consumption of the final device. An example is a 33 % reduction when 1.5 ¡xm technology is used in place of 2.0 /¿m technology for an identical function. This can often allow the selection of a lower cost plastic package. After processing, the effective length is lower than the original drawn gate (see Table 31.4). The performance is related to the effective length (Leff) that results after processing. The use of bipolar transistors in standard bipolar or BiCMOS processes provides for very high performance where designs of 1 GHz or higher are possible. Also different technologies such as SOS (silicon on sapphire) or materials such as GaAs (gallium arsenide) can produce devices of higher performance than CMOS. However, CMOS is by far the dominant ASIC technology. 31.5.3 Critical path performance, design architecture A circuit will have a path (or paths) that is the limiting factor to performance. The total propagation delay down a path is the sum of the individual cell delays on the path, considering the polarity of the output change. The rise and fall propagation delays of each cell depend on a number of factors, which for estimation purposes can be considered to be technology, device and fanout loading. Fanout loading is the load presented to the output of a gate by all of the gates connected to that output and the connections themselves. For the example in Figure 31.9 the delays have been calculated for a particular path between two flip-flops for a 0.9 /im CMOS technology.
Device performance is affected by the supply voltage, the junction temperature and the processing tolerance. These factors are described in the relevant product data sheets. The processing tolerances are technology dependent, so check these carefully. The effect on delays is global and a simple multiplying factor is applied to the complete delay path. Table 31.5 summarises these factors for the LSI Logic LMA9000 series. For example shown in Figure 31.9, the worst case commercial path delays would be 8.6 ns (AA goes high) and 10.8 ns (AA goes low) (i.e. the nominal delay x 1.86). Junction temperature should initially be assumed to be the same as the ambient temperature. However, where timing is marginal a more accurate calculation should be performed including the effect of temperature rise caused by power dissipation. All these factors (and others) must be taken into account by the design system used, e.g. LDS* for LSI Logic, to ensure the provision of accurate and dependable delay predictions for all paths including the critical ones. 31.5.5 Gate count Taking a block diagram of the circuit under consideration and partitioning the circuit hierarchically allows a rapid estimation of the gates required. Specific data books and design manuals provide the gate counts for the majority of the smaller elements (e.g. NAND gates and flip-flops) used in a design. Gate counts for many of the larger standard functions, e.g. 29xxx, 82xx and generic functions, may be provided by some vendors. If the design being considered uses standard products, this will be particularly useful, saving a very large amount of design effort and ensuring correct functionality (see Section 31.5.6). Having established a gate count for designs consisting solely of random logic, use the following product family dependent guidelines: (1) Arrays Use the available usable gates published in the data sheet to determine the minimum size practicable. (2) Cell-based designs Area calculations are required (see the relevant data sheets or consult the vendor).
Input signal AA
FD1 FO = 4
ND2 FO = 3
Goes high Goes low
1.9 1.7
Figure 31.9
Calculating critical path delay
0.5 1.1
ND4 FO = 4
1.4 1.2
FD1 set-up
0.8 0.8
Typical path delay (ns) 4.6 5.8
The internal elements use standard drive gates in this example. Substituting high drive gates will improve critical path performance. Careful consideration of the design architecture (pipelining, parallel processing) can significantly improve the performance obtainable.
Table 31.3 indicates estimated usable gates available for some products. This is a guideline only as the true number is design dependent. A review by the vendor is recommended and some would usually insist upon this design review. Many designs do, however, have elements with a higher density. The following sections examine these elements and the effect they have on design size. 31.5.6 Standard products and compiled functions and cells Small standard products (i.e. 7474) are generally available in the macrocell library. Medium sized standard products (i.e. 4-bit counters) are frequently available as macrofunctions in the ASIC vendor's library. Medium to large functions (i.e. ALUs, barrel shifters, multipliers and many other industry standard functions) are available in extended libraries as megafunctions. They are provided with complete test patterns greatly easing test program generation for the total design. For Channel-Free arrays these may also be available as metal megacells optimised for size and * LDS is a registered trademark of LSI Logic Corporation
31/8 Application -specific integrated circuits Table 31.5 Delay multiplieir for different operating conditions (LMA9000 series) Combined
Factors
Worst case conditions
Commercial Industrial Military
Supply voltage (V)
Junction temperature (°C)
Processing tolerances
5 + 5% 5 + 5% 5+10%
- O t o +70 - 4 0 to +85 - 5 5 to +125
0.6-1.5 0.6-1.5 0.6-1.5
performance. This optimisation in size is not practicable where routing channels are used because of the varying channel width with array complexity. For cell-based products these functions may be available as fully diffused megacells. When a particular element is available as a megacell the effective logic density is significantly increased. Consult current lists for available standard functions and megacells. Table 31.6 summarises the types of available logic building blocks. Table 31.7 gives gate counts for some standard functions. When a required function or cell is not contained in a library or some customisation is necessary, consider constructing that function from existing cells and functions or compiling a new cell. A range of compilers is available (see Table 31.8). These may be used to advantage reducing design size and enhancing performance. The contents of the libraries are constantly enlarged based on the varying requirements of designers. They may thus become the generic functions described earlier.
xl.86 x 1.96 x2.38
Table 31.8 Compilers
Logic compilers Schematic compilers Memory compilers Logic synthesis interface compilers Data path compiler
Multipliers, adders, shifters, counters and other logic functions Netlist to schematic conversion RAM with multiport options ROM with very wide words practicable, conversion of state machine tables, Boolean equations, truth tables, fuse maps and PL As to optimised logic equivalents Data path architecture design and conversion to megafunctions and megacells
31.5.7 On-chip storage requirements Table 31.6 Logic building blocks
Macro cells Low-complexity building block Examples : NAND, NOR, FLIP-FLOP Fixed transistor interconnection Fully characterised
Mega cells High-complexity building block Examples : RAM, ROM, ALUs, UARTs Fixed and optimised interconnection Fully characterised
Macro functions Medium-complexity building block Examples : COUNTERS, ADDERS Combinations of macrocells Performance layout dependent
Mega functions High-complexity building block Examples : RAM, ROM, ALUs, UARTs Combinations of macrocells Performance layout dependent
Table 31.7 Gate counts for some standard functions
Function
Description
Gate count
2901 2910 8254 8259A
4-bit slice ALU 12-bit microprogram controller Programmable interval timer Programmable interrupt controller 32-bit carry select adder 16 x 4 content addressable memory 16 x 16 two's complement multiplier
1006 1182 3046 1246 643 636 2099
RAM and ROM can be implemented on ASICs and provide fast local memory. Dedicated blocks of memory (megacells) are very dense and fast. Select product type based on the amount of RAM or ROM required. Table 31.9 shows examples of memory limits on ASIC products, and Table 31.10 gives some performance examples. Small amounts of RAM and ROM can be converted to gates using latches and combinatorial logic alone. Sections of ROM can be converted to optimised combinatorial logic using logic synthesis (LLS is one of LSI Logic's compiler tools). Such converted areas can be included on any ASIC product. 31.5.8 Replicated logic blocks Designs that have a significant amount of random logic that is formed from repeated sections can benefit from the creation of a metal megacell. The repeated section is treated as a single element and typically has a greater logic density. Since the metal megacells are generated as tiles, the allowance for block interconnect is minimal. The identical layout of each section results in a repeatable performance which can be of significant performance advantage. Table 31.11 compares the relative logic density for all the various styles of implemented logic on Channel-Free arrays. 31.5.9 Signal pins, partitioning and interfacing The periphery of every die contains the buffers and associated bonding pads used in packaging. The number of pads a device will need is determined by the sum of input, output and bidirectional signals used in the design and the power and ground requirements of the device. Refer to the device data sheets for specific details but, in general, all inputs and standard drive outputs and bidirects use only one pad.
Selecting the ASIC 31/9 Table 31.9 Suggested limits of memory on ASIC products Product Micro array Compacted array Compacted array plus Cell-based
LMA9000 LC A10000 LCAIOOK LCB15
Maximum bits of RAM
Maximum bits of ROM
Comments
4K 8K 32K 72K
16K 64K 128K 512K
Metal megacell Metal megacell Metal megacell Megacell
Table 31.10 Examples of memory performance for LMA9000
Table 31.12 Pads available on LMA9000 series
Memory block
Configuration
Typical performance (ns)
Device number
Estimated user gates
Available gate complexity
V¿¿
RAM RAM ROM
256x8 64 x 8 256x8
10.0 9.2 12.0
LMA9020 LMA9033 LMA9050 LMA9072 LMA9095 LMA9141 LMA9190 LMA9239 LMA9284 LMA9350
700 1200 1750 2 500 3 300 5000 6700 8400 10000 12 500
1968 3286 4992 7238 9 504 14124 19000 23 908 28 388 34944
1 1 1 2 2 2 2 4 4 4
Table 31.11 Relative logic densities for Channel-Free arrays
Percentage ROM Single-port RAM Multiport RAM Metal megacell Registered logic Typical utilisation Random logic
90 75 70 50 45 40 35
Device pads Vss
I/O
3
70 54 66 80 92 110 130 144 158 174
3 3 4 4 6 6 6 6 8
pad limited designs. When several designs are required for one system, repartitioning the circuit can radically alter pin count/gate ratios, potentially eliminating pad-limited designs. 31.5.10 Packaging requirements
A simple calculation then defines the minimum number of Vss and V¿¿ pads required to adequately support the device for all conditions. When possible, add additional pads. These reduce noise induced by the current power demands of switching outputs since a small resistance exists in the power supply metal. The switching current for a CMOS output buffer may be ten times the maximum static current. It is the dynamic current consumption that must be allowed for. These induced voltages also have the effect of reducing noise immunity on all inputs that share the same power rails. For this reason more advanced products (e.g. Compacted Arrays from LSI Logic) split the power supply rails (three Vss and two Vdd power supply rails). The total number of pads defines the minimum chip size required. Table 31.12 shows the pads available for the LMA9000 series. It may be necessary to configure additional I/O pads for Kdd/Kjs» depending on the number and drive of the output buffers. When the number of usable gates is less than that required (pad-limited design), a larger device must be selected. Partitioning the circuit in several different ways can provide an improved solution for multi-chip designs. The output buffer slew rate can be altered on some vendor's products by appropriate selection of output buffer type (none, moderate or full). This very beneficial feature slows the rate of rise and fall of the chosen output without affecting the steadystate drive capability. This reduces the power requirements (there is a reduction in peak dynamic current) and system noise (less radiated signal noise). Use slew rate control wherever practical. High drive output buffers will use more pads and require more power supply pads. Reassess the device interface needs, to avoid
The package must be able to accept the chosen device. Cavity size available for packages limits the size of device that may be used. The package selected must have sufficient pins for I/O and power supply. Pin grid arrays offer highest pin counts. The package must meet the requirements of the manufacturing process. Pin grid arrays are 'through board', while most chip carriers are surface mounted. The package must suit its operating environment. Ceramic packages are the most robust and can dissipate the most heat, while cavity down packages enable heatsinks to be mounted on them. Unique requirements can also be accommodated. Figure 31.10 gives the presently available range of packages. Packaging technology is currently evolving very rapidly and new developments offer many possibilities not currently easily available. The use of multichip assemblies, new substrate materials and electrical connection techniques all offer exciting possibilities for the near future. 31.5.11 Summary The various factors influencing the choice of ASIC have been addressed above more or less in isolation. In practice, many are interrelated and thus several iterations may be required to obtain the perfect choice. However, unless the design is stretching the limits of technology, it is more important to consider the design from the point of view of how to ensure that the ASIC is a success. This is particularly true for the first ASIC design which will inevitably be accompanied by justified concern at the potential risk in terms of cost and wasted time and effort. From the company point of view a failure at this point may adversely affect
31/10
Application-specific integrated circuits
Figure 31.10
Current range of packages
decisions on taking advantage of the ASIC technology available for several years. It is clear that ASICs are very attractive in terms of their cost, size,, power consumption, reliability and the degree of design security offered over alternative solutions. It is not clear what to do in order to produce one. The various horror stories that circulate coupled with over a hundred potential vendors make choices difficult. The potential investment in software and workstations and the concern over repercussions if the design has an error worsen the situation. It is therefore necessary to use the first ASIC as a learning vehicle. In many respects this is a similar situation to the introduction of microprocessors. Engineers must have hands-on experience to remove confusion and learn new skills. Training in jnanagement, manufacturing and procurement is also required. The approach to use is to choose a major ASIC supplier that you can be certain is doing a large number of designs a year. Check the company's ASIC success record and future stability by asking for ten references and checking the financial situation. Go directly to the ASIC vendor rather than through a third party to keep communications as direct as possible, to learn from their experience. Choose the most reliable supplier to keep the chances of success as high as possible. The small cost penalty would be small compared to the cost of failure. The time for high-risk ventures is after the first success. Select an HCMOS technology. This is the most used, is easily available and yet offers high performance. Also use a mediumsized array for the first design to minimise cost and risk. With a design of 2000-5000 gates the design is simple enough to complete in three to six weeks and yet complex enough to be a valuable learning vehicle. Preferably choose an existing design that has not been implemented with ASICs. Any delays in obtaining the ASIC can be buffered by maintaining existing production. The package selection should be done in consultation with manufacturing to avoid an unusable device being produced. Purchasing should be involved to check the financial viability of the project and the ASIC vendor. The ASIC vendor's software will be optimised for the product, putting the responsibility for producing parts to specification on the vendor. Use of 'universal' or 'free' libraries again significantly
increases risk of failure. Also, ASIC vendors provide training, usually as a one week class. These provide excellent grounding in ASIC design, testing and the use of the software tools. Go prepared with the questions that must be answered and gain years of experience in just a few days. It is generally possible to do ASIC designs at the vendor's design centre. Expert advice can be immediately sought and concentration on the design is improved, reducing potential delays. Do not be content with simply completing the logic designs. Check the device performance as exhaustively as possible and most importantly derive production tests before committing the design to silicon. Designing good tests retrospectively is fraught with problems and may prove to be impossible. The ASIC vendor should also do the layout. It avoids having to spend time (extra delay) in learning all the layout process and the layout will probably be done quicker as well. The potential for performance 'tweaking' by having 'hands on' is usually unnecessary, given today's technology, and is risky. Checking the design's performance after layout is essential, however, and here software tools can save significant effort. Package pinout. should also be checked. Possibly a full design review is an advantage to catch any last problems. Insisting that all prototypes are fully tested to the production specification by the vendor minimises the risk of delays caused by trying to debug vendor problems. With a test bed prepared and made ready by the designer, the first prototypes can be fully exercised over temperature and voltage. If all of these steps have been followed the probability is that the ASIC will be a complete success.
Further reading ANDREWS, W., 'Designers content with an explosion in ASICs', Comp. Design, 15 April (1988) BUTZERIN, T. et ai, 'ASIC testing with high fault-coverage', VLSI Syst. Design, 9, No. 9, September (1988) CORLETT, R., 'Moving towards analog semicustom ICs', Electron. Syst. Design Mag., 18, No. 10, October (1988) HARA, D. et ai, 'Timing analysis improves efficiency of ASIC design', EDN, 26 May (1988) INGLIS, M., 'ASICs—service versus technology', Electron. Eng., February (1988) KING, H., 'A statistical approach to route estimating', Electron. Product Design, May (1988) LEUNG, S. J. et ai, 'A conceptual framework for ASIC design', IEEE Proc, 76, No. 7, July (1988) MASTERS, N., 'The basics of ASICs', Electron. Design Automation, mid-April/mid-May (1988) MEYER, E., 'Structured arrays re-enter semicustom arena', Comp. Design, 1 January (1989) MOORE, B., 'Consider the tradeoffs when evaluating linearsemicustom ICs', EDN, 4 February (1988) OS ANN, B. et al, 'Compare ASIC capacities with gate array benchmarks', Electron. Design Int., November (1988) PRYCE, D., 'Semicustom I C s ratings and architectures aid analogand digital-circuit designers', EDN, 15 October (1987) PRYCE, D., 'Semicustom ICs combine analog and digital functions', EDN, 8 December (1988) RICE, V., 'Analog/digital chips mix problems with promise', Electron. Business, 1 February (1988) SINGER, P. H., 'Fast turnaround for ASIC photomasks', Semiconductor Int., February (1988) SMITH, T., 'ASICs set the pace in ATE progress', New Electron., April (1988) WHITE, A., 'The painless path to ASIC design', J. Semicustom ICs, 6, No. 1, September (1988)
31
ApplicationSpecific Integrated Circuits J Berry,BSc(Hons) LSI Logic Ltd
Contents 31.1 Introduction 31/3 31.2 Arrays and cells 31/3 31.2.1 Arrays 31/3 31.2.2 Cells 31/4 31.3 The reasons for choosing an ASIC 31/5 31.4 The design process 31/5 31.5 Selecting the ASIC 31/6 31.5.1 General considerations 31/6 31.5.2 System clock speed 31/6 31.5.3 Critical path performance, design architecture 31/7 31.5.4 Operating conditions 31/7 31.5.5 Gate count 31/7 31.5.6 Standard products and compiled functions and cells 31/7 31.5.7 On-chip storage requirements 31/8 31.5.8 Replicated logic blocks 31/8 31.5.9 Signal pins, partitioning and interfacing 31/8 31.5.10 Packaging requirements 31/9 31.5.11 Summary 31/9
Arrays and cells
31/3
31.1 Introduction
31.2 Arrays and cells
Integrated circuits destined for one specific application are termed ASICs—application-specific integrated circuits. These devices form one of the fastest growing sectors of the electronic market (see Figure 31.1). With well over 100 companies competing in this area, it is also the fastest evolving and most exciting segment. Figure 31.2 shows the changing technology and maximum complexity associated with the ASIC market. The proliferation of technologies and terms used to describe the various product offerings should not be a barrier to using and taking advantage of ASICs. This chapter defines what an ASIC is, the potential advantages ASICs offer over other design approaches, the method of design, how to choose an ASIC and the factors that must be considered when selecting both the most appropriate ASIC and the vendor of that product.
ASICs fall into two quite distinct groups—arrays and cells. Arrays, more frequently called gate arrays, are personalised by the final processing steps only. The other group consists of cellbased circuits often called standard cells. They differ from arrays in that all processing steps are used for personalisation. Figure 31.3 shows the two groups.
Figure 31.1 1987)
European consumption of ASICs (Source: SEMSTAT
31.2.1 Arrays Arrays were first conceived in the early 1970s when Ferranti introduced their ULAs* (uncommitted logic arrays). These chips * ULA is a registered trademark of Ferranti
Figure 31.2
Single chip complexity
cell-based processing Figure 31.3 Array- and cell-based processing
31/4
Application-specific integrated circuits
consist of a regular array of uncommitted (or unconnected) logic elements. A peripheral area surrounds the internal array structure to provide a signal interface and power supply connections. Figure 31.4 shows this arrangement, unchanged in principle to this day. Semi conductor die
each uncommitted 'gate' on all sides. An alternative is to produce rows or columns of uncommitted gates with dedicated routing channels between them, known as a channelled array. Routing is achieved in one direction in the 'routing channels'. The other direction is routed across the columns in unused routing slots. Additional routing can be made but at the expense of some gates. This approach to routing can be extended to both directions allowing the sea of gates or Channel-Free* architecture where no dedicated routing channels are included. Clearly gates are lost to routing but the extra gates gained using such an architecture far outweigh these losses. The most important factor is the actual number of usable gates. Interconnection between components and gates may be achieved using metal, poly silicon or diffusions. The most predictable is metal and this is certainly the most common today. In many cases two layers of metal are used, occasionally three. For designs up to about 50 MHz clock the various interconnection methods generally affect only utilisation (the maximum number of usable gates possible compared to the number available). Higher performance devices can require separate routing layers for clock and power and need a very full review before designing in detail.
31.2.2 Cells Figure 31.4
Basic array structure
Arrays are processed in high volumes up to the point at which personalisation begins and they are then stockpiled. Economies of scale result from this approach. The limited processing required for personalisation also results in minimal turnround time for array designs. Peripheral buffers surround the array elements and are used for several purposes. They can be used as power supply connections or as input buffers (also supplying electrical protection for the internal gates) or output buffers. Tristate capability is usually possible, as are bidirectional buffers. Different manufacturers will have specific rules as to possible options, electrical characteristics and the capabilities which may include pull ups, pull downs, and open drain (or source, collector). The internal array elements each consist of a number of components. The interconnection defines the final function of each element. An example for a CMOS array where each element consists of four transistors (two n-type and two p-type) is shown in Figure 31.5.
Cell-based designs do not really differ a great deal from arrays. The most major difference is that all layers are customised as opposed to just the top layers. This allows extra flexibility not possible for arrays. First only used gates are made (arrays usually have a number of unused transistors left over'). This allows a continuous spectrum of device sizes. However, the argument is complicated by being able to alter the size of transistors used in the gates. This produces a gate that uses less area than for arrays. Figure 31.6 shows the relationship between internal gate area and used gates with both fixed and variable transistor sizes.
Figure 31.6
Figure 31.5
Examples of element interconnections
The internal architectural arrangement of the gates has several possibilities. One is shown in Figure 31.4, with room around
Area usage curve
This reduced area of silicon can result in lower production costs, particularly at higher volumes. This is offset by the higher development cost for cells. Since all layers are customised, many more masks (about ten more) are required for cells than for arrays. This results in additional tooling costs. The additional processing steps also result in longer turnround times than for arrays. Figure 31.7 shows the comparative cost relationship for * Channel Free is a registered trademark of LSI Logic Corporation
The design process
31/5
Time to market The design automation possible with ASICs allows for very rapid design when compared with alternative approaches. The surety of getting good parts back in a short time after design completion (one week is quite possible from some vendors) allows early entry of the final product to the market place. The proprietory features are also well protected, ensuring that the competitive edge is retained for as long as possible.
31.4 The design process The essential steps of the design process are shown in Figure 31.8.
Figure 31.7 Comparative costs of array-based as opposed to cell-based designs
the total spend on a project, totalling the development cost and production costs across the lifetime of the product.
31.3 The reasons for choosing an ASIC The electronic part of a system can be implemented in a variety of different ways, each with its own set of advantages. ASICs offer advantages in cost, performance, time to market, power consumption, reliability and size. Cost The cost of manufacturing and maintenance are dramatically reduced because of fewer parts on smaller or fewer boards. This leads to less inventory, assembly and testing. The reduced power consumption also reduces costs of power supplies and cooling requirements whilst increasing reliability. An example of an actual product costing is given in Table 31.1. Table 31.1 ASIC costing example: typical 4000-gate system, 10 000 production volume
TTL-based system 65 SSI/MSI TTL ICs ($) Breadboarding Chip development PC board (20/sqin) Components Assembly ($2/part)
ASIC system one ASIC chip ($)
6000 0
0 45000
162000 390000 1300000
90000 300000 20000
1858 000
455 000
Source: EDN 1984, Advanced Technology Research 1986 and LSI Logic
Size When compared to standard product implementations the ASIC offers a greatly reduced size. Compare the external size of a 30-gate TTL MSI (medium scale integration) part to that of a microprocessor of 1000 or more times the complexity. This can result in significant weight savings as well. Performance The performance of an ASIC-based system can be dramatically improved over the standard product approach. Removal of buffers is a clear benefit. However, the ability to optimise the design, potentially with added features, also brings improvements to performance. Early access to the next generation of technology and reduction in power consumption increases performance still further.
Figure 31.8 The design and manufacturing process
The design concept is arrived at gradually. The method of implementation and technology chosen will affect the feasibility of the project. Software tools such as behavioural simulators allow a very high-level description of the design or entire system to be made. This description may be simulated to check the concept. The model can then be split into appropriate sections and the descriptive detail increased. Since each piece can be worked on separately the design effort is eased and design time reduced. Continuing this process leads to a fully described and optimally partitioned system. Design entry consists of conversion of the behavioural description to the ASIC vendor's library elements. Ideally the behavioural simulator allows these gate-level implementations to be substituted for their equivalent behavioural block allowing full proof of a correct conversion. Verification of this design can now proceed. Functionality, performance, testability and package must all be carefully verified against the original specification. Layout must now be completed, preferably by the ASIC vendor, with full checking after this process against the original specification. Production test patterns are extracted at this stage.
31/6
Application-specific integrated circuits
After full approval has been given the prototypes are fabricated in the vendor's facility. The test sequence is then used on the wafers (to determine good devices) before the wafer is sawn into die. Good die are packaged to the required pinout and then fully tested against the production test patterns. On delivery the prototypes must be very carefully checked. It is only on this final acceptance that all the design details can be released to production. Vendors each have their own specific flow, but all adhere in general to these steps. Where the sequence is not followed the risk of design failure is greatly increased.
31.5 Selecting the ASIC With a wide range of different ASICs available it is important that a careful selection is made as to the most appropriate ASIC. Table 31.2 Product type comparison
Description
Advantages
Array products
Cell-based products
Metal programmable
Full custom diffused and metalised Full custom silicon
Pre-diffused masterslice Fastest development cycle Smallest feature size Lower development costs
Highest complexity Smallest die size Lower piece parts costs
This section describes the factors to be considered in that selection process. 31.5.1 General considerations Select array productsfirstand only move to cell-based products when a clear advantage exists. Array products provide access to the most recent technology and provide for very rapid product development. When product lifetimes are short and upgrades or redesigns are likely, the lower development cost is a benefit. Cell-based products are more suitable for designs that have a high-volume production requirement (when the smaller die size allows a lower piece part cost) or the degree of complexity exceeds that available on array products at the time of design definition. Table 31.2 compares the product types. A list of available products from LSI Logic is included in Table 31.3 as an example of the devices available from one vendor. 31.5.2 System clock speed A smaller MOS device geometry will produce shorter gate delays and improve device performance. Thus an approximate, but very rapid, assessment of the technology required can be made simply by using the system clock rate. Table 31.4 indicates the MOS technology geometries that will support a range of system clock rates. Once the selection of technology has been made a more detailed analysis of critical paths (see Section 31.5.3) is required to confirm the choice. The availability of such high-performance CMOS products minimises the design effort needed for high-performance chip design.
Table 31.3 Product range from LSI logic Device number
Estimated usable gates
Available gate complexity
Total pads
Max I/O pads
Channel-Free arrays LMA9000—micro array LMA9020 LMA9033 LMA9050 LMA9072 LMA9095 LMA9141 LMA9190 LMA9239 LMA9284
700 1200 1750 2500 3 300 5000 6700 8400 10000
1968 3286 4992 7238 9 504 14124 19000 23 908 28 388
44 58 70 86 98 118 138 154 168
41 55 67 80 92 110 130 144 158
LCA10000—compacted array LC A10026 LCA10038 LC A10051 LCA 10075 LCA 10100 LCA10129
10000 15000 20000 30000 40000 50000
25740 37 932 50904 74970 100182 129042
168 204 234 282 326 368
154 184 214 262 306 348
LCA100K—compacted array pl\us LCA100139 60000 80000 LCA100188 LCA 100237 100000
139104 187 748 236880
340 392 436
320 372 416
20
18
348
256
Cell-based LCB15—structured cell LCB1501
—
LCBÍ560
10Ò000
Selecting the ASIC Table 31.4 A guide to potential device technology
System clock rate (MHz)
Largest geometry (¿mi)
<25 <40 <60 <80 <100
Drawn
Effective
Typical relative gate delay (ns)
3.0 2.0 1.5 1.5 1.0
2.4 1.5 1.1 0.9 0.7
2.4 1.4 1.0 0.57 0.46
31/7
The use of a chip floorplanner is frequently advantageous to provide the designer the ability to pre-place critical hierarchical blocks to give optimum performance with minimum interconnect delays. This high-level approach is particularly useful for larger designs. 31.5.4 Operating conditions
The smaller the geometry used the lower the power consumption of the final device. An example is a 33 % reduction when 1.5 ¡xm technology is used in place of 2.0 /¿m technology for an identical function. This can often allow the selection of a lower cost plastic package. After processing, the effective length is lower than the original drawn gate (see Table 31.4). The performance is related to the effective length (Leff) that results after processing. The use of bipolar transistors in standard bipolar or BiCMOS processes provides for very high performance where designs of 1 GHz or higher are possible. Also different technologies such as SOS (silicon on sapphire) or materials such as GaAs (gallium arsenide) can produce devices of higher performance than CMOS. However, CMOS is by far the dominant ASIC technology. 31.5.3 Critical path performance, design architecture A circuit will have a path (or paths) that is the limiting factor to performance. The total propagation delay down a path is the sum of the individual cell delays on the path, considering the polarity of the output change. The rise and fall propagation delays of each cell depend on a number of factors, which for estimation purposes can be considered to be technology, device and fanout loading. Fanout loading is the load presented to the output of a gate by all of the gates connected to that output and the connections themselves. For the example in Figure 31.9 the delays have been calculated for a particular path between two flip-flops for a 0.9 /im CMOS technology.
Device performance is affected by the supply voltage, the junction temperature and the processing tolerance. These factors are described in the relevant product data sheets. The processing tolerances are technology dependent, so check these carefully. The effect on delays is global and a simple multiplying factor is applied to the complete delay path. Table 31.5 summarises these factors for the LSI Logic LMA9000 series. For example shown in Figure 31.9, the worst case commercial path delays would be 8.6 ns (AA goes high) and 10.8 ns (AA goes low) (i.e. the nominal delay x 1.86). Junction temperature should initially be assumed to be the same as the ambient temperature. However, where timing is marginal a more accurate calculation should be performed including the effect of temperature rise caused by power dissipation. All these factors (and others) must be taken into account by the design system used, e.g. LDS* for LSI Logic, to ensure the provision of accurate and dependable delay predictions for all paths including the critical ones. 31.5.5 Gate count Taking a block diagram of the circuit under consideration and partitioning the circuit hierarchically allows a rapid estimation of the gates required. Specific data books and design manuals provide the gate counts for the majority of the smaller elements (e.g. NAND gates and flip-flops) used in a design. Gate counts for many of the larger standard functions, e.g. 29xxx, 82xx and generic functions, may be provided by some vendors. If the design being considered uses standard products, this will be particularly useful, saving a very large amount of design effort and ensuring correct functionality (see Section 31.5.6). Having established a gate count for designs consisting solely of random logic, use the following product family dependent guidelines: (1) Arrays Use the available usable gates published in the data sheet to determine the minimum size practicable. (2) Cell-based designs Area calculations are required (see the relevant data sheets or consult the vendor).
Input signal AA
FD1 FO = 4
ND2 FO = 3
Goes high Goes low
1.9 1.7
Figure 31.9
Calculating critical path delay
0.5 1.1
ND4 FO = 4
1.4 1.2
FD1 set-up
0.8 0.8
Typical path delay (ns) 4.6 5.8
The internal elements use standard drive gates in this example. Substituting high drive gates will improve critical path performance. Careful consideration of the design architecture (pipelining, parallel processing) can significantly improve the performance obtainable.
Table 31.3 indicates estimated usable gates available for some products. This is a guideline only as the true number is design dependent. A review by the vendor is recommended and some would usually insist upon this design review. Many designs do, however, have elements with a higher density. The following sections examine these elements and the effect they have on design size. 31.5.6 Standard products and compiled functions and cells Small standard products (i.e. 7474) are generally available in the macrocell library. Medium sized standard products (i.e. 4-bit counters) are frequently available as macrofunctions in the ASIC vendor's library. Medium to large functions (i.e. ALUs, barrel shifters, multipliers and many other industry standard functions) are available in extended libraries as megafunctions. They are provided with complete test patterns greatly easing test program generation for the total design. For Channel-Free arrays these may also be available as metal megacells optimised for size and * LDS is a registered trademark of LSI Logic Corporation
31/8 Application -specific integrated circuits Table 31.5 Delay multiplieir for different operating conditions (LMA9000 series) Combined
Factors
Worst case conditions
Commercial Industrial Military
Supply voltage (V)
Junction temperature (°C)
Processing tolerances
5 + 5% 5 + 5% 5+10%
- O t o +70 - 4 0 to +85 - 5 5 to +125
0.6-1.5 0.6-1.5 0.6-1.5
performance. This optimisation in size is not practicable where routing channels are used because of the varying channel width with array complexity. For cell-based products these functions may be available as fully diffused megacells. When a particular element is available as a megacell the effective logic density is significantly increased. Consult current lists for available standard functions and megacells. Table 31.6 summarises the types of available logic building blocks. Table 31.7 gives gate counts for some standard functions. When a required function or cell is not contained in a library or some customisation is necessary, consider constructing that function from existing cells and functions or compiling a new cell. A range of compilers is available (see Table 31.8). These may be used to advantage reducing design size and enhancing performance. The contents of the libraries are constantly enlarged based on the varying requirements of designers. They may thus become the generic functions described earlier.
xl.86 x 1.96 x2.38
Table 31.8 Compilers
Logic compilers Schematic compilers Memory compilers Logic synthesis interface compilers Data path compiler
Multipliers, adders, shifters, counters and other logic functions Netlist to schematic conversion RAM with multiport options ROM with very wide words practicable, conversion of state machine tables, Boolean equations, truth tables, fuse maps and PL As to optimised logic equivalents Data path architecture design and conversion to megafunctions and megacells
31.5.7 On-chip storage requirements Table 31.6 Logic building blocks
Macro cells Low-complexity building block Examples : NAND, NOR, FLIP-FLOP Fixed transistor interconnection Fully characterised
Mega cells High-complexity building block Examples : RAM, ROM, ALUs, UARTs Fixed and optimised interconnection Fully characterised
Macro functions Medium-complexity building block Examples : COUNTERS, ADDERS Combinations of macrocells Performance layout dependent
Mega functions High-complexity building block Examples : RAM, ROM, ALUs, UARTs Combinations of macrocells Performance layout dependent
Table 31.7 Gate counts for some standard functions
Function
Description
Gate count
2901 2910 8254 8259A
4-bit slice ALU 12-bit microprogram controller Programmable interval timer Programmable interrupt controller 32-bit carry select adder 16 x 4 content addressable memory 16 x 16 two's complement multiplier
1006 1182 3046 1246 643 636 2099
RAM and ROM can be implemented on ASICs and provide fast local memory. Dedicated blocks of memory (megacells) are very dense and fast. Select product type based on the amount of RAM or ROM required. Table 31.9 shows examples of memory limits on ASIC products, and Table 31.10 gives some performance examples. Small amounts of RAM and ROM can be converted to gates using latches and combinatorial logic alone. Sections of ROM can be converted to optimised combinatorial logic using logic synthesis (LLS is one of LSI Logic's compiler tools). Such converted areas can be included on any ASIC product. 31.5.8 Replicated logic blocks Designs that have a significant amount of random logic that is formed from repeated sections can benefit from the creation of a metal megacell. The repeated section is treated as a single element and typically has a greater logic density. Since the metal megacells are generated as tiles, the allowance for block interconnect is minimal. The identical layout of each section results in a repeatable performance which can be of significant performance advantage. Table 31.11 compares the relative logic density for all the various styles of implemented logic on Channel-Free arrays. 31.5.9 Signal pins, partitioning and interfacing The periphery of every die contains the buffers and associated bonding pads used in packaging. The number of pads a device will need is determined by the sum of input, output and bidirectional signals used in the design and the power and ground requirements of the device. Refer to the device data sheets for specific details but, in general, all inputs and standard drive outputs and bidirects use only one pad.
Selecting the ASIC 31/9 Table 31.9 Suggested limits of memory on ASIC products Product Micro array Compacted array Compacted array plus Cell-based
LMA9000 LC A10000 LCAIOOK LCB15
Maximum bits of RAM
Maximum bits of ROM
Comments
4K 8K 32K 72K
16K 64K 128K 512K
Metal megacell Metal megacell Metal megacell Megacell
Table 31.10 Examples of memory performance for LMA9000
Table 31.12 Pads available on LMA9000 series
Memory block
Configuration
Typical performance (ns)
Device number
Estimated user gates
Available gate complexity
V¿¿
RAM RAM ROM
256x8 64 x 8 256x8
10.0 9.2 12.0
LMA9020 LMA9033 LMA9050 LMA9072 LMA9095 LMA9141 LMA9190 LMA9239 LMA9284 LMA9350
700 1200 1750 2 500 3 300 5000 6700 8400 10000 12 500
1968 3286 4992 7238 9 504 14124 19000 23 908 28 388 34944
1 1 1 2 2 2 2 4 4 4
Table 31.11 Relative logic densities for Channel-Free arrays
Percentage ROM Single-port RAM Multiport RAM Metal megacell Registered logic Typical utilisation Random logic
90 75 70 50 45 40 35
Device pads Vss
I/O
3
70 54 66 80 92 110 130 144 158 174
3 3 4 4 6 6 6 6 8
pad limited designs. When several designs are required for one system, repartitioning the circuit can radically alter pin count/gate ratios, potentially eliminating pad-limited designs. 31.5.10 Packaging requirements
A simple calculation then defines the minimum number of Vss and V¿¿ pads required to adequately support the device for all conditions. When possible, add additional pads. These reduce noise induced by the current power demands of switching outputs since a small resistance exists in the power supply metal. The switching current for a CMOS output buffer may be ten times the maximum static current. It is the dynamic current consumption that must be allowed for. These induced voltages also have the effect of reducing noise immunity on all inputs that share the same power rails. For this reason more advanced products (e.g. Compacted Arrays from LSI Logic) split the power supply rails (three Vss and two Vdd power supply rails). The total number of pads defines the minimum chip size required. Table 31.12 shows the pads available for the LMA9000 series. It may be necessary to configure additional I/O pads for Kdd/Kjs» depending on the number and drive of the output buffers. When the number of usable gates is less than that required (pad-limited design), a larger device must be selected. Partitioning the circuit in several different ways can provide an improved solution for multi-chip designs. The output buffer slew rate can be altered on some vendor's products by appropriate selection of output buffer type (none, moderate or full). This very beneficial feature slows the rate of rise and fall of the chosen output without affecting the steadystate drive capability. This reduces the power requirements (there is a reduction in peak dynamic current) and system noise (less radiated signal noise). Use slew rate control wherever practical. High drive output buffers will use more pads and require more power supply pads. Reassess the device interface needs, to avoid
The package must be able to accept the chosen device. Cavity size available for packages limits the size of device that may be used. The package selected must have sufficient pins for I/O and power supply. Pin grid arrays offer highest pin counts. The package must meet the requirements of the manufacturing process. Pin grid arrays are 'through board', while most chip carriers are surface mounted. The package must suit its operating environment. Ceramic packages are the most robust and can dissipate the most heat, while cavity down packages enable heatsinks to be mounted on them. Unique requirements can also be accommodated. Figure 31.10 gives the presently available range of packages. Packaging technology is currently evolving very rapidly and new developments offer many possibilities not currently easily available. The use of multichip assemblies, new substrate materials and electrical connection techniques all offer exciting possibilities for the near future. 31.5.11 Summary The various factors influencing the choice of ASIC have been addressed above more or less in isolation. In practice, many are interrelated and thus several iterations may be required to obtain the perfect choice. However, unless the design is stretching the limits of technology, it is more important to consider the design from the point of view of how to ensure that the ASIC is a success. This is particularly true for the first ASIC design which will inevitably be accompanied by justified concern at the potential risk in terms of cost and wasted time and effort. From the company point of view a failure at this point may adversely affect
31/10
Application-specific integrated circuits
Figure 31.10
Current range of packages
decisions on taking advantage of the ASIC technology available for several years. It is clear that ASICs are very attractive in terms of their cost, size,, power consumption, reliability and the degree of design security offered over alternative solutions. It is not clear what to do in order to produce one. The various horror stories that circulate coupled with over a hundred potential vendors make choices difficult. The potential investment in software and workstations and the concern over repercussions if the design has an error worsen the situation. It is therefore necessary to use the first ASIC as a learning vehicle. In many respects this is a similar situation to the introduction of microprocessors. Engineers must have hands-on experience to remove confusion and learn new skills. Training in jnanagement, manufacturing and procurement is also required. The approach to use is to choose a major ASIC supplier that you can be certain is doing a large number of designs a year. Check the company's ASIC success record and future stability by asking for ten references and checking the financial situation. Go directly to the ASIC vendor rather than through a third party to keep communications as direct as possible, to learn from their experience. Choose the most reliable supplier to keep the chances of success as high as possible. The small cost penalty would be small compared to the cost of failure. The time for high-risk ventures is after the first success. Select an HCMOS technology. This is the most used, is easily available and yet offers high performance. Also use a mediumsized array for the first design to minimise cost and risk. With a design of 2000-5000 gates the design is simple enough to complete in three to six weeks and yet complex enough to be a valuable learning vehicle. Preferably choose an existing design that has not been implemented with ASICs. Any delays in obtaining the ASIC can be buffered by maintaining existing production. The package selection should be done in consultation with manufacturing to avoid an unusable device being produced. Purchasing should be involved to check the financial viability of the project and the ASIC vendor. The ASIC vendor's software will be optimised for the product, putting the responsibility for producing parts to specification on the vendor. Use of 'universal' or 'free' libraries again significantly
increases risk of failure. Also, ASIC vendors provide training, usually as a one week class. These provide excellent grounding in ASIC design, testing and the use of the software tools. Go prepared with the questions that must be answered and gain years of experience in just a few days. It is generally possible to do ASIC designs at the vendor's design centre. Expert advice can be immediately sought and concentration on the design is improved, reducing potential delays. Do not be content with simply completing the logic designs. Check the device performance as exhaustively as possible and most importantly derive production tests before committing the design to silicon. Designing good tests retrospectively is fraught with problems and may prove to be impossible. The ASIC vendor should also do the layout. It avoids having to spend time (extra delay) in learning all the layout process and the layout will probably be done quicker as well. The potential for performance 'tweaking' by having 'hands on' is usually unnecessary, given today's technology, and is risky. Checking the design's performance after layout is essential, however, and here software tools can save significant effort. Package pinout. should also be checked. Possibly a full design review is an advantage to catch any last problems. Insisting that all prototypes are fully tested to the production specification by the vendor minimises the risk of delays caused by trying to debug vendor problems. With a test bed prepared and made ready by the designer, the first prototypes can be fully exercised over temperature and voltage. If all of these steps have been followed the probability is that the ASIC will be a complete success.
Further reading ANDREWS, W., 'Designers content with an explosion in ASICs', Comp. Design, 15 April (1988) BUTZERIN, T. et ai, 'ASIC testing with high fault-coverage', VLSI Syst. Design, 9, No. 9, September (1988) CORLETT, R., 'Moving towards analog semicustom ICs', Electron. Syst. Design Mag., 18, No. 10, October (1988) HARA, D. et ai, 'Timing analysis improves efficiency of ASIC design', EDN, 26 May (1988) INGLIS, M., 'ASICs—service versus technology', Electron. Eng., February (1988) KING, H., 'A statistical approach to route estimating', Electron. Product Design, May (1988) LEUNG, S. J. et ai, 'A conceptual framework for ASIC design', IEEE Proc, 76, No. 7, July (1988) MASTERS, N., 'The basics of ASICs', Electron. Design Automation, mid-April/mid-May (1988) MEYER, E., 'Structured arrays re-enter semicustom arena', Comp. Design, 1 January (1989) MOORE, B., 'Consider the tradeoffs when evaluating linearsemicustom ICs', EDN, 4 February (1988) OS ANN, B. et al, 'Compare ASIC capacities with gate array benchmarks', Electron. Design Int., November (1988) PRYCE, D., 'Semicustom I C s ratings and architectures aid analogand digital-circuit designers', EDN, 15 October (1987) PRYCE, D., 'Semicustom ICs combine analog and digital functions', EDN, 8 December (1988) RICE, V., 'Analog/digital chips mix problems with promise', Electron. Business, 1 February (1988) SINGER, P. H., 'Fast turnaround for ASIC photomasks', Semiconductor Int., February (1988) SMITH, T., 'ASICs set the pace in ATE progress', New Electron., April (1988) WHITE, A., 'The painless path to ASIC design', J. Semicustom ICs, 6, No. 1, September (1988)