Area and delay efficient GDI based accuracy configurable adder design

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Area And Delay Efficient GDI Based Accuracy Configurable Adder Design B. Sakthivel , A. Padma PII: DOI: Reference:

S0141-9331(19)30528-9 https://doi.org/10.1016/j.micpro.2019.102958 MICPRO 102958

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Microprocessors and Microsystems

Received date: Revised date: Accepted date:

21 October 2019 10 December 2019 14 December 2019

Please cite this article as: B. Sakthivel , A. Padma , Area And Delay Efficient GDI Based Accuracy Configurable Adder Design, Microprocessors and Microsystems (2019), doi: https://doi.org/10.1016/j.micpro.2019.102958

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Area And Delay Efficient GDI Based Accuracy Configurable Adder Design

Sakthivel.B 1, Padma .A 2 1 Assistant professor, Madurai Institute Of Engg And Technology,India 2 Professor , Sethu Institute Of Technology ,India E-mail: [email protected] Abstract Adders are one of the basic fundamental critical arithmetic circuits in a system and their performances affect the overall performance of the system. Traditional n-bit adders provide precise results, where as the lower bound of their critical path delay of n bit adder is Ὠ(log n). To achieve a minimum critical path delay lower than Ὠ(log n), many inaccurate adders have been proposed. These inaccurate adders decrease the overall critical path delay and improve the speed of computation by sacrificing the accuracy or predicting the computation results. In this work, a fast reconfigurable approximate ripple carry adder has been proposed using GDI(Gate Diffusion Logic) passing cell. Here, GDI cell acts as a reconfigurable cell to be either connected with the previous carry value or approximated value in an adder chain . This adder has greater advantage and it can be configured as an accurate or inaccurate adder by selecting working mode in GDI cell. The implementation results show that, in the approximate working mode, the proposed 64 -bit adder provides up to 23% ,34% and 95 % reductions in area, power and delay ,respectively compared to those of the existing adder.

1 Introduction The speed improvement and power dissipation reduction are the key objectives in the design of digital signal processing units, particularly portable systems. Generally, speed improvement can be achieved at the increased cost of more power consumption in the exact processing units. One of the ways to improve the speed and power is to sacrifice the computation accuracy .This strategy, which is approximating computing has been used for error tolerant applications [1] . Adder units, which are principle component in arithmetic unit of DSP systems, are power starving and often form hot-spots on the die[2].These facts have been the inspirations for realizing this block using approximate computing methods. Normally,conventional full adder uses cascaded full adders of length equal to that of number of input bits and hence , a critical carry propagation delay has been formed by carry chain .To the best of the researchers knowledge, all the approximate adders rely

on the concept of overall carry propagation delay and it is less than complete length of the adder. This has motivated the researchers to split the cascaded full adders into sub adders or smaller disjoints for reducing carry chain delay [3]. In each smaller disjoints the resultant bits are calculated separately and contributed to the final sum calculation and the previous prediction bits are used to calculate output carry. In this paper, reconfigurable ripple carry adder has been focused as well as the use of GDI passing cell has been suggested for switching between the inexact and exact working modes for both exact and inexact applications. The construction of the adder, which is based on the conventional RCA adder, does not require any

correction unit

externally for the exact addition operation. The proposed design during exact mode delay and power is same as the conventional working one and it is considerably smaller in inexact working mode. The rest of the paper has been structured as follows. In Section II, some related works are pointed and reviewed .The structure of the proposed GDI reconfigurable approximate adder is described in Section III. The results of the efficacy of the proposed as well as their comparison with the conventional structures are discussed in Section IV. Finally, the conclusion is depicted in Section V

2 Related works Earlier researches on inexact adders have concentrated on two general strategies such as error weight and error probability reductions (see [4]– [11]).The first design strategy has used hybrid structure by combining two different parts, correct MSBs(Most Significant Bit) and approximated Least Significant Bits(LSB) [6-11]. The accurate values of MSB have been propagated to next stage and LSB has been formed by summation. It restricts error weight to the weight of the carry input of accurate MSB part and 70% of power reductions can be achieved [6]. In the second methodology, pure inexact adder structures are utilized. For these adders, reductions of power consumption, error probability and delay have been considered as key design parameters [10][13]]. It may also need an error compensation unit which also has area ,power and time overhead

.To address these issues some image and video processing applications are required to run time accuracy adjustments and hence, runtime accuracy altering designs have been developed Few Accuracy Configurable Adders(ACA) other than voltage over scaling have been proposed using approximation schemes .At earlier [14],approximate adder has been designed with error detection and correction unit. That adder can be configured to varying

accuracy levels or accurate levels based on the application. But,the error

detection and the correction circuit have further increased area overhead .In ACA and GeAr (Generic accuracy configurable adder )[15] designs, error compensation starts from Least Significant Bits (LSBs) that leads to accuracy improvement.Where as computation time takes more cycles because of the connections of error correction circuits with the pipelined fashion. An alternate method of ACA design is accuracy Degrading Adder(DA) and RAPCLA[16] (Carry Look ahead Adder).DA design consists of accurate ripple carry adder and additional carry prediction circuit .Thus , its area is quite large .In [16] accuracy can be varied by selecting the portions of carry look ahead portions. 3 Proposed work In digital logic circuit design,the performance of circuits can be optimized by the selection of logic styles .In the literature various logic styles available for implementing boolean functions based on computation of intermediate nodes and transistor counts like full adder design with the

classes of

CMOS(Complementary Metal Oxide

Semiconductor),PASS Transistor logic ,Dynamic circuit, transmission gate and GDI logics [17]-[23] have been presented. GDI logic has been proposed as an alternative to other logic styles and it offers less number of transistor count for implementing boolean function by reducing swing voltage at their outputs .The reduction in voltage swing has encouraged to design low power circuits

Fig 1 GDI cell

Fig 2 Carry Passing GDI Cell

N

P

0

In2 In1 In1’in2

In2 1 1

G

Out

In1 In1’+In2

In2 In1 In1+in2

In2 0

In1 In1In2

Output f1 f2

Table

1:

Different

logic

implementations by GDI

OR AND

In3 In2 In1 In1’In2+In1In3 MUX 0

1

In1 In1’

NOT

Fig 3 Proposed GDI passing cell RCA The structure of GDI cell is shown in Fig.1.The diffusion terminal acts as an external input in the GDI cell and it helps to implement various Boolean functions such as OR, AND, MUX, INVERTER, f1 and f2, as listed in Table 1. In the proposed work, N and P terminals of GDI cell act as a selection line for choosing approximate mode or normal mode operation and it is called as GDI Passing cell as shown in Fig 2. By setting NP terminal as 10 ,the GDI passing cell can be configured as wire to pass an input terminal G value to the output terminal. By setting NP as either 00 or 11 ,simply an output can be set as zero or one. Adder units are connected using GDI passing cell, as shown in Fig 3. 12 bit ripple carry adder has been connected with GDI passing cells for the selection of accurate or

inaccurate mode.It selects carry-in from either the previous stage adder units or from a fixed user defined carry inputs. For the accurate mode of operation NP input is set as 10 or 01 ,The entire GDI cell acts as a wire and passes previous carry values.Where as for inaccurate mode ,NP input is set as 00 for passing zero as carry value or 11 for passing one as a carry value. If all the GDI cells select the carry from the user defined inputs, the delay to execute such an N-bit addition will be much smaller than the original delay of Nbit conventional full adder,with some accuracy loss. Consequently, by setting the control signals of GDI cells,the normal N bit addition can be executed without any accuracy loss.

4 Result and Discussion All the adders have been coded in Verilog HDL for various bit size and also synthesized by Synopsys Design Compiler. By using this tool, the design parameters of the considered adders are extracted. The results of delay, area, and power are analyzed for both accurate and inaccurate modes. To quantify and analyze a errors in approximate designs, three metrics of Error rate (ER) , Normalized Error Distance (NED) and Mean Relative Error Distance (MRED) have been used [17]. Each simulation is performed with random input patterns and each output value is compared with a correct value to produce the accuracy of performance metrics. In the proposed design, GDI cell is inserted between every fourth full adder of carry chain .For an accurate mode, an NP terminal is set either 10 or 01.where as for an approximated mode, it is set as 11 or 00 by forcing constant one or zero carry values .From the Tables 2 & 3,it is clear that the proposed design involves significantly less area and less delay and consumes less power than the existing designs in both accurate and in accurate modes with decreased error rate .It is also found that in approximate mode, the proposed design offers an average saving of 21 % area and 32% power and 91% delay than the existing one and achieves very less error rate than others on average, for different bit-widths. Table 2 Error rate analysis

s.no

Structure

Error rate

MRED

NED

1

GeAr [15]

0.42

0.015

0.04

2

RAP-CLA [16]

0.25

0.002

0.003

3

Proposed

0.18

0.001

0.003

Table 3 Design parameters obtained for adder structures under different bit sizes Structure

Mode

Bit

Area

POWER

DELAY

8

344.95

162.12uw

0.79

16

689.76

337.72uw

1.61

32

1379.39

682.91uw

3.22

64

2758.73

1370uw

6.48

8

328.46

17.52uw

0.57

16

656.79

348.23uw

1.08

32

1296.05

695.33uw

2.10

64

2630.37

1410uw

4.16

8

401.97

196.85uw

0.58

16

803.79

399.69uw

0.58

32

1553.31

785.25uw

0.59

64

3184.38

1600uw

0.61

8

344.94

162.12uw

0.79

16

689.76

337.72uw

1.61

32

1379.39

682.91uw

3.22

64

2737.67

1360uw

6.11

8

302.62

130.50uw

0.34

16

562.76

241.94uw

0.34

32

1088.59

460.86uw

0.35

64

2123.73

892.13uw

0.34

size RCA

RAP-CLA

------

APPROX=0

APPROX=1

PROPOSED

APPROX=0

APPROX=1

5 Conclusion In this work, a reconfigurable approximate ripple carry adder has been suggested for high speed application. The adder has greater advantage of swapping between the inexact and exact working modes by making it suitable for both error-tolerant and exact applications. The structure is similar to conventional adder with some modification by adding GDI cell. To evaluate the effectiveness of the proposed structure, its design parameters have been compared to those of some conventional and reconfigurable approximate adders. The parameters ,which include area, delay and power are evaluated by using synopsis complier. The results have shown up to 23 %, 34% and 95 % reduction in area,power consumption and delay, respectively Conflict of interest: None 6 References [1] T. Moreau, A. Sampson, and L. Ceze, ‘Approximate computing: Making mobile systems more efficient’ IEEE Pervasive Comput., vol. 14, no. 2, pp. 9–13, Apr. 2015. [2] S. Ghosh, D. Mohapatra, G. Karakonstantis, and K. Roy, ‘Voltage scalable highspeed robust hybrid arithmetic units using adaptive clocking,’IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 9, pp. 1301–1309, Sep. 2010. [3] A. K. Verma, P. Brisk, P. Ienne,’Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design’ Design, Automation and Test in Europe (DATE), 2008. [4] N. Zhu, W. L. Goh, W. Zhang, K. S. Yeo, and Z. H. Kong,’Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing,’ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 8, pp. 1225–1229, Aug. 2010. [5] H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas, ‘Bio-inspired imprecise computational

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Sakthivel received a B.E degree in Electronics and Communication Engg from the SACS MAVMMM ENGG college ,Madurai. He completed M.E in Anna University. He is currently Working as Associate Professor in the Department of ECE at Madurai Institute of Engg and Technology and pursuing Ph.D , where he heads the VLSI Lab. He a focus on VLSI architecture design, particularly as applied to data path circuits like adders and multipliers