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Nuclear Instruments and Methods in Physics Research A 570 (2007) 241–247 www.elsevier.com/locate/nima
Assembly, construction and testing of the ALICE silicon pixel detector V. Manzari Istituto Nazionale di Fisica Nucleare, Sez. di Bari, via E. Orabona, 4, 70126 Bari, Italy on behalf of the Silicon Pixel Detector Project Available online 2 October 2006
Abstract The Silicon Pixel Detector (SPD) is the innermost detector of the ALICE experimental apparatus. ALICE is the CERN LHC experiment dedicated to the study of ultra-relativistic heavy ion collisions, furthermore ALICE will contribute to the proton–proton physics programme. The SPD is based on hybrid SPDs assembled in 120 modules (half-staves). The half-staves are mounted on 10 low-mass carbon fibre sectors arranged in two barrel layers placed at 3.9 and 7.6 cm from the colliding beams. The total SPD silicon surface is 0.2 m2. The SPD assembly procedure and the current status of the construction are overviewed. r 2006 Elsevier B.V. All rights reserved. PACS: 25.75. q; 29.40.Gx; 29.40.Wk Keywords: Silicon pixel detector; Silicon tracker; ALICE; LHC
1. Introduction ALICE is a general purpose detector to study ultrarelativistic nucleus–nucleus collisions at LHC [1]. ALICE will explore a new regime of matter, increasing by a large factor both the volume and the energy density of the interacting fireball achieved at the CERN SPS and at RHIC. The ALICE experiment will also contribute to the p–p physics programme, where in particular for charm and beauty detection at very low transverse momentum ALICE is competitive with respect to other LHC experiments. As in most of the collider experiments, the ALICE subdetector closest to the interaction point is an array of silicon detectors named Inner Tracking System (ITS) [2]. The ITS consists of six cylindrical coaxial layers of silicon detectors: The configuration of the ITS has been optimized for track finding and impact parameter resolution. The two innermost layers (SPD) consist of Silicon Pixel Detectors (SPDs), the two intermediate layers (SDD) and the two outer layers (SSD) are made out of silicon drift detectors and of double-side silicon strip detectors, respectively. Tel.: +39 080 5443288; fax: +39 080 5442470.
E-mail address:
[email protected]. 0168-9002/$ - see front matter r 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2006.09.028
Fig. 1 shows a schematic view of the ALICE apparatus, the two layer SPD barrel with the main components. The SPD is based on a hybrid technology: the basic detector element, named ladder, is a matrix of reversed biased p+n junctions flip-chip bonded to five readout chips. Each individual cell of the sensor matrix is connected via an Sn–Pb solder bump to a readout cell on the frontend chip. This technique has been pioneered by WA97 [3] and successfully used in NA57 [4] and more recently NA60 [5], all experiments being part of the heavy ion fixed target physics programme at the CERN SPS.
2. The ALICE SPD The very high particle density expected in the nucleus– nucleus interactions at the LHC energy requires the use of a true two-dimensional detector close to the interaction point, combining very good space accuracy with high double track resolution. In particular, the SPD provides ALICE with a good secondary vertexing capability for charm and beauty decays as well as hyperon decays. The SPD will allow a track impact parameter resolution below
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Fig. 1. A schematic view of the ALICE experimental apparatus; on the right the two layer Silicon Pixel Detector (SPD) is shown with a detail of a carbon fibre sector and one detector module (half-stave).
Fig. 2. The half-stave layout.
50 mm and will improve the tracking of low-pT particles and the momentum resolution. The constraints on physics performance are very demanding in terms of material budget and geometrical dimensions. The SPD components have been developed during several years of R&D activity, tested and qualified both in the laboratory and in high-energy particle beams. The basic building block of the SPD is the half-stave, schematically shown in Fig. 2. The two SPD layers are made of 120 half-staves arranged in 10 sectors around the beam pipe. Each half-stave contains two detector modules (ladders), one low-mass Al–polyimide multi-layer flex (pixel bus), one Multi-Chip Module (MCM) and one grounding foil. The half-staves are mounted onto a carbon fibre support sector, with a 200 mm thick wall, embedding the cooling pipes which run underneath the half-staves. The total power dissipated by the SPD electronics is about 1.5 kW. The cooling system must maintain the SPD at an approximately constant temperature of 24 1C, as required by the high sensitivity of the adjacent SDD to temperature variations. For this purpose an evaporative C4F10-based cooling system has been developed [6]. The system has
proven to be very efficient and capable of assuring the required performance in all conditions. The total material budget of the SPD is 1% X0 for each SPD layer.
3. The half-stave components In this paragraph, a brief description of the half-stave components is presented (a recent general overview can be found in Ref. [7]) and the half-stave assembly procedure is described. The front-end pixel chip ALICE1LHCb is a mixed function chip produced in commercial six metal layer 0.25 mm CMOS process, made radiation tolerant by the design layout [8]. It contains 8192 cells, 50 (rf) 425 (z) mm2, arranged in 256 rows 32 columns. The 200 mm pixel chip wafers, each containing 84 die, are probed and the chips are classified into three classes, according to the type and number of defects. The die suitable for the flip-chip bonding (Class I) in particular show less than 1% pixel defects. The plot in Fig. 3 shows the number of Class I chips per wafer in the 45 wafers probed so far [9].
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Number of class 1 chips/wafer
80 70 60 50 40 30 20 10 0 Fig. 3. Number of Class 1 chips per wafer in the 45 probed wafers.
The SPD ladder is an assembly of a silicon sensor matrix of 256 (rf) 160 (z) cells bump-bonded to five readout ALICE1LHCb front-end chips. The bump deposition and bonding are carried out at VTT,1 which makes use of solder Pb–Sn bumps. The total ladder thickness is 350 mm: the native thickness of the sensor is 200 mm while the readout chips are 150 mm thick. The native thickness of the 200 mm readout wafers is 725 mm; the wafers are thinned down to 150 mm at VTT after bump deposition. The detector ladders are probed in order to identify those suitable for the half-stave assembly. Only ladders which satisfied the following criteria are accepted for the half-stave assembly: full electrical functionality of the five readout chips, including the response to an 90Sr source, number of defect pixels per chip less than 1% and total leakage current below 2 mA [9]. The production yield of ladders suitable for half-stave assembly is about 70%. Each half-stave is read out and controlled by auxiliary ASICs placed on the MCM located at the end of the module as shown in Fig. 2. A detailed description of the readout architecture and components is given in Ref. [10]. The MCM contains three custom ASICs and an 800 Mbit/s optical link for the data transfer between the detector and the control room. The ASICs, made in a 0.25 mm CMOS process, are mounted on the MCM without package in order to reduce the overall MCM size and thickness. The MCM handles configuration and trigger signals, initiates the data and provides the pixel chips with the required reference bias voltages. The optical package contains two optical receiver PIN diodes and one optical transmitter laser for the data transfer from and to the counting room at 40 and 800 MHz, respectively. The MCMs are tested and undergo burn-in before they are assembled in a half-stave. For this purpose a dedicated FPGA-based test card has been developed which emulates the 10 front-end pixel chips sitting in a half-stave. The connection between the control and readout electronics on the MCM and the individual front-end pixel 1
VTT Center for Microelectronics, Espoo, Finland, http://www.vtt.fi.
chips in one half-stave is based on a flexible five layer aluminium/kapton cable, referred to as pixel bus. The pixel bus provides data, control and power lines between the readout chips and the MCM. The use of aluminium as conducting material, in order to reduce the material budget, has required an intensive R&D activity for the pixel bus. The thickness of the Al layers varies between 5 and 30 mm. The two layers used for the data lines are connected with vias. Two copper extender buses carry power lines to the front-end chips and the auxiliary electronics housed in the MCM. The grounding foil is a thin Al/polyamide (25/50 mm thick, respectively) laminate. The Al layer is connected to the common ground of the half-stave, while the polyamide side is facing the carbon fibre support. The shape of the grounding foil allows a good thermal coupling between the back side of the front-end chips and the cooling ducts embedded in the carbon fibre support sector. 4. The half-stave assembly and wire-bonding The assembly of the half-staves and their mounting on the carbon fibre support sectors, described in the following section, are performed with automated motion controllers and glue dispensers on high-precision measuring tables. The assembly of the half-staves, as well as the wirebonding and the final functional test and characterization are performed in a dedicated clean room.2 The assembly procedure of the half-stave has been worked out and extensively tested with dummy components [7,11]. The micrometric alignment of the half-stave components is performed with a Mitutoyo coordinate measuring machine Crysta Apex 9166 equipped with tools and jigs developed and built-in house for the proper vacuum-based handling of the components, as shown in Fig. 4. 2 The half-stave production takes place in the clean room of the INFN laboratory in Bari, Italy.
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Fig. 4. Coordinate measuring machine equipped with tools and jigs for the half-stave assembly.
The selected glue is the bicomponent epoxy adhesive Eccobond 45 produced by Emerson & Cuming.3 It is electrically insulating with a suitable thermal conductivity. The Eccobond 45 can be cured at room temperature and the flexibility can be determined by the amount of the Catalyst 15 used. For the half-stave assembly we have adopted a 1–1 ratio of glue and catalyst. The first operation is the alignment of the two ladders and the MCM with respect to each other and their gluing onto the grounding foil. In the second gluing step the pixel bus, soldered to the copper extender which provides power to the front-end chips, is aligned and glued onto the two ladders and the MCM. The tight dimensional tolerances of the SPD require that the thickness and the planarity of the half-stave are kept under control very carefully during every production step. The required thickness of the glue layer is obtained by scraping the excess with respect to an adhesive mask making use of the coordinate measuring machine. Acceptable results in terms of strength of the assembly, minimum achievable thickness and reproducibility have been proven to correspond to a glue layer of E130 mm. In Fig. 5 a picture of a fully mounted half-stave is shown with its main components on the top. The third and final step of the half-stave construction is the ultrasonic wire-bonding connection of the pixel bus to the front-end chips and the MCM. There are more than 1100 bonds on each half-stave. The quality of the component alignment and gluing is crucial with respect to the reliability and robustness of the wire-bonds. The geometry of the half-stave and the layout of the wire-bonding connections require the maximum error in the relative position of ladders, MCM and pixel bus to be of the order of 50 mm, i.e., half the size of the bonding pads.
3
http://www.emersoncuming.com/.
On the about 40 half-staves assembled so far the precision on the positioning of the half-stave is found to be always better than 10 mm and the distribution shows 4 mm statistical error. In addition, to make the wire-bonding feasible, special care is taken in the glue dispensing which has to ensure a uniform distribution of the glue up to the edge of the pixel bus and to be well confined in order to avoid any contamination of the bonding pads due to overflowing of the glue. The wire-bonding technique adopted for the ALICE SPD consists of an ultrasonic aluminium wedge bonding with a 25 mm diameter wire [12]. A protocol has been developed to determine the proper range of the main parameters of the bonding process, namely the Bonding Force (BF), the UltraSonic bonding Time (USTime) and the UltraSonic Power (USPower), for each type of component. Also the loop of the bond wires has been studied and optimized with respect to the strength of the connection and the space occupancy. Fig. 6 shows a detail of the wire-bonding between the pixel bus, the MCM and the ladder closest to the MCM. Before a half-stave is mounted on the carbon fibre sector, its functionality is extensively tested including the response to a radioactive source. In fact, the complexity and compactness of the SPD makes the replacement of a malfunctioning half-stave very hard and risky in terms of probability to damage a neighbour half-stave. In Fig. 7 is shown the result of the half-stave test with the 90Sr source above chip 4: the shadow of the SMD components glued on the top layer of the pixel bus is also visible.
5. The sector mounting and testing The procedure developed for the sector mounting is described in Ref. [13] and summarized in the following. The mounting of the carbon fibre sector is performed in a dedicated clean room facility.4 The carbon fibre sector is equipped with the embedded PHYNOX cooling ducts, 1 mm diameter and 40 mm thick wall. A thin layer of thermal grease is dispensed onto the sector surface where the half-staves will be placed: it ensures a good thermal coupling between the half-stave and the cooling pipe. Two half-staves are aligned with respect to each other to form a stave which is then aligned and placed onto the sector. The aligned stave is finally glued to the carbon fibre sector using a UV curable glue: to ensure a good mechanical stability. The upper part of the stave is fixed by means of carbon fibre clips, which also act as a protection for the wire-bonding. Each sector carries on four staves for the outer layer and two for the inner layer, respectively, as shown in Fig. 8. 4 The sector production takes place in the clean room of the INFN laboratory in Legnaro, Italy.
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Fig. 5. Half-stave components and the assembled half-stave.
Fig. 6. A detail of the wire-bonding connection between the pixel bus, ladders and the MCM.
Five sectors are connected together to form a half-barrel, see Fig. 9; two half-barrels are mounted around the beam pipe to make the whole two layer SPD barrel. Fully assembled sectors are transported to the CERN Divisional Silicon Facility where a dedicated laboratory has been equipped for the integration and functional test of the SPD sectors. Here, sectors are tested with final power supply, cooling, data acquisition and detector control systems. Two SPD sectors have already been built and are under test. The first fully equipped sector is shown in Fig. 10. 6. Detector performance Several flip-chip bonded assemblies have been tested at the CERN SPS during three test beam runs in 2001, 2002 and 2003. In particular, the results of the analysis from 350 GeV/c proton/pion beam data on detectors with final thickness, i.e. 200 mm thick sensor and 150 mm thick front-
end chips, show that the detector performance is in very good agreement with respect to the design parameters [14]. The experimental set-up consisted of a single chip assembly under test (middle plane) placed in between two tracking stations. Each tracking station (minibus) consists of two single chip assemblies, placed one after the other along the beam. The trigger is set by the coincidence of the signals from an incoming beam particle traversing four scintillator counters. The hits on each plane are processed by a cluster finding algorithm, where a cluster is defined either as a single fired pixel or a group of fired pixels where each pixel shares at least one side with an adjacent fired pixel. Before the track reconstruction, the relative misalignments in the transverse position of the detector planes with respect to the beam line are taken into account. The least squares fit procedure is applied to reconstruct the tracks both in the xz and yz projections, z being the coordinate along the beam. The reconstructed tracks are then used to estimate the intrinsic spatial precision of the test assembly and its detection efficiency. To evaluate the intrinsic spatial precision of the detector under test from the widths of the measured residual distribution, i.e. the difference between predicted impact and nearest cluster positions, the tracking errors have been estimated by means of a simulation which takes into account the telescope geometry, the multiple scattering and the residual tracking plane misalignment. When only single-pixel clusters are selected, the intrinsic spatial precision of the pixel detector under test is 120.170.5 mm along the long side pixel cell, i.e. 425 mm, and 11.570.2 mm along the short side pixel cell, i.e. 50 mm. The measured spatial precision results to be slightly better in both coordinates with respect to the pitch/O12 value as expected for a digital device. It can be explained as follows: the track impact parameter distribution shows that single-pixel clusters are generated by tracks crossing a pixel cell in a region narrower than its size. Depending on the
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Fig. 7. Control panel of the half-stave test: the 10 hit map plots, one per chip, are also shown. The picture has been taken with the radioactive source placed above chip number 4.
Fig. 8. A schematic drawing of two sectors around the beam pipe: each sector carries four staves on the outer layer and two staves on the inner layer.
threshold setting, tracks impacting the cell close enough to the boundary regions will fire double-pixel cluster. The detector efficiency, defined as the ratio between the number of events where a cluster correlated to a reconstructed track is detected and the total number of events with a reconstructed track crossing the test plane, has been found to be in excess of 99% at a threshold of about 2000 electrons with a wide plateau up to E6000 electrons. In Fig. 11 is shown the detector efficiency as a function of the threshold at three impact angles of the track. In all three curves a wide plateau is present well
Fig. 9. One SPD half-barrel is made of five sectors connected together.
before the usual operating range of 200 DAC units corresponding to about 3000 electrons. The detector performance has been studied as a function of the threshold and the track impact angle. A detailed
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One key element in the production of such a complex device as the SPD is the testing and qualification of the components at each phase of the construction. The first two sectors have been fully assembled and are currently under test. The detector performance has been evaluated from data collected in several test beam runs at the CERN SPS with single assemblies. The results of the data analysis have shown an excellent performance of the ALICE SPDs: the measured spatial resolution inferred from the residual distribution is comparable to the intrinsic detector resolution with binary readout and the overall efficiency is above 99%.
References Fig. 10. First SPD sector fully equipped with 12 half-staves.
3000 e-
Decreasing threshold
Efficiency (%)
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Threshold (DAC units) Fig. 11. Detector efficiency as a function of the threshold at three impact angles of the track.
discussion of the results from the data analysis can be found in Ref. [15]. 7. Conclusions The SPD provides the ALICE experiment with a highgranularity detector for high-performance tracking and secondary vertexing capability. The construction procedure of the half-stave and their mounting on the carbon fibre support sector is ongoing.
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