Assessments of micropackaged integrated circuits in high reliability applications

0026-2692/83/1402-0005 $5.00/0

Assessments of micropackaged integrated circuits in high reliability applicatlons' by N. Sinnadurai and D. Roberts British Telecom Research Labs,lpswich, England *This paper was presented at the International Microelectronics Symposium 1982 organised by the International Society for Hybrid Microelectronics

An earlier study showed that plastic coatings could provide adequate protection of microcircuits for long life applications. This promise that low cost techniques could be used in high reliability telecomms applications encouraged further investigations of micropackaged integrated circuits. Transistor arrays and operational amplifiers typical of those required for hybrids in telecomms applications were used as the test vehicles. The micropackages included SO packages supplied as standard components and leadless ceramic and epoxy-glass chip carriers coated with the more promising plastics. These micropackaged ICs have been exposed to a range of damp heat stress in non-saturating autoclaves and thermal overstress in ovens for extended durations representing operation for more than 20 years in telecomms environments, and the failures and survivors were then analysed in detail. Very promising results have been obtained, showing that the majority of the micropackaged ICs had reliabilities that would survive 20 year lifetimes, and some - in particular Ti-Pt-Au metallised, silicon nitride passivated ICs in plasticcoated and lidded epoxy-glass chip carriers - would comfortably exceed this lifetime. The results are very encouraging indeed for the prospects of low-cost, plastic micropackaging for high reliability applications.

1. Introduction The inexorable growth in the use of hybrid microelectronics has led to the development of a variety of types of encapsulation for hybrids. The technologies developed for the higher reliability applications have tended to be those that were also more costly. However, despite their high cost, some hermetic assemblies for instance of bare-chip-and-wire (HeW) hybrids, were found actually to contribute to their unreliability.' On the other hand, there is increasing evidence that lower cost encapsulations such as plastic can provide adequate protection even for long-life applicationsr' and the desire to lower the costs of high reliability components (i.e. to make them 'cost-effective') has led to increased attention to the development and improvement! of plastic encapsulations for hybrids. In an earlier paper? we reported the systematic evaluation of a number of plastic coatings, both as single-layer junction coatings (i.e. those in direct contact with bare semiconductor dice) and also with added top coatings for mechanical protection. The evaluation showed that a number of junction coatings and a particular few combinations of junction and top coatings gave very promising reliability performances indeed. There was thus a potential for highMICROELECTRONICS JOURNAL Vol 14 No 2 © 1983 Benn Electronics Publications ltd. Luton

5

Assessments of micro packaged integrated circuits in high reliability applications continued from page 5

reliability, low-cost packaging that was realisable either by encapsulating BCW hybrids, or by coating individual integrated circuits (lCs) assembled in micropackages such as chip carriers (CCs). There are a number of convincing reasons for using micropackaged ICs in preference to BCW hybrids, probably the most compelling of which is the necessity to be able to fully characterise the ICs prior to their assembly into the hybrid. These arguments are dealt with quite effectively elsewhere.P They have given emphasis to the desirability of developing cost-effective micropackaging, which led to the extension of our studies to the more promising coatings applied to ICs assembled in low-cost CCs. Described in this paper is the evaluation of the more promising coatings applied to ICs assembled in low-cost plastic and ceramic based CCs, whose reliability performance during both damp heat and thermal overstress ageing tests has been compared with that obtained from commercially-available Small Outline (SO) micropackaged les. Some thousands of hours of test time have been accumulated from overstress of over 700 test vehicles, and the subsequent sections describe the choice of test vehicles and overstress and measurement conditions, report the observations made and failure analysis findings and finally deal with the interpretation of the observations from which conclusions are drawn. 2.

Experimental methods

2.1 Test vehicles Sensitive ICs of most immediate interest were operational amplifiers (op-amps). These were obtained both as bare dice and encapsulated in SO micropackages from a number of manufacturers. A useful comparison was therefore possible between the effectiveness of the coatings in protecting the dice and the reliability performance of the commercially moulded plastic micropackaged ICs. The concept of a new low-cost plastic-based CC 6 was inspired by the earlier findings? that plastic encapsulation could achieve high reliability, and its development had preceded the present work. The CC, illustrated in Fig. 1, is constructed of epoxy-glass-fibre material with metallisations for bonding and soldering pads of copper-nickel-gold added by print-and-etch and plated-through-hole techniques akin to printed-circuit-board (PCB) processing. Hence the CC has become known as the PCB CC. 6 The PCB CC has a 'windowframe' at its

Fig. 1 Low-cost plastic-based chip carrier..

periphery to provide a retaining wall for the coatings. Only prototype versions of the PCB CC were available at the outset of this study and both junction plus top coatings were employed to encapsulate the IC dice. Later developments of the PCB CC incorporated an improved metallisation for better bondability and utilised an epoxy-glass lid instead of the top coating for mechanical protection. For completeness, single-layer and three-layer ceramic-based leadless chip carriers (LCCs) without lids, and some hermetically sealed CCs were also employed in this study. 6

The test elements employed in the previous exercise? had been high-gain transistors and a moisture sensor, in order to be able to analyse, with some sensitivity, the influence of the coatings during the accelerated ageing tests. For continuity, a small number of transistor arrays, type 3096, containing both npn and pnp transistors were included in the present study. However, the predominant component in this exercise was the 741 family of op-amps, supplied in either single (741) or quad (348) form. A smaller number of748 op-amps (without an internal compensating capacitor) were also included in order to observe whether the integral compensating capacitor of the 741, with its large expanse of metallisation, affected its reliability in the plastic encapsulations. The transistor arrays were assembled in both PCB CCs and ceramic CCs and were protected with both a junction coating and a top coating. The op-arnp dice were similarly encapsulated and some versions were packaged in hermetic CCs. Op-amps were also obtained in transfer moulded epoxy SO micropackaged or dual-in-line package (DIP) form as available from four sources. Op-arnp dice from one source (b) were supplied in two variants: aluminium metallised with oxide passivation, and titanium-platinum-gold (Ti-Pt-Au) metallised with silicon nitride passivation. In order to facilitate measurement, and loading and electrical biasing in the environmental chambers, the micro-packages were assembled onto leaded

(a)

(b)

Fig.2

(a) SO packages or ceramic CC mounted onto ceramic substrate. (b) PIPs and PCB CCs mounted onto epoxy-glass substrate. 7

Assessments of micropackaged integrated circuits in high reliability applications continued from page 7

single-in-line (SIL) substrates. The 741 and 748 op-amps were mounted in pairs, while the quad op-arnps and transistor arrays were individually mounted on the substrates. All SO packages and ceramic CCs were mounted on ceramic substrates with platinum-gold or palladium-silver conductors, and the DIPs and PCB CCs were mounted onto epoxy-glass substrates with tinned copper conductors (Fig. 2). The SIL leads of the ceramic substrates were gold-plated to avoid problems of oxidation. The coatings initially used within the PCB and the ceramic CCs were the silicone 'K', identified in the earlier work as an effective junction coating, and the phenolic 'L' - to provide mechanical protection. The phenolic L was more conveniently applied as an overall coating over the SIL substrates containing the single layer ceramic CCs (Fig. 3). The later development of the improved PCB CC, which incorporated a lid and thereby obviated the second plastic coating, was the object of additional evaluations that are described later. Details of the components that were evaluated are listed later in Tables 3 and 4 which also give a breakdown of their allocation in the environmental tests.

Fig. 3

2.2

Phenolic L coating over the SIL substrates containing single layer ceramic CCs.

Methods for reliability evaluation

The evidence from reliability experiments conducted over many years has established the validity of accelerated ageing methods for determining the longevity of electronic components. While thermal overstress is employed to determine the reliability of hermetically packaged ICs, the accelerated ageing tests relevant to plastic encapsulated semiconductor 8

components include both thermal overstress' and damp heat stress.' The lifetimes required of telecomms components range up to 20 years, and the test conditions and durations necessary to prove longevity may be calculated from the acceleration factors established by previous experiment. The expression for acceleration by damp heat was given in a previous paper as: Acceleration Factor A

= exp [0.00044 (RH/ -

RH amb2) + 7000 (1{Tamb-1{fs)]

in which T, and RH s are the stress temperature and humidity respectively, and the suffix 'amb' refers to the ambient conditions. Apparatus for inflicting damp heat stress include both humidity chambers and non-saturating autoclaves," the latter having the attractions of good controlability and short test durations. The relationships between test durations in an autoclave operated at 108°e, 90% RH, and 20 year lifetimes in alternative telecomms environments are given in Table 1; hence survival for up to 100 hours in the autoclave is necessary to prove a 20 year reliability. Table I

Acceleration factors and test durations at !08°C, 90% RH, corresponding to some humid operating conditions for telecomm equipment. T

COC) UK Exchange UK Office UK Uncontrolled

30 20 12-

RH (%)

Acceleration Factor

Time (hr s)

25

3100 3700 1800

50 100

45 72

60

Acceleration by thermal overstress has been found to conform to the following expression: A = exp [10.44 x 1()3 (l{f.mb-l{fs)] from which acceleration factors and test durations may be calculated for 20 year lifetimes in warm dry telecomms environments and are given in Table II. Table II

Acceleration factors and test conditions to represent 20 years life in a dry environment at 70°C.

Test Temperature

Acceleration Factor

Test Duration (hours)

125 150 160

65 315 555

2700

("C)

600

320

Thus, test durations of up to a few weeks under overstress conditions can represent 20 year operation in the different telecomms environments of interest. The conditions inflicted on the components have of course to be carefully chosen to ensure that only the failure mechanisms relevant to normal operation are stimulated. Therefore temperatures and humidities are kept within Validation Limits? - beyond which abnormal effects could occur. The components should also be electrically biased either to achieve maximum dissipation or maximum electric fields, depending on the likely hazard during operation. For plastic encapsulations the more serious hazard is the non-dissipating condition in damp environments, when the full ambient humidity would be experienced at the IC surface; whereas dissipation would cause some drying out locally and could give rise to optimistic results. Electrical bias should also be maintained whilst cooling the components to the measurement temperature in order to 'freeze in' any degradation that has occurred due to volatile causes such as mobile ions. These 9

Assessments of micropackaged integrated circuits in high reliability applications continued from page 9

considerations duly influenced the test conditions chosen for the present evaluation of micropackaged ICs. 3. Test conditions The accelerated ageing stress conditions and the measurements made were chosen to ensure relevance of the evaluation to the conditions obtained in service, in accordance with the foregoing requirements. __________- - - - - - _ - - - _ +10V

NPN 33k +6V -6V 33k

--+-

_ _-+-

-10V

Fig. 4 The bias applied to the transistors in the life tests.

J I I

I

1 I I I

~

~'P

1::1 I

lk

10k -14V

I I

Fig.5 The bias and signal applied to the operational amplifiers in the life tests.

3.1 Overstress Following the evidence of the effectiveness of the non-saturating autoclave in the previous exercise.s the same apparatus was employed to inflict a damp heat overstress of 108°C, 90% RH on the test vehicles in the present evaluation too. In addition, because of the interest in the operation of micropackaged components in warm dry environments, test vehicles were also exposed to thermal overstress at ISO°C. Because the epoxy-glass material has a glasstransition-temperature of 130°C, the PCB CCs and the epoxy-glass substrates were only subjected to the damp heat stress, which is considered to be more severe stress for plastic encapsulations anyway; and only the SO micropackages and ceramic-based CCs on ceramic 10

substrates were subjected to the 150"Cstress. According to the acceleration factor above, test durations of up to 100 hours at !08°C, 90% RH and less than 1000 hours at 1500C would represent 20 years operation in the telecomms environments. The actual test duration at each overstress condition was longer, so that more than just adequate information was gained. In both environments the test vehicles were biased while under stress by employing the circuits shown in Figs 4 and 5 for the transistors and op-amps respectively. They were intended to create electric fields at the die surfaces without significantly altering the applied temperature or humidity locally. Thus all diode junctions in the transistor arrays were reverse biased, and the operational amplifiers were connected as unity-gain buffers with no load and with sinewave excitation. To safeguard against mains failure and consequent loss of volatile changes, DC power was supplied from continuously charged lead-acid cells. A later variant in the planned programme of tests became necessary with the improvements in the PCB CC. However, because of the commitment of the autoclave apparatus, the additional test was conducted at 85°C, 85% RH, for durations equivalent to the 108°C, 90% RH, and the results were rescaled accordingly. The allocation of test vehicles to the overstress tests is listed in Tables III and IV.

Table III Batch Code

Size

A

40 40

D P F

J N

T U W

X M

Z

40 40 40

40 40 20 20 20 20 20 20 20 20 15

Devices in Autoclave (108°C 90% RH)

Package Type S08 S08 508 S08 S08 SLCC SLCC SLCC SLCC 3LCC PCBCC(P) 3LCC PCBCC(P) DIP DIP PCBCC(D)

IC Type 741 748 741 748 741 741 741 741 748 348 348 3096 3096 741 748 348

Man. Code B B B B E B B L L V V y y L L V

Metall + Passiv,

AI + oxide AI + Oxide Ti-Pt-Au + SbN4 Ti-Pt-Au + SbN4 AI+ Oxide AI+Oxide Ti-Pt-Au + SbN4 AI+ Oxide AI+Oxide AI+ Oxide Al+ Oxide AI+ none AI+ none AI+Oxide Al+Oxide AI+ Oxide

Notes to Tables III and IV: = Single layer chip carrier SLCC = 3 layer chip carrier 3LCC = Hermetic 3 layer chip carrier HCC = Dual in line (plastic) DIP PCBCC(P) = PCB chip carrier (early type) PCBCC(D) = PCB chip carrier (later type) Batch Z was stressed at 85/85 not 108/90

3.2 Measurements The test vehicles were measured at approximately logarithmically increasing intervals during the overstress tests and, for that purpose, were removed from the test and allowed to cool with bias still applied. Measurements were made using an HP85 computer-controlled datalogger with associated peripheral accessories connected via the IEEE 488 bus. Readings were 11

Assessments of micropackaged integrated circuits in high reliability applications continued from page 11

Table IV

Devices in Oven (I50°C)

Code

Size

Package Type

IC Type

Man. Code

C

20 20 20 20 40 40 40 20 20

S08 S08 S08 S08 S08 SLCC SLCC HCC HCC

741 748 741 748 741 741 741 348 348

B B B B E B B V V

Batch

G

Q H K R S

Metal1+ Passiv. AI + Oxide Al + Oxide Ti-Pt-Au + SbN4 Ti-Pt-Au + SbN4 AI+Oxide AI+ Oxide Ti-Pt-Au + SbN4 AI+ Oxide AI+ Oxide

taken at least three times to ensure repeatability. Means and standard deviations ofthe batch changes were then calculated and the processed data stored for later analysis. Failureschanges beyond specified limits- were automatically flagged during the measurements. Each faulty SIL substrate was then removed from the measurement jig, its leads were cleaned, and then measurements repeated to check their validity. The measurements of the op-amps included the input offset voltage (Vos), DC open-loop gain (Av), cut-off frequency (fr) and supply current (Icc). Vos and Avwere measured using a second amplifier in a standard circuit configuration (Fig. 6 [lO]) and fT was calculated from the AC gain measured at 100 Hz and 10kHz. Later batches were measured directly on a Gen Rad automated op-amp tester. The transistor parameters of interest were the collector-base and emitter-base forward voltages at 1mA, and the DC gains at collector currents of lOJLA, 100JLA and 1mA. The gains were calculated from the ratios of the base and emitter currents in an emitter-follower mode. lOOk Rl +5V

L..o

-5V..L

47R R2

vol 1.

Fig. 6 Circuit diagram of jig used to measure open loop gain of op-arnps.

3.3

Failure criteria

The parameters that were measured and their associated failure criteria are listed in Table V. The failure criteria were set at two levels; namely, 'parametric' which defined the value 12

beyond which the components although still functioning would be deemed to have failed, and 'catastrophic' indicating severe and probably destructively permanent degradation of the components. 4. Observations It is apparent from Tables III and IV that a considerable number of components were subjected to overstress, and the measurements made would be a prohibitively large number to report in detail in this paper. The observed trends are therefore summarised and only illustrative examples given below. As stated earlier, precautions were taken during the measurements to safeguard accuracy and ensure that the recorded failures were genuine. In addition, it is normal practice to analyse the failed components in order to confirm the failures, determine whether they are abnormal in any way, and attempt to understand the failure mechanims. Because more than one test element was mounted on each substrate, and. because the present exercise was intended primarily as a straightforward comparison of the potential reliabilities of the different micropackaging options, substrates containing failed components were not usually removed from the stress environments until the tests were concluded. The failure analyses therefore revealed the ultimate condition ofthe components.

Table V Device

Parameter

Failure Criteria for Devices Failure

NPN trans. in array

lebo lebo Vf(eb) Vf(cb) hFE

> > > >

100JLA lOOJLA lOV lOV

PNP trans. in array

lebo Icbo Vf(eb) Vf(cb) hFE

> > > >

lOOJLA lOOJLA lOV 10V

OP-AMP

Vos Avol

>lOmV 0 0 >lOmA

fr

Icc

Catastrophic Parametric LO

(for

HI

::!:

> lOOnA > lOOnA >O.82V >O.82V change

<0.5V ::!:

> lOOnA > lOOnA >O.77V >O.77V change

< 104 < 105Hz
>6mV > 106 > 107Hz >2.8mA >5.0mA

4.1 Overstress test results A useful way of summarising the behaviour of the different component types during the damp heat and thermal overstress tests is to plot the failures cumulatively with time. As in the previous paper, the differences are compared by plotting linear percentage failures versus the logarithm of stress time. The cumulative percentage failures of the 741 and 348 op-amps, the 748 op-amps and the 3096 transistor arrays that occurred during the damp heat overstress are plotted in Figs7a, 7b and 7c respectively. The test had been conducted beyond the required 100 hours and was eventually terminated at 520 hours. It is apparent from the plots that the majority of the batches remained very well behaved up to 100 hours, after which some dramatic failures occurred in some of the batches while others survived very well indeed. The early failures from batch D were actually intermittent and could not be explained. The better survivors of the 741 op-amp batches were Z, P, F, J and T, of the 748 op-amps was batch D, and of the transistor arrays was batch W. Few failures actually occurred during thermal overstress, as shown in Fig. 8. Once again, the test duration was longer than necessary to prove 20 year life and actually lasted 2000 hours. Surprisingly, the greater number of failures were oflCs in the hermetic CCs, while the 13

Assessments of micropackaged integrated circuits in high reliability applications continued from page 13

M

100

F--===~-~--

, N I I

I I

, I

I

I

I

I I

T

o 102

10' Fig.7a

103

t (hours)

% cumulative failures 741 &348 types SO, LCC, DILpackagesin autoclave at lO8°C,90% RH.

M

100

_

,r'-

A

!

I

i, ,/,' /

E :3 U

/

I/

*

•

I

1/

,I

I

o

_.--~-

10'

102

t

Fig.7b

103

(hours)

% cumulative failures 748 types SO. LCC. OIL packages in autoclave at lO8°C.90% RH. X(pnp)

100

,/X(npn)

/

,/ / ./

o

/ W(pnp)

----_.=-~~==::::::19

100

W(npn)

520

t (hours) Fig.7c

14

% cumulative failure of transistor arrays at lOsoC/9O RH autoclave.

plastic encapsulations survived remarkably well, even up to 2000 hours; the one permanent failure that occurred having been an infant mortality at 16 hours. Intercepts from the above plots, at 100 hours for the damp heat stress and 1000 hours for thermal stress, and also at the end of each stress test, are plotted as bar charts in Figs9 and 10. They provide simple comparisons of the percentage failures from the different batches at lifetimes equivalent to 20 years and beyond. 100

E

a /'

R .... 5

o 16

200 t (hours)

2027

Fig.8 Percentage cumulative failures of devices in oven tests at 150°C. failures at 100 hours failures at 520 hours 100

e80 :::>

J§ 60

'"

.~

~:::> 40 E

:::> u

* 20 o

Fig.9

~ .I nl

n •

.

ABFJMNPTUZ

ABMN

741 and 348 devices

748 devices

n

I

Bar chart of % cumulative failures of op·amps in autoclave at IOSoe. 90% RH.

The actual parametric behaviour is quite usefully illustrated by plotting frequency distributions of the parametric changes obtained at specific times during the overstress tests. Of particular interest are the times corresponding to the intercepts in Figs 9 and 10. Illustrative examples of the distributions of changes in Vos and Av of the op-amps are therefore plotted in Figs 11 to 14 for batches in which the catastrophic failures did not exceed 50% at that time. The majority of the distributions are seen to peak near zero change, about which they appear to be centred. Some distributions are more squat (e.g. batch Z) and others more spread (e.g, batch U); nevertheless the distributions do not stray close to the limits for parametric failure, and encouraged the expectation that Ie failure in micropackages had not arisen from serious parametric degradation. 15

Assessments of micropackaged integrated circuits in high reliability applications continued from page 15

4.2

Failure analysis

Typical samples of the failed components were subjected to detailed electrical and destructive physical analyses to locate and attempt to identify the causes of failure. An elementary preliminary step was to ensure that no external artefact, such as degradation of the supporting SIL substrate, had caused apparent failure of the dice. Probing and measurement using a curve tracer revealed some shorting between adjacent leads of some ceramic substrates supporting the ceramic CCs containing the transistor arrays. Visual examination confirmed that metal from the solder and the palladium-silver conductors had migrated over the ceramic between the leads and also through the overglaze between some tracks, but not between the solder pads of the micropackages. The shorts were removed by mechanical abrasion in order to identify the genuine failures.

100

failures at 1000 hours failures at 2027 hours

~ 80 ::l

~ 60

'"

.2:

~

~

E 40 ::l

U

~ 20

o-.-J

no

~

g.

PO

C G

CGHKQRS

748 types

741 and 348 types

Fig. IO Bar chart of % cumulative failures of op-amps in oven at 150°C.

l00hrs A (38)

0(39)

F (38)

J 1311

T (78)

p 1391

U (79)

Z (59)

100 75 50 25 0

.! . ·4.. .1 0

scale

0

0

-80........0.....•..·80

I 1. 0

0

J 1311

P 1391

...•..-.l 0

..

'~""I'I"

•.._Wl..,_•....

0

0

520hrs F (381

T (781

Z 1591

100 75 50 25 0

~. 0

Fig. II

16

j 0

1 .•..."t· 0

0

...........

"(~

...

0

Spread of change in A, of devices in autoclave expressed as percentage of batch at intervals of 100and 520 hours.

After verifying that the failures on each SIL substrate were genuine, the next step was to assess whether the failures were permanent or volatile, by exposing the components to heat without electrical bias (remembering that bias had been maintain ed whilst cooling to the measurement temperature in order to freeze-in any deg radation due to volatile causes). Components were measured beforehand, then stored in an oven at 100°C for 263 hours and then measured again. Of some 647components so stored, only 6 recovered. A small number also recovered in the interval bet ween overstress and re-measurement. This number was not regarded as significant and the inference was that the compon ent degradation was predominantly non-volatile. 100 hrs

P 139)

F 1381 J (3 1)

0 1391

A 1361

T 17BI

U 179 1

''''''l'L ,

~,

Z 1, 9 )

100 7,

I

50 25

0

.. ~

j 1I

..

0

0

0

0

F 1381

J (31)

0

.

.

0

0

0

- 6........0.......•• 6

scale

520hrs

o

139 ) 1262 hr.)

100

7,

,0 2,

~ ....

0

0

~

0

I 0

P 1391

.~

. .."I"'.' .,

Z 1,91

U 1791

T 17BI

·1a.1...... ••

.1

0

0

0

Fig. 12 Spread o f change in Yo. (m Y) of devices in a utoclave expre ssed as percentage of batch at inter vals of 100 a nd 520 hours. l 000 hrs C (39)

G 1381

H 1381

K 133!

Q

(38)

R 1741

s

(79 1

100

7, 50 25

.. ~.

0

0 scale

-

ooal ..

+., . . 0

i

0

l 0

l..

... . . .1.

,.~

...

0

0

01381

R 1741

~ 0

.

-80........0..... ...·80 20 27 hrs C 139)

G 1381

~.

"4A·

H 1381

K 1331

100

75 50

25 0

0

Fig. 13

0

.~ . 0

1 l 0

0

.!.... 0

Spread of ch ange in A s' of devices in ove n e xpressed as percen tage of batch :11 inte rvals of IlXX] and 2027 hours.

17

Assessments of micropackaged integrated circuits in high reliability applications continued from page 17 iooo n« C 1391

G 1381

H 1381

K (361

o

"~

17~1

R

Q (391

100 7~

so 2~

.~

0

0

J

.+. o

o

-6..... ..0 ........·6

SC
C (391

G (331

~",

.~ ..

K 1361

17~1

R

Q 1391

100 7~

so 2~

0

0

Fig. I~

o

~o

J

",1o

o

.- + o

s

»

Spread of change in V", of devices in oven expressed as percentage of batch at intervals of lOon and 2027 hours.

The next stages of the analyses were progressively more destructive of the components, involving gas analyses of the contents of the hermetic CCs foIlowed by decapsulation of both hermetic and plastic packages and further physical and electric examination as necessary. Gas analysis was carried out by puncturing each package into a smaIl-volume, heated mass-spectrometer" specifically designed and calibrated to measure small quantities of water vapour and gases of low atomic mass. The results proved to be inconclusive because similar quantities of water vapour and other gases. and less than 0.2% hydrocarbons,were found in both failed and surviving components - as shown in Table VI which lists the contents of sample failures and survivors of batch R. Table VI

Gas Analyses of Hermetic Chip Carriers (Batch R) Failures

Device Code

%of total pressure

Estimated total pressure (rnbars at 20"C) Estimated H20 pressure (mbars at 20"C)

N2 02 A CO2 CO H2 He H2O

Survivors

Rl

R25

R37

R9

R29

97.3 <.2 <.1 .7 < .8 .4 <.3 .3

97.8 < .2 <.1 .4 <.4 .6 < .3 .3

96.6 <.2 <.1 .5 <.5 1.1 <.3 .8

97.3 < .3 <.1 .4 <.4 1.0 <.2 .4

96.4 <.2 <.1 .5 <.5 1.9 < .2 1.4 .

690

(MO

560

650

620

2

2

5

3

9

Decapsulation of the hermetic CCs and optical microscopic examination revealed considerable mechanical damage to the surface of the dice (a) Many of the aluminium bonding pads had been damaged, with aluminium displaced under the bonds (Fig. 15), which was indicative of excessive power during thermosonic bonding; 18

Fig. 15 Aluminium bonding pads damaged by excessive power during thermosonic bonding.

.

.

. •

.

Fig. 16 Aluminium metallisations scratched resulting in a potention open circuit condition.

(b) The aluminium metallisations of about half the dice were scratched, in some instances almost to the point of being open circuits (Fig. 16)which probably contributed to their unreliability. In view of this damage and because the failures had been non-volatile, no further examination of the hermetically packaged dice was considered necessary. As no significant failures of plastic encapsulated ICs had occurred during thermal overstress, failure analysis was only necessary of the plastic encapsulations that were subjected to damp 19

Assessments of micropackaged integrated circuits in high reliability applications continued from page 19

heat stress. The coated CCs were decapsulated using a combination of Panasolva-Decap" to soften the outer layer and a hot sulphuric acid spray technique to remove the junction coating. This acid technique was also used on the moulded S08 packages. The exposed dice were then closely examined by both optical and scanning electron microscopy. Whilst there were differences in detail between individual components, some general observations may be made (remembering that all components had been exposed to 520 hours at 108°C, 90% RH. Of the SO 8 and DIP packaged components, the aluminium metallisations of the oxide passivated dice were found to be severely corroded (Fig. 17) and the Ti-Pt-Au metallisation of the nitride passivated dice to be slightly less so. Significant voluminous growth of a gold compound had occurred through cracks in the nitride passivation and was seen to be deposited on the nitride surface (Fig. 18).

Fig. 17 Corrosion of aluminium electrode of capacitor of 741 Op-Amp.

Generally, the 741 dice showed more signs of degradation than the 748 dice, which may be attributed to the presence of the compensation capacitor which was distinctly corroded on a number of the 741 dice. Of the coated ICs in low-cost ceramic CCs, some of the aluminiummetallised oxide-passivated dice did show signs of corrosion, but the tri-metallised nitrided dice remained in excellent condition (Fig. 19). The oxide-passivated ICs in the PCB CCs showed only slight corrosion of the aluminium. Degradation of wire bonds had also been suspected because of the open circuits indicated by the measurements, particularly in the PCB CCs which had suffered from bondability problems in the prototype versions. Unfortunately the decapsulation procedure also demolished the PCB CC and thereby prevented examination of the bonds on the CC. Nevertheless, inferences may be drawn from the dramatically better performance of batch Z which employed the later development versions of the PCB CC with the improved metallisation. * Registered Trade Name of Panacol Ltd.

20

Fig. 18 Migration of gold metallisation.

The majority of the failures may therefore be attributed either to mechanical damage of the dice in the hermetic CCs, or to metallisation corrosion or migration on the dice in the plastic encapsulations generally, or weak bonds particularly in the prototype versions of the PCB CCs. The promising exception was the lack of corrosion or migration on the tri-metaIlised nitride-passivated dice protected by the plastic coatings. The various findings from the failure analyses are summarised in Table VII. 5. Interpretation of observations The exposure of the various micropackages to damp heat and thermal overstress for durations exceeding the equivalent of20 years operation in typical telecomms environments has given rise to a variety of behaviour patterns. The differences and occurrences of failure usually became significant only after the equivalent of20 years life had elapsed- as seen in Figs7 and 8. The findings, from the thermal overstress and the subsequent failure analysis, that the failures of the ICs in the hermetic CCs were probably due to mechanical damage rather than either packaged ambient gases or ionic effects, justifies the dismissal of these failures as being irrelevant to genuine degradation, instead being indicative of unfortunately poor quality control in bonding and visual inspection - not a favourable finding! A particularly interesting observation was the lack of significant failures of the plastic encapsulated ICs during the thermal overstress, which contrasts with the larger numbers of failures that occurred during damp heat stress. The observation emphasises the greater vulnerability of plastic encapsulations to damp heat stress, which is therefore an essential overstress to be applied in their evaluation. The few failures that did occur during the thermal overstress were found to be recoverable parametric changes and therefore differed from the predominantly permanent corrosion failures that occurred during damp heat stress. In fact the remarkable stability of the Ie parameters during both stress tests is very apparent in the plots of frequency distribution of parametric changes shown in Figs 11 to 14. The thermal overstress results do nevertheless show that the plastic encapsulated ICs - in SO micro21

Assessments of micropackaged integrated circuits in high reliability applications continued from page 21

packages and coated CCs - would survive more than 20 years operation at 70°C. In fact much the same general inference of survival for 20 years can be drawn from the damp heat tests, for the operation of plastic encapsulated micropackages in damp telecomms environments too. Survival beyond 20 years would however be very dependent both on the types of encapsulation and on the metallisation and passivation of the ICs according to their behaviour beyond 100 hours at 108°C, 90%, as plotted in Fig. 7. These results together with the findings from the failure analyses enable an order of merit to be produced for the preferred combinations of encapsulations and IC technologies necessary to achieve survival in damp environments as follows: 1. Ti-Pt-Au metallised, nitride passivated ICs from source B assembled in junction coated and lidded PCB CC(D). 2. Al metallised, oxide passivated ICs in moulded plastic S08 packages from source E. 3. Ti-Pt-Au metallised, nitride passivated ICs from source B assembled and junction coated on single layer ceramic cc. Table VII

Summary of Typical Failure Analysis Findings of Plastic Encapsulated Op-Amps by Optical and Scanning Electron Microscopy Time to Fail

Sev,

741 748

150 520

X X

741 741 748 748

150 ok 520 ok

741

520

X

741 748

150 150

X X

741 741

520 ok

X

J

741 741

ok rec

N

741 748

150 150

T

348

150

X

slight corr. in central areas

U

348

520

X

slight corr. otherwise good

Z

348

540 (equiv.)

X

Code S08s A D

P

Die

Extent ofCorr. Mod.

sn.

Growths

Comments

corr. ofVcc rail & liPs X X X X

X X X X

mig. of upper metal layers and growth on top of nitride

corr. of Vee rail and cap.

X

DIPs

M CCs F

4. 5. 6. 7. 22

overglaze cracked

corrosion of bond pads X

die appearance excellent X X

corrosion of capacitor

Al metallised, oxide passivated ICs from source B assembled and junction coated on single layer ceramic CC. Al rnetallised, oxide passivated ICs from source V assembled and junction coated on ceramicCC. Ti-Pt-Au metallised, nitride passivated ICs in moulded plastic S08 packages from source B. Al metallised, oxide passivated ICs in moulded plastic S08 packages from source B.

ICs from source B with variants of AI metallisation with oxide passivation and Ti-Pt-Au metallisation with nitride passivation were the main clements encapsulated in S08 packages and coated low-cost CCs and tested in both damp heat and thermal overstress. The trimetallised nitrided ICs did achieve much better reliability than the AI-metallised oxide passivated ICs with the exception of the inexplicable intermittent faults that appeared during the early measurements and judged by both damp heat testing and failure analysis, their performance in coated CCs was particularly impressive. The coatings were also effective in safeguarding the survival of the aluminium metallised ICs including those from source V, but not in preventing eventual corrosion of the aluminium. The reason for the effectiveness of the junction coating has been previously explained-v to be due to the strong chemical bonding between the silicone and the silicon passivation surface, which thus inhibits the formation of continuous films of water and thereby impedes the mobility of ions present at the semiconductor-plastic interface. The effectiveness of the

Fig. 19 Trimetallised nitrided disc in good condition.

protection can however be impaired by contamination and will eventually be degraded by persistent penetration of moisture which would reach even low levels of contamination present in the plastic, and by the action of ions activated by the electric potentials present at the surface of the dice, account for the observed corrosion. It is worth emphasising that 520 hours duration at 108°C, 90% RH is a very severe stress indeed, and consequently the eventual corrosion of the ICs is not surprising. Any intrinsic unreliability of the IC dice would be expected to dominate their reliability performance regardless of the effectiveness of the encapsulation. Such unreliability was clearly present in the ICs from source L whose performance was poor both in coated chip carriers and moulded DIPs (S08s not delivered!). The failure analysis not only showed that extensive corrosion of the die metallisations had occurred, but also revealed the severely cracked passivation which would have nullified the protection offered by the coating. The performance of the source B ICs in the early versions of PCBCCs protected by the coatings also did not come up to expectation, as seen in the cumulative failure plots for batches U and X in Figs 7a,c. The corresponding batches employing ceramic CCs were T and W, which showed markedly better performance. Although the suspected faulty bonds were not confirmed by the abortive failure analysis of this package, nevertheless a very positive 23

Assessments of micropackaged integrated circuits in high reliability applications continued from page 23

inference - that suspect bonding had been eliminated - may be drawn from the dramatically better results obtained from the later version of the PCBCC with the improved metallisation, as used in batch Z. In fact, despite the slight corrosion revealed by the failure analysis, the performance of batch Z was about the best in the damp heat stress test. This was an encouraging result indeed for the prospects of cost-effective micropackaging and, because of the confirmed lack of corrosion on the coated dice with tri-metallisation and nitride passivation, the optimum combinations would be an assembly comprising a tri-rnetallised IC bonded into the improved PCBCC protected with a junction coat and epoxy-glass lid. The performance of the trl-metallised nitrided ICs in the SO packages after 100 hours damp heat stress was poorer than that of the ICs in the coated chip carriers. This may be explained by the properties of epoxy mouldings that are somewhat different from those of the silicone coatings. For instance, while epoxy plastics are less permeable than silicones to water vapour, epoxies nevertheless do tend to contain more ionic contaminants and halides which can be quite injurious to semiconductor dice, particularly in the presence of moisture. A number of researchers have reported the dendritic corrosion of gold metallisations in the presence of halides," and more recently Frankenthal" has reported an anodisation mechanism that occurs in the presence of non-complexing media such as sulphate salts or high relative humidities. The anodisation mechanism is known to generate a voluminous Au(OH») reaction very similar to that found at the surface of the SO micropackaged dice in batch 0, where the gold metallisation has been exposed by cracks in the nitride passivation. If the conditions obtained within the SO encapsulation ofsource B during damp heat stress were sufficient to corrode the robust Ti-Pt-Au metallisation, it is not surprising that the aluminium metallised ICs suffered a poorer fate. In contrast, the aluminium metallised ICs from source E were remarkably long lived, despite the extent of corrosion revealed during failure analyses. Source E components proved to be the best of the SO packaged ICs that were evaluated, but unfortunately dice were not obtainable from this source to enable a comparison with ICs in coated form. 6.

Conclusions

This study in support of the development of cost-effective micropackaging for hybrids and sub-systems has revealed encouragingly good reliability performance from both aluminium metallised oxide-passivated ICs and Ti-Pt-Au metallised nitride-passivated ICs in SO packages and plastic-coated low cost chip carriers subjected to damp heat and thermal overstress. The indications are that many of the types of encapsulation would survive for 20 years in a range of telecomms environments, and that some combinations of encapsulation and IC technology would be even longer lived. Despite early setbacks, excellent results have been obtained with the improved PCBCC and with coated Ti-Pt-Au metallised nitride-passivated ICs, indicating that an optimum combination would be to use the coatings and the PCBCC to encapsulate tri-metallised nitrided ICs (provided that the IC dice were intrinsically reliable). An order of merit has been produced from the findings of this exercise and enables a choice of other options if the need should arise. For instance, the use of a ceramic CC with a top coating over the junction coating, can be a good option. Promising results were also obtained from SO micropackaged ICs, particularly from source E, although their survival beyond 20 year operation in damp environments would eventually be curtailed by corrosion of the metallisation. The corrosion of aluminium metallisations would be more rapid than that of Ti-Pt-Au metallisations. The results are altogether very encouraging indeed for the prospects of low cost, plastic , micropackaging for high reliability applications. 7. AcknOWledgments .Many important contributions to this exercise are acknowledged with gratitude: John Herington and Andy Saunders of British Telecom Research Labs (BTRLl, and personnel of Tectonic 24

Electronics for preparation of the test vehicles; Philip Strudwick of ERAtechnology and Richard Tillman and Paul Woods of BTAL who conducted the overstress tests; and finally Jim Bryant, Alan Cross, Bob Merrett and Mike Whybray of BTAL who carried out different parts of the failure analyses. Acknowledgment is also made to the Director of Systems Evolution and Standards Department of British Telecom for permission to publish this paper. 8.

References

[1] Sinnadurai, F. N., Wilson, K. and Brace, D., "Some Problems and Possible Solutions for Hybrid Microcircuit Reliability", Microelectronics Journal 11,26-36 (1980). [2] Sinnadurai, F. N., " An Evaluat ion of Plastic Coatings for High Reliability Microcircuits" ,Proc. 3rd European Hybrid Microelectronics Conference, pp.482-492 (1981). Also Microelectronics Journal 12,30-38 (1981). [3] Wong, Ching-Ping, "Room Temperature Vulcanised Silicone as Integrated Circuit Coating", International Journal for Hybrid Microelectronics, 14,315-319 (special issue 1981). [4] Boetti, A., et aI, "Investigation into MicropackagingTechniques for High-Rei Active Chips", Proc. 3rd European Hybrid Microelectronics Conference, 75-88 (1981). [5] Saunders, A. G. and Roberts, D. A., "Packaging Trends in British Telecom Equipment", Proc. Semiconductor International, Brighton, England, 87-90(22-24 Sept. 1981). [6] Sinnadurai, F. N., Cook, A. 1. and Gumett, K.W., "Integrated Circuit Chip Carrier", UK patent application No. 8103840 (1981). [7] Reynolds, F. u., "Thermally Accelerated Ageing of Semiconductor Components", Proc. IEEE, 62,2,212-222 (Feb. 1974). [8] Sinnadurai, F. N., "The Accelerated Ageing of Plastic Encapsulated Semiconductor Devices in Environments Containing a High Vapour Pressure of Water" , Microelectronics and Reliability, 13, 1,23-27 (1974). [9] Melia, A. 1. and Sinnadurai, F. N., "A Reliability Study of Low Power TTL Integrated Circuits", Inst. Physics, Meeting on Physical Basis of Quality Assurance of Electronic Components (24 Ian. 1975). . [10] British Standards Specification 9400 for Electronic Components o f Assured Quality, Amendment No.4, 31 October 1979, test method3030B . [11] Merrett. R. P., "A Dynamic Method of Calibrating a Mass Spectrometer for Measuring the Water Content of Hermetic Semiconductor Encapsulations", ARPA/NBI Workshop, National Bureau of Standards (22-23March 1978). [12] Sbar, N. L. and Kozakiewich, "New Acceleration Factors for Temperature Humidity Bias Testing", 16th Annual Proc. IEEE ReI. PhysicsSymposium, pp .161-178 (1978). [13] Gruthaner, F., Griswold, T. and Bright, H., "Migratory Gold Resistive Shorts (MGRS) FailuresChemical Aspects of a Failure Mechanism", Proc. 13th Annual Reliability Physics Symposium of the IEEE, 99-106 (1975). [14] Frankenthal, R. P. and Becker, W. H., "Corrosion Failure Mechanisms for Gold Metallisations in Electronic Circuits", J. Electroch em. Soc., U6, 10,1718-1719 (1979). [15] Lum, R. M. and Feinstein, L. G., "Investigation of the Molecular Processes Controlling Corrosion Failure Mechanisms in Plastic Encapsulated Semiconductor Devices", Microelectronics and Reliab., 21,15-31 (1981).

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