Assignment of unexpected tasks in embedded system design process

Accepted Manuscript

Assignment of unexpected tasks in embedded system design process Adam Gorski , Maciej J. Ogorzałek ´ PII: DOI: Reference:

S0141-9331(16)00003-X 10.1016/j.micpro.2016.01.001 MICPRO 2326

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Microprocessors and Microsystems

Received date: Revised date: Accepted date:

26 September 2015 2 December 2015 3 January 2016

Please cite this article as: Adam Gorski , Maciej J. Ogorzałek , Assignment of unexpected ´ tasks in embedded system design process, Microprocessors and Microsystems (2016), doi: 10.1016/j.micpro.2016.01.001

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Assignment of unexpected tasks in embedded system design process Adam Górski*, Maciej J. Ogorzałek.** *Department of Information Technologies, Jagiellonian University, Poland (e-mail: [email protected]) ** Department of Information Technologies, Jagiellonian University, Poland (e-mail: maciej.ogorzalek@ uj.edu.pl).

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Abstract: Embedded systems design process focuses on three areas: modeling, validation and implementation. Typically such procedure assumes constant number of tasks in every instance of designing procedure. Thus the designer must predict all possible tasks executed by the system. Serious problems appear when the system has to execute unexpected tasks. In this case the design process must be repeated. We propose a new approach in embedded system design process which covers such situation. In the approach unexpected tasks are assigned to previously allocated resources. Therefore the system can execute more tasks that were predicted by the designer. Keywords: Embedded systems, unexpected tasks, co-design, 3D integrated circuits, co-synthesis, microprocessors and microcontrollers 

1. INTRODUCTION

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Nowadays embedded systems and software can be found everywhere. For example: modern cars (see. Srovnal et al. (2010), Chandra et al. (2015)), mobile phones (see Sun et al. (2010)), large group of medicine solutions (e.g. Masihpour et. al. (2010), Shoeb at al. (2009), Ölveczky (2008)), face recognition (e.g. Acasandrei et al. (2014)), coordination of different teams in crisis management (e.g. Mahdjoub et al. (2014)), etc. Most of the papers assume distributed target architecture of embedded systems. In such a representation tasks are executed by Processing Elements (PEs). PEs can be divided on two groups: Programmable Processors (PPs) and Hardware Cores (HCs), which are connected in target architecture using Communication Links (CLs).

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Embedded system design process according to De Micheli et al. (1997) consists of: modelling, validation and implementation phases.

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Modelling is the process which provides a hardware/software model of the system. A part of modelling process is cosynthesis (e.g. Densmore et al. (2006), Jozwiak at al. (2010)). Cosynthesis automatically generates the architecture of Embedded system using specification given as a list of parallel processes. The process includes allocation of processors, task assignment and task scheduling. Cosynthesis methodologies can be divided on two basic groups: constructive (e.g. Deniziak et al. (2008)) and iterative improvement (e.g. Oh et al. (2002)). Constructive algorithms build system step by step choosing processing elements for each task separately. Iterative improvements methodologies start from suboptimal solution (usually the fastest) and try to improve system quality by making local changes. Large group of solutions are evolution algorithms like: simulated annealing (e.g. Eles et al. (1997)), genetic algorithms (e.g. Guo at al. (2005), Dick et al. (1998)) and adaptive methodologies (e.g. Górski et al. (2014a)) which are able to adapt to the environment. Especially good results were obtained using genetic programming (Górski et al. (2014b)). Validation (e.g. Ko et al. (2008)) verifies if system works properly and that all the requirement were satisfied.

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A really serious problem with system design process appears when unexpected tasks must be executed. Then in every existing methodology all design process must be repeated. It is needed because every design methodology assumes constant number of tasks that are executed by the embedded system. Even papers that assume unexpected scenarios of embedded systems (e.g. Mise et al. (2006)) concentrate on security and faults detection (e.g. Kovalev et al. (2014)). In this work we propose a new approach to system design process. In our approach the designer can assign unexpected task to existing processing elements without repeating the design process in the case where adding a new PE is not possible. That implies a possibility to react in situations when redesigning is impossible or only part of a design process can be repeated. The approach is also suitable when the system is design re-use. We can also decrease designing costs and cost of the system. The paper is organized as follows: section 2 describes a representation of embedded system, section 3 includes problem statement, section 4 presents a methodology, section 5 the example and in chapter 6 conclusions and future work are given. 2. REPRESENTATION OF EMBEDDED SYSTEM Some of the most popular representations of behaviour of an embedded system are: task graph representation (this representation was used in this paper) and conditional task graph (e.g. Xie et al. (2001)). Another important types of

ACCEPTED MANUSCRIPT representation, amount others, are: c-code (e.g. Venkataramani et al. (2004)) and MATLAB representation (e.g. Banerjee et al.(2000)). Task graph G = {V, E} is consisted of nodes (V) and edges (E). In the graph each node vi Є V represents a task. Each edge eij Є E represents amount of data that has to be transferred between two connected tasks vi and vj. Eles et al. (1998) proposed the concept of an extended task graph. Klaus et al. (2001) applied this concept for analysis of an autonomous robot. We decided to adapt part of this example to describe a robot working on the planet Mars. Figure 1 shows an example of task graph for that robot.

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Fig. 1. Example of a task graph for a robot working on Mars. It consists of 7 nodes corresponding to 7 tasks T0-T6. The numbers at the edges correspond to amount of data that has to be sent between the tasks.

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The system described by above graph executes 7 tasks: T0, T1, T2, T3, T4, T5 and T6. Tasks T1, T2 and T3,T4, T5, T6 are parallel. An example database for the system is presented in table 1. Table 1. Example database

t 103 60 50 86 40 30 150

c 10 34 20 8 8 3 30

HC1 t 30 5 3 10 2 2 25

c 100 93 60 95 40 55 150 c=10

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PP2 C=250

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T0 T1 T2 T3 T4 T5 T6 CL1, b=6

PP1 C=200 t c 100 12 87 23 45 18 90 9 35 5 22 1 190 25 c=3

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Task

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The values in the table were generated randomly. t is the time of the execution of a task, and c is the cost of execution the task or cost of connecting task to CL. C is a cost of a PP. The cost of HC is included in the cost of execution tasks. In the example there are three kinds of PE – two programmable processors and one hardware core. All PEs can be connected using one CL (CL1). All tasks can be executed by every resource, and CL1 can be connected to every PE.

tij 

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tij is the transmission time between tasks vi and vj. eij

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where bCLij is bandwidth between the tasks. If tasks vi and vj are implemented on the same PE, the transmission time will be zero. 3. NEW PROBLEM STATEMENT 3.1 Overview

ACCEPTED MANUSCRIPT Embedded system must execute the designated tasks. All of existing design methodologies assume constant number of tasks. Therefore in Hardware/Software co-synthesis process the database includes time and cost of execution of all predicted tasks. We decided avoid this assumption -unexpected tasks can appear during the design process. Such a problem can be easily resolved by allocation of new components or by new tasks assignment. Therefore much more interesting is situation when all the system is designed and realized. Than it is not possible to extend it by adding new resources. We will concentrate on this problem. We assume that the embedded system is realized and than during its operation unexpected tasks appear. The tasks can also appear after (or during) re-design, partly re-design or design re-use of the system. The system was not originally designed to execute such tasks. Allocation of those tasks can for example extend possibilities and decrease costs of smartphones. It can be also important in space industry for robots working on other planets (moons) in the solar system. In such case there is no possible to change the architecture after unexpected tasks appear. Sending a new robot is also too expensive.

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The new tasks are inserted in the task graph as separate nodes. Depending on the situation unexpected tasks can appear between the original tasks or after them. If unexpected tasks appear between original tasks the structure of the task graph will have to be modified. Unexpected tasks can be split to a number of subtasks (which can be executed on separate resources). In such a situation all of the subtasks must be present in the task graph as separate nodes. In some rare situations, especially when a task consists of a few subtasks, some tasks (subtasks) will have to start theirs execution at the same time. 3.2 New representation

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In this work we also assume that embedded system under consideration is described by a task graphs. However the graph is modified during the design process. Figure 2 presents an example of a modified task graph from figure 1. T0

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Fig. 2. Modified task graph. It contains four additional tasks T7- T10 (compare with figure 1).

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The figure 2 indicates that there are four unexpected tasks: T7, T8, T9 and T10. Task T5 is a predecessor of tasks: T8, T9 and T10. Task T3 is a predecessor of task T7. In this case all additional tasks are parallel and do not modify the order of previous tasks and structure of graph presented on figure 1. We must underline that in general the structure of base graph can be modified. The additional tasks can appear between two connected tasks. Thus amount of data needed to be transferred between two connected tasks can also be different. However such modifications has no impact on methodology presented in section 3. Table 2 gives an example of the values of time and cost for unexpected tasks. All the values were generated randomly.

Task T7 T8 T9 T10

PP1 t c 80 15 40 8 230 22 130 25

Table 2. Values of time and cost for additional tasks PP2

t 90 55 200 150

HC1 c 10 4 19 18

t 10 6 11 20

c 98 70 250 160

The table also includes values for HC1, however hardware cores cannot be chosen because using HC implies allocation of new PE, which is not possible. 4. THE METHODOLOGY

ACCEPTED MANUSCRIPT The methodology proposed in this paper is based on iterative improvements algorithms, which are able to escape local minima. Such approaches are widely used in embedded system design. We start from a system designed by any known methodology without taking it on account the unexpected tasks. At the beginning all new (unexpected) tasks are assigned to the fastest PE. Next for each task the following value (Vi) is calculated: Vi  t * c .

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where t is the time of execution of i-task, and c is the cost of execution this task. In a similar way we can calculate the values of Vi for all PEs able to execute each additional task.

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The final system must meet the time constrains but it is possible that after appearance of unexpected tasks the time limit for the system can be extended. The designer sets the value M as the minimal viable gain. The gain is difference between value of Vi functions for different task allocations. The methodology does not change previous tasks allocations.

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Finally all additional tasks with the gain value greater than M are moved from the fastest implementation to PEs on which the Vi values are the lowest. According to iterative improvements algorithm rules at first the task with the greatest gain is reassigned. If the assignment exceeded time constrains it cannot be performed. In such a case the task is executed on the PE which was chosen before. After each operation the new cost of the system is calculated. Every task with the gain value lower than M, is executed on previously selected PE. The best obtained system is the solution which meets system constrains and has the lowest cost of the system. Only valid solutions are allowed. The overall cost of the system (Co) is described by the following formula: Pe

Co   C PEi   C j   CCLe, PCl

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e 1 l 1

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where r is the number of programmable processors in the system, q is the number of tasks and k is the number of communication links connected to Pe of PEs. The formula includes all of PEs and CLs in the system, and all of the tasks (expected and unexpected) executed by the system. The first part of the sum is the cost of all of the PPs in the system. Second part corresponds to the costs of execution of the tasks (costs of the tasks executed by HCs include costs of the resources). The last one part represents the cost of CLs and its connection to PEs. When task scheduling is needed, the list scheduling is used. 5. THE EXAMPLE

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As an example we have chosen a modified version of autonomous robot proposed by Klaus et al. (2001). The task graph for the system is presented on figure 1. The database for the system is given in table 1. In presented example we assume, that the robot works on planet Mars and the time limit for execution of all the tasks is 100. During design process we obtained a solution for task allocation for the example robot. It consist of two programmable processors PP1 (executes task T4) and PP2 (executes task T5) and five Hardware cores which execute the rest of tasks. All the resources are connected to CL1. Figure 3 presents the described task allocation.

Fig. 3. Task allocation for robot working on Mars. All tasks finish their execution before time equal 89. The cost of the system is 1011. During the work considered robot encountered four unexpected tasks. The task graph for the robot which includes the unexpected tasks is presented in figure 2. The database is given in table 1 and table 2. Because the robot works on Mars and was not designed to execute those unexpected tasks it is not possible to repeat the design process. Additional tasks have to be assigned to accessible resources. At the beginning the fastest solution is created. As fastest solution we understand the system in which all unexpected task are assigned to the fastest available resources (programmable processors). In investigated example the fastest solution is a system where tasks T7, T8 and T10 are assigned to PP1, and T9 is assigned to PP2. Table 3 includes the Values of Vi functions for additional tasks. Hardware core is dedicated to execute only one task thus it cannot be used.

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Vi PP1 1200 320 5060 3250

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The maximum time of execution of all tasks is extended to 450. The cost of the system is 1078, and time of execution of all tasks is 323. We set minimal viable gain as 350. Thus T10 as a task which is characterized with the highest gain of modification (550) is moved to PP2. Task T9 was assigned to PP2 which has minimum value of Vi function. The rest of tasks have gain lower than minimal admissive value (T7 has value of the gain 300, and T8 has the value 100). Therefore those tasks are executed on previously selected resources. The time of execution of all task for the final solution is 436 and cost of the system is 1071. Figure 4 presents the task allocation for the final solution.

Fig. 4. The final task allocation for robot working on Mars.

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We decided to compare the results with greedy algorithms. Table 4 presents comparison of the presented approach with greedy time and greedy cost methodologies. Greedy cost solution allocates all unexpected tasks to the cheapest resources. Greedy time methodology allocates all unexpected tasks to the fastest possible PEs. Table 4. Comparison of obtained results

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Greedy time 323 1078

Presented approach 436 1071

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Time Cost Tmax

Greedy cost 582 1062 450

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Time of execution of all the tasks for greedy cost algorithm is 582. The value is greater than maximum allowed time (450). Therefore the solution is not allowed. Time of execution of all tasks for the greedy time methodology is 323 which is lower than maximum allowed time. However the cost of the solution (1078) is greater than cost obtained by the methodology presented in this paper (1071). The time of execution of all the tasks for the approach is 436. The value is lower than the maximum allowed time. Thus the best solution was obtained using the methodology presented in this work. 6. CONCLUSIONS

In this paper we proposed a new approach which deals with the problem of unexpected tasks. Our approach is based on Iterative improvement algorithms for co-synthesis which are able to escape local minima of optimizing procedures. It is easy to find many situations when unexpected tasks can appear. The tasks can appear in some special conditions as well as in casual situations. We believe that new solutions in this area can make the design process much cheaper, efficient and can decrease the costs of embedded systems too. Therefore some modern systems can be available for wider group of people. The systems will be also more comprehensive. What is more the designers will not need to predict all possible tasks that have to be executed by the system. Thus in our opinion the problem of unexpected tasks is worth to be deeply examined in depth. The future work will concentrate on providing more methodologies that cover the problem of unexpected tasks. We will also examine the influence of unexpected task on the design process and provide solutions for all discovered problems. 7. ACKNOWLEDGEMENTS

ACCEPTED MANUSCRIPT This work is supported by the Foundation for Polish Science, under grant “Mistrz 2012” No. 9/2012: “New computational approaches for solving next generation microelectronic design problems”. REFERENCES

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Adam Górski is a PhD. student and professor’s assistant and at Jagiellonian University in Kraków. He received his MSc degree at Cracow University of Technology. His researches concentrate on embedded systems (especially synthesis and optimization problems), 3d integrated circuits, Internet of Things and genetic programming.

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Maciej J. Ogorzałek is a full Professor and Head of the Department of Information Technologies, Jagiellonian University Krakow, Poland. He held visiting positions in Denmark, Switzerland, Germany, Spain, US, Japan, Hong Kong. In 2000 he worked at the National Microelectronic Center, Seville, Spain. In 2001 he was visiting professor at Kyoto University, in 2005 Hertie Foundation guest professor at The Goethe University Frankfurt-am-Main. Between 2006-2009 he held the Chair of Bio-signals and Systems, Hong Kong Polytechnic University under the Distinguished Scholars Scheme. In 2008 was a president of IEEE CAS Society. Recipient of many awards including IEEE-CAS Golden Jubilee Award and the CASS Guillemin-Cauer Award, 2002, CAS Distinguished Service Award 2012, Education Medal (Poland). In 2012 elected Member of Academia Europaea. In 2014 became IEEE Division 1 Director-elect. Author of over 280 technical papers published in journals and conference proceedings, and the book (Chaos and Complexity in Nonlinear Electronic Circuits World Scientific, 1997).

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