Atomic layer deposition deposited high dielectric constant (κ) ZrAlOx gate insulator enabling high performance ZnSnO thin film transistors

Accepted Manuscript Atomic layer deposition deposited high dielectric constant (κ) ZrAlOx gate insulator enabling high performance ZnSnO thin film transistors

Chuan-Xin Huang, Jun Li, De-Yao Zhong, Cheng-Yu Zhao, Wen-Qing Zhu, JianHua Zhang, Xue-Yin Jiang, Zhi-Lin Zhang PII:

S0749-6036(17)30055-1

DOI:

10.1016/j.spmi.2017.06.011

Reference:

YSPMI 5058

To appear in:

Superlattices and Microstructures

Received Date:

08 January 2017

Accepted Date:

02 June 2017

Please cite this article as: Chuan-Xin Huang, Jun Li, De-Yao Zhong, Cheng-Yu Zhao, Wen-Qing Zhu, Jian-Hua Zhang, Xue-Yin Jiang, Zhi-Lin Zhang, Atomic layer deposition deposited high dielectric constant (κ) ZrAlOx gate insulator enabling high performance ZnSnO thin film transistors,

Superlattices and Microstructures (2017), doi: 10.1016/j.spmi.2017.06.011

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ACCEPTED MANUSCRIPT

Atomic layer deposition deposited high dielectric constant (κ) ZrAlOx gate insulator enabling high performance ZnSnO thin film transistors Chuan-Xin Huang 1, Jun Li 1,, De-Yao Zhong, Cheng-Yu Zhao 1, Wen-Qing Zhu 1, JianHua Zhang 2, Xue-Yin Jiang 1, and Zhi-Lin Zhang 1, 2 1

School of Material Science and Engineering, Shanghai University, Jiading, Shanghai 201800, People’s Republic of China.

2

Key Laboratory of Advanced Display and System Applications, Ministry of Education, Shanghai University, Shanghai 200072, People’s Republic of China.

Abstract The high κ ZrAlOx gate insulators were deposited by atomic layer deposition on silicon and characterized by the different analytical techniques. The grazing incidence X-ray diffraction (GIXRD) verifies that ZrAlOx thin films show an amorphous structure. The X-ray photoelectron spectroscopy (XPS) confirms that the form of ZrAlOx phase improves the electrical properties and stability of the associated devices. Then, all ZrAlOx thin films were integrated in metal-insulator-semiconductor structures to check the electrical capabilities. They all show a low leakage current density (about 1×10-8 A/cm2) under a high electric field of about 2.0 MV/cm, and exhibit a stable capacitance as a function of frequency. Their associated ZTO TFTs were deposited by a radio frequency sputtering, and the influence of the ZrAlOx thickness on the stabilities under positive bias stress and electrical properties is investigated. The 130 nm ZrAlOx based TFT shows the optimized electrical properties (its mobility, threshold voltage, sub-threshold voltage swing and on-off ratio are 12.5 cm2/Vs, 0.3 V, 0.15 V/dec. and 8×107 and the good stability with 2.5 V threshold voltage shift under the positive bias voltage stress. The better properties of 130 nm ZrAlOx based TFTs are attributed to a less interface trap states and surface scattering center. Keywords: Atomic layer deposition, ZrAlOx gate insulator, ZTO TFTs, PBS

)

Corresponding author: E-mail address: [email protected] 1

ACCEPTED MANUSCRIPT stability

1. Introduction Over the past thirty years, transparent conducting oxide (TCO) thin film transistors (TFTs) have been extensively investigated in many applications like active matrix liquid crystal displays, active matrix organic light emitting diodes and see-through displays, since it shows a high mobility and transparency compared with an amorphous Si [1]. Since the last decades, many oxide semiconductors such as ZnO, ZnSnO (ZTO), InZnO (IZO), InZnSnO (IZTO) and InGaZnO (IGZO) [2-6] have received quite intensively attention. Among those oxide semiconductors, IZO based TFTs like HfIZO and IGZO have been extensively carried out in terms of its good electrical properties and high device stability [7]. However, those In based oxide semiconductors have some shortages, including a higher and higher indium prices and the harmful environment effects [8]. Accordingly, there have been significant attempts to find a new oxide semiconductor as an alternative to In based semiconducting oxides. For all of the In-free based semiconducting oxides, ZTO oxide semiconductor films have been currently considered one of the most promising materials to be used as the channel layer of TFTs due to a high mobility and a large optical band gap [9, 10]. Several works have already reported that the ZTO based TFTs exhibite a remarkable device property, and we have also recently demonstrated high performance ZTO TFT with Al2O3 as gate insulator that exhibit a mobility (μ) of 11.0 cm2/V s and a subthreshold swing (SS) of 0.23 V/decade. As a crucial part of TFTs, the dielectric materials also play an significant role in the performance of TFTs. Recently, high dielectric constant (κ) gate dielectrics like HfO2 [12], ZrO2 [13] and TiO2 [14] have received much attention due to a high value of the capacitance, which results in considerable improvements in TFTs performance, in particular, a small operating voltage and large on-state current. Among those gate insulators investigated, ZrO2 has been regarded as one of the most promising gate dielectrics in terms of the high κ (~25), reasonable bandgap (5.68 eV), and high transparency in a visible light [15]. However, ZrO2 thin film tends to crystallize 2

ACCEPTED MANUSCRIPT easily, which will lead to a large leakage current density and a small breakdown voltage [16]. In contrast, although Al2O3 gate dielectric material is an attractive material because of the high electrical dielectric properties and amorphous structure, it has a relatively low κ [17]. Moreover, because adopting a suitable dopant can distort original bond structure, the transition from amorphous to crystallization can be hindered. Consequently, adding other elements into the high κ binary gate insulator can enhance its electrical dielectric properties [18, 19]. Hence, fabricating the ZrAlOx dielectrics with the advantage both a high κ ZrO2 and an amorphous phase Al2O3 is reasonable. Several deposition techniques can be used to grow ZrAlOx thin film, such as RF sputtering, atomic layer deposition (ALD), and also non-vacuum techniques, like sol-gel. Among all deposition techniques, ALD is the most promising technique to provide an accurate thickness and composition with a perfect conformality and good film uniformity [20]. In this study, the high κ ZrAlOx gate insulators were deposited by atomic layer deposition on silicon and characterized by various analytical techniques. In term of the results of these analytical techniques, it indicates that the high κ ZrAlOx gate insulators are very potential materials for TFT application. Consequently, their associated ZTO TFTs were deposited by radio frequency sputtering, and the influence of ZrAlOx thickness on the stabilities under positive bias stress and electrical properties was investigated. The optimized electrical properties and stability under positive bias voltage stress for 130 nm ZrAlOx based TFT is attributed to a less interface trap states and surface scattering center.

2. Experimental details The ZrO2 and Al2O3 films were deposited by ALD technique on a highly-doped Si substrate at 250 °C. ZrO2 films were fabricated by using Tetrakis dimethyl amino zirconium (TDMAZr) and water (H2O) as Zr source and O source. In this process, the TDMAZr bubbler was heated at a temperature of 60 °C. The Al(CH3)3 and H2O vapor were used to form Al2O3 thin film as the sources of aluminum and oxygen. The bottom gate top-contact-type TFTs were fabricated on various-thickness 3

ACCEPTED MANUSCRIPT ZrAlOx thin film (Device A : 130 nm, Device B : 170 nm, Device C : 210 nm and Device D : 250 nm) grown by atom layer deposition as gate insulators. The ZTO active layer was fabricated by radio frequency sputtering sputtering using a 4-in. ZTO target with Zn/Sn atomic ratio of 2:1. The power of ZTO target was set to 50 W. Before sputtering, the chamber pressure was pumped to 4×10-4 Pa. On the process of sputtering, the total pressure was fixed at 0.5 Pa. All TFTs were annealed at 350 °C for 60 min at atmosphere, and then 200-nm-thick Al was fabricated by thermal evaporation with a shadow-mask to form the source-drain electrode. The channel width (W) is 1000 μm and channel length (L) is 100 μm. Finally, the various-thickness ZrAlOxbased TFTs were annealed at 250 °C for 3 min in atmosphere. The alpha step (Alpha-Step IQ) was used to measure the thickness of the film. We used the Agilent E3647A Dual output DC power supply and Keithley 6485 Picoammeter to measure the electrical characteristics of ZTO TFTs, and used Agilent E4980A LRC meter to measure the capacitance characteristics. The structure of ZrAlOx thin films was measured by grazing incidence X-ray diffraction (GIXRD) scans using Cu Kα radition.

We

used

X-ray

photoelectron

spectroscopy

(XPS)

(Thermo-

ESCALAB250XL) to measure the chemical bonding states and chemical composition of films.

3. Result and discussion Fig. 1 shows Al 2p spectra, Zr 3d spectra and O1s spectra for ALD ZrAlOx thin films. The binding energy of those three elements was calibrated by the C 1s peak for C-C bonds at 284.5 eV. The chemical composition of ALD ZrAlOx thin films was analyzed by XPS, and the concentrations of zirconium, aluminum and oxygen element are 9.51%, 25.74%, 64.75%, respectively. Interestingly, as seen in Fig. 1, the Al 2p peaks moves to the direction of lower binding energy (74.9 eV) and the Zr 3d peaks moves to the direction of higher binding energy (183.6 eV). However, as reported previously, Al 2p 3/2 peaks in stoichiometric Al2O3 film and Zr 3d 5/2 peaks in stoichiometric ZrO2 film are found at 75.7 eV and 183.2 eV, repectively[21]. When the electronegativity of aluminum (1.66) and zirconium (1.33) is taken into 4

ACCEPTED MANUSCRIPT consideration, the peak shifts most likely result from a bonding process. In this process, zirconium is easy to lose an electron and aluminum tends to get an electron [21]. Other report have observed a very similar shift of the Al 2p and Zr 3d peaks in ZrAlOx thin films fabricated by thermal ALD and ozone-based ALD [21,22]. This indicates that an electron exchange occurs in ZrAlOx thin films, and the shift of the Al 2p 3/2 peaks and Zr 3d 5/2 peaks shows a high correlation to the generation of a ZrAlOx phase. As is known to all, the ZrAlOx phase is more thermodynamically stable than the phase of Al2O3 and ZrO2 [23], and the ZrAlOx phase is also more dense than a ZrO2 layer [24]. Consequently, ZrAlOx thin film with a high K and high densification can improve the stabilities under positive bias stress and electrical properties. Fig. 1(d) shows the` GIXRD patterns of the ALD ZrAlOx thin films. XRD patterns of the ALD ZrAlOx films are measured at room temperature. In our previous report, a sharp structural peaks at 35.2°in ZrO2 XRD patterns verifies the crystalline structure of the ZrO2 films [25]. Nonetheless, the doped ZrAlOx is amorphous structure without any distinguishing peak, as shown in Fig. 1(d). The transition of amorphous to crystallization also can hinder, because the original bond structure order is distorted by adding a suitable dopant [26]. Consequently, the electrical dielectric properties of the high k binary metal-oxide ZrO2 gate insulators can be improved by doping the Al element into the ZrO2 dielectric. More importantly, the uniform amorphous oxides will decrease the interface trap states between ZTO channel layer and ZrAlOx insulator layer in their associated TFTs, leading to a high electrical properties and stability under various stresses. Meanwhile, the uniform amorphous structure also will be great benefit of their application in large area TFTs. To quantify the electrical dielectric properties of ZrAlOx gate dielectric, the metalinsulator-semiconductor (MIS) sandwich structure devices were carried out. The n-Si was used as a bottom electrode and the thermally evaporated Al as a top electrode. As seen in Fig. 2 (a), the leakage current density of ZrAlOxthin film is less than 1×10-8 A/cm2 under 2.0 MV/cm. An adequate electrical dielectric strength (less than 10−6 A/cm2 under 2 MV/cm) is required for a stable TFT operation [27]. In terms of that, 5

ACCEPTED MANUSCRIPT ZrAlOx thin film is a potential oxide dielectric material as a gate insulator in TFTs. Capacitance–frequency (C–f) measurements were measured by the same MIS structures for the ZrAlOx thin films with various thicknesses. For each of the four devices, capacitance was measured with the frequency from 20 Hz to 2 MHz. The κ of ZrAlOx at 1 kHz is determined to be about 12 (calculated from the equation, COX =εoκ/t, where COX, εo and t are the capacitance of ZrAlOx thin film per unit area, permittivity in vacuum and the thickness of a ZrAlOx thin film, respectively) and the value of κ is higher than that of Al2O3 (8). Moreover, as seen in Fig. 2(b), although the COX decreases slightly with increasing the frequency, the variation of COX between 2 MHz and 20 Hz is less than five percent for all ZrAlOx thin film, indicating a stable COX [17]. The goal of fabricating ZrAlOx thin film is its application for high performance TFT, so ZTO TFT based on the ZrAlOx gate insulator was carried out. The representative transfer characteristic curves at a VDS of 20 V for their associated TFTs as a function of ZrAlOx gate insulator thickness are shown in Fig. 3. As seen in Fig. 3, a very low off-state current (Ioff) (less than 1×10-11 A) is obtained for all devices, ensuring the good performance of their associated TFTs, which results from a low leakage current density confirmed by Fig. 2 (a). Moreover, the transfer characteristic curves shift toward positive direction, and the on-state current (Ion) decreases as the thickness of ZrAlOx gate insulator increases. The Ion/off ratio for Device A, Device B, Device C and Device D is about 8×107, 5.5×107, 4×107 and 2×107, respectively. The threshold voltage (VT) f and the μ for all TFTs with a various-thickness ZrAlOx gate insulator in the saturation region are calculated according to the equation: I DS  VGS  VT   WC i 2L 2

(1)

where IDS, Ci, W and L denote the output current, the capacitance per unit area of ZrAlOx gate insulator, the width and length of the channel layer, The estimated μ and VT are 12.5 cm2/Vs and 0.3 V for Device A, 10.5 cm2/Vs and 1.4 V for Device B, 9.5 cm2/Vs and 3.2 V for Device C and 7 cm2/Vs and 4 V for Device D, respectively. Compare with a thicker ZrAlOx gate insulator based TFT, a lower VT of 130 nm 6

ACCEPTED MANUSCRIPT ZrAlOx based TFT results from a stronger coupling capability to cumulating more charges (per unit area) at the channel layer under the same VGS in a thinner ZrAlOx gate insulator. The slight decrease of μ is due to the less interface trap states and surface scattering center that is confirmed by Capacitance-Voltage (C-V) below. Because a better channel-insulator interface will decrease the suppression of carrier transport, both of which will result in a higher μ [28]. According to the following equation (2), the SS can be obtained from IDS-VGS curves as the minimum VGS needed to increase IDS for a decade: SS  dVGS d LogI DS 

(2)

The SS increases from 0.15 to 0.21 V/dec. with the increase of ZrAlOx insulator thickness, indicating that the interface trap density increases with the increase of ZrAlOx insulator thickness. Moreover, compared with SS, the C-V characteristics are more sensitive to the interface trap states between ZTO channel layer and ZrAlOx insulator layer, so the CV characteristics of various-thickness ZrAlOx based TFTs are measured. The C-V curves for Device A, Device B, Device C and Device D are shown in Fig. 4. The VGS is swept from -10 V to 30 V and reverse biased for the hysteresis measurement at 1 kHZ. As seen in Fig. 4, the accumulation regime with a high capacitance is achieved at positive bias voltage, while the depletion regime with a low capacitance occurs at negative gate bias voltage. Moreover, an distinguishing hysteresis (△) is observed for C-V curves of all devices obviously, it indicates that trap charges are present at interface between ZTO channel layer and ZrAlOx gate insulator [29]. The values of △ are 1.9, 2.5, 3.3 and 4.4 V for Device A, Device B, Device C and Device D,

respectively. From the △, the trap charges can be estimated using the relation [29]: Nt=C0x△/q

(3)

where C0x and q are the accumulation capacitance of ZrAlOx gate insulator per unit area and the elementary charge, Nt are calculated to be about 5.13×1011, 5.32×1011 5.64×1011 and 5.89×1011 cm-2 for Device A, Device B, Device C and Device D, respectively. Obviously, the 250 nm ZrAlOx based TFT shows the largest trap charges 7

ACCEPTED MANUSCRIPT than other TFTs, indicating that the number of interface trap states depends significantly on the thickness of ZrAlOx thin film. The decrease in interface trap states for a thin ZrAlOx insulator layer based TFT will slightly improve the μ, which has been discussed above. Moreover, a less interface trap states will also enhance the stability under positive bias stress (PBS) for TFT application, which will be discussed below. When ZrAlOx based TFTs are applied to active matrix liquid crystal displays and active matrix organic light emitting diodes, they are always exposed to a gate bias stress. Under PBS, the change in VT leads to a current voltage hysteresis that is fatal to current-driven device. For these reasons, the long-term stability of devices under PBS is an important issue to be guaranteed for TFTs application. Consequently, to further comparatively understand the role of ZrAlOx thickness, we investigate the effect of ZrAlOx thickness on the PBS stability of ZTO TFTs. The device is stressed under the following conditions: The effective gate voltage (VGS,eff, VGS,eff = VGS - VT) stress is set to 8 V, and the maximum stress duration is 3,600 s. Fig. 5 shows the evolution of transfer characteristic with the increase of applied stress time for various-thickness ZrAlOx based device. As seen in Fig. 5, the transfer curves for various-thickness ZrAlOx based device move to positive direction, but their shape stay almost constant. Their slope does not show a distinguishing change under the applied PBS, which indicates that the movement can be mostly depicted by the VT shift (△VT) without any μ and SS degradation. This result indicates that the generation of extra electron trapping states under PBS is inappreciable and that the △VT primarily results from the trapped electrons by the traps at the interface between the ZTO channel and ZrAlOx gate insulator or ZrAlOx bulk gate insulator [30]. Moreover, from the SS, in particular， the C-V measurement， they all indicate that the interface and bulk trap states for various-thickness ZrAlOx based TFT with reducing the thickness of ZrAlOx gate insulator. The decrease in interface trap states between ZTO channel layer and ZrAlOx insulator layer will result in trapping little electrons, which will decrease the VT shift under the same PBS. Consequently, as seen in Fig. 4, the values of △VT become larger from 2.9 to 4.7 V with increasing the thickness of ZrAlOx gate 8

ACCEPTED MANUSCRIPT insulator. As a result, 130 nm ZrAlOx based TFT shows the best μ and the best PBS stability than others.

4. Conclusion In summary, the high κ ZrAlOx gate insulator was fabricated by atomic layer deposition. The ZrAlOx gate insulators show an amorphous structure, a stable capacitance as a function of frequency and a better uniformity associated with a low leakage current density. This indicates that all thickness ZrAlOx gate insulators are very promising materials for TFTs application. As a result, the ZrAlOx gate insulators based ZTO TFTs are fabricated by radio frequency sputtering, and the thickness of ZrAlOx gate insulators is optimized. The 130 nm ZrAlOx based TFT shows large μ, small VT, small SS, and very low interface trapped charge density. More importantly, the best stability of 130 nm ZrAlOx based TFT demonstrates that a less interface trap states can improve not only the electrical properties of TFT but also their stability under various stresses. TFTs with a high κ ZrAlOx gate insulator show a promising application for active matrix liquid crystal displays and active matrix organic light emitting diodes.

5. Acknowledgements This work is supported by the Shanghai Science and Technology Commission (15JC1402000), Natural Science Foundation of China (51302165, 61274082), Program of Shanghai Subject Chief Scientist (14XD1401800) and National Key Research and Development Program of China (2016YFB0401100).

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Figures Fig. 1 XPS spectra of ZrAlOx thin films for (a) Zr 3d, (b) Al 2p, (c) O 1s, (d) XRD 10

ACCEPTED MANUSCRIPT patterns of ZrAlOx thin films. Fig.2 (a) Leakage current density as a function of voltage bias. (b) Capacitance– frequency (C–f) measurements as a function of frequency from 20 Hz to 2 MHz. Fig. 3. Transfer characteristics of ZTO TFTs with various thickness ZrAlOx gate insulator. Fig. 4. The C-V curves for various devices, (a) 130 nm ZrAlOx gate insulator based TFT, (b) 170 nm ZrAlOx gate insulator based TFT, (c) 210 nm ZrAlOx gate insulator based TFT, (d) 250 nm ZrAlOx gate insulator based TFT. Fig. 5. Evolution of the transfer curves for various devices, under positive bias stress for 3600s. (a) 130 nm ZrAlOx gate insulator based TFT, (b) 170 nm ZrAlOx gate insulator based TFT, (c) 210 nm ZrAlOx gate insulator based TFT, (d) 250 nm ZrAlOx gate insulator based TFT.

11

ACCEPTED MANUSCRIPT Highlights:  The novel high κ ZrAlOx gate insulator.  The atomic layer deposition technique.  The ZnSnO thin film transistors  The stability under positive gate voltage bias stress.