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Back-bias effect on the current-voltage characteristics of amorphous silicon thin-film transistors
Journal of Non-Crystalline Solids 149 (1992) 264-268 North-Holland
IOURUaL or NON-CRYSTALLINESOLI~
Back-bias effect on the current-voltage characteristics of amorphous silicon thin-film transistors * Y. Kaneko, K. Tsutsui and T. Tsukada Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan Received 24 October 1991 Revised manuscript received 2 June 1992
The electrical potential of the back-surface of amorphous silicon thin-film transistors is controlled by a back bias, Vbb, applied to the back-gate electrode of a dual-gate structure. The threshold voltage of the transistor moves in the negative direction when Vbb is positive; this movement is similar to the substrate-bias effect of conventional metal-oxide-semiconductor transistors. The type of majority carriers of the off-current is determined by the polarity of the Vbb: electrons for Vbh > 0 V and holes for Vbb < 0 V. Amorphous silicon thin-film transistors that operate more stably can therefore be made by optimizing the electrical conditions at or near the back surface of the amorphous silicon layer.
1. Introduction
2. Experiments
Amorphous silicon thin-film transistors (a-Si TFTs) have been used to drive image sensors and liquid crystal displays [1,2], and the most common structure of a-Si TFTs is the bottom-gate inverted staggered type with a silicon nitride (SIN) gate insulator [3,4]. Although, little is known about how TFT characteristics are affected by the electrical conditions of the interface between a-Si and the passivation (back-surface), polyimide passivation has been reported to degrade the subthreshold characteristics [5]. To achieve highly stabilized operation, it is necessary to more closely study the back-bias effect on the TFT characteristics. This paper describes the way in which the current-voltage characteristics of a-Si TFTs are affected by an electrically modulated back surface.
2.1. Sample preparation
* This paper was presented at 14th ICAS, Garmisch-Partenkirchen, Germany, August 19-23, 1991. Correspondence to: Dr Y. Kaneko, Central Research Laboratory, Hitachi Ltd., PO Box 2, Kokubunji, Tokyo 1985, Japan. Telefax: + 81-423 27 7780.
The typical rf plasma (13.56 MHz) deposition and photolithography process was used to fabricate conventional dual-gate a-Si TFTs [6] (fig. 1). The a-Si TFT consists of a Cr bottom gate electrode, a SiN gate insulator, intrinsic and phos-
Back Gate (AI) \
Back Bias Vbb Passivation ? (SIN)
g[
(Ci
a-Si
Fig. 1. Cross-section of a dual-gate a-Si TFT.
0022-3093/92/$05.00 © 1992 - Elsevier Science Publishers B.V. All rights reserved
Kaneko et el. / Back-bias effect on a-Si thin-film transistors
phorus-doped a-Si layers ( i + n + ) , and Cr/A1 source-drain electrodes. The ohmic contact layer, 40 nm thick n + a-Si, between the source and drain was removed by dry etching. To obtain an off-current of < 10-12 A, the intrinsic a-Si was overetched to a depth of > 20 nm [7]. Sample TFTs were p r e p a r e d with gate insulators 0.34 p~m thick and with a-Si thicknesses, t(a-Si), of 0.12, 0.27, 0.49 and 0.79 ~xm. The passivation layer was a 0.8 txm thick stress-free SiN layer deposited at a t e m p e r a t u r e of 170°C. An A1 back-gate electrode was formed on the passivation layer. The channel in these samples was 12 ~ m long and 500 txm wide.
2.2. I,t-V~ measurements For each sample, drain current, I d, vs. gate voltage, Vg, characteristics were measured twice in the dark at a t e m p e r a t u r e of 25 +_ I°C. In a back-bias experiment, a dc back-bias, Vbb, was applied to the back gate. In each measurement, this Vbb, which was applied in addition to the conventional gate voltage, Vg, and the 10 V drain voltage, Vd, was kept constant at a value between - 20 and 20 V. These results were compared with the characteristics measured when Vbb = gg, i.e., the dual-gate driving mode [6]. A Hewlett-Packard 4140B pA m e t e r / d c voltage m e t e r was used for the measurements. In all these experiments, the accuracies of GId/I d and GV/V were respectively 0.5% and 0.1%. The threshold voltage, Vt, and the field effect mobility,/z, were evaluated by applying the gradual channel approximation [8] to the saturated drain current. That is, the Vt and /x values were derived from the differential curves o f (Id)l/2-Vg. by using the relation (Id) 1/2= (tzCiW/2L)I/Z(vg - V t ) ; where W, L, and Ci are channel width, channel length, and the gate insulator capacitance per unit area. Experimental errors included i n / z were up to _+0.025 c m Z / V s. Because the channel quality of the interface between the a-Si and the SiN passivation layer was not optimized, the threshold voltage of the T F T drifted during the Ia-Vg m e a s u r e m e n t under a constant bias of Vbb. The amount of the drift was larger than those observed in the con-
265
ventional single gate TFTs [9]. This Vt drift could prevent observation of the net back-bias effect, so these TFTs were annealed at 200°C for 1 h to initialize the Vt before each ld-Vg measurement. This initialization procedure reduced the errors in the Vt values to < 0.2 V. These errors in # and Vt caused the observed on-current to vary between measurements, but Glo,/lon values were typically within 6% of each other.
3. Results
Both the on-current (Vg = 10 V) and off-current (Vg = - 5 V) of the characteristics depended on Vbb (fig. 2). As Vbb was increased from - 2 0 to 20 V, the off-current at first decreased, reaching a minimum value around Vbb = 0 V, and then increased. These results indicate that the polarity of the majority carriers of the off-current strongly depends on the polarity of the back bias; this effect is discussed below. On-current increased monotonically with increasing back bias. The degree of on-current enhancement is clearly shown in fig. 3. The on-current, /on, is normalized by Ion0 (10.2 txA), which is the on-current at a Vbb of 0 V. As Vbb ranges
10 -4
10
-6
t(a-Si) = O.12 #m Vd = 10 V ~
,#-oO-E.,,==
j E 10-8
,&O-A
A A
O
O
o o
.__ 1 0 - 1 0
Am Am
,,
Vbb (V)
J= Iz
o •
•
-20
•
-10
o 0
Q
A []
10 -12
10 20
O 10 -14
-10
,
!
,
0
t
10
,
20
Vg (V) Fig. 2. ld-Vg characteristics of duaL-gate TFTs measured when a constant dc voltage Vbb was applied to the back gate.
266
Y.. Kaneko et al. / Back-bias effect on a-Si thin-film transistors 0.2 t(a-Si)
~tm
O
I o n 0 = 1 0 . 2 ~A in0 = 0.52 cm 2/Vs
o a
= 0.12
O
~,2 tO
> >
O
Ion /Iono'~b'O
O
o.1
O 0
o
•
•
O
0(~
0
0
0
o
•
I
I
0.2
' -20
' ' -10
0
'
I
I
0.6
0.8
I
,
.0
t(a-Si) (lam)
I
I'0
I
0.4
~t/la0 |
0-30
i
i
20
30
Fig. 5. Dependence of the back-bias effect on the a-Si thickness.
Vbb (V) Fig. 3. Dependence of normalized on-current and mobility on back bias. Errors included in on-current and mobility are + 0.5 FxA and _+0.025 c m 2 / V s, respectively.
from - 2 0 to 20 V, the on-current increased by a factor of more than six. Two characteristic parameters of the on-current increase were investigated: the electron field effect mobility, /x, and the threshold voltage, Vt. These parameters were evaluated in the saturation region by using the gradual channel approximation stated previously. Figure 3 shows the change in the field effect mobility by plotting a normalized form, /x//x0,
where ix0 is the mobility at a Vbb of 0 V and is equal to 0 . 5 2 cmZ/V s. Over the same Vbb range, the ratio /x/ix 0 increases slightly, from 0.92 to 1.05. These results prove that the back bias has little effect on the field effect mobility. The threshold voltage instead changed significantly with Vbb (fig. 4). The Vt moves toward the positive direction when Vbb is negative and vice versa. Because this voltage shift corresponds to a
30 O
t(a-Si) = 0.12 I,tm
,J
O Vbb = Vg (Dual-Gate Driving) 2O 0 0 []
>
[]
t(a-Si) 0 • 0.12 pm []:0.791am
0
[]
--Vbb --
v
O []
= Cons tant 12V lOV 8v
o//,
/////"" ~//
4v
6 I []
O
t--
[]
[]
~
10 --
[]
0 0
0 0
-230
-20
- 0
0
;
0
'
20
0 30
Vbb (V) Fig. 4. Threshold voltage, Vt, vs. the back-bias voltage, Vbb. Errors included in Vt are _+0.2 V.
0
5
10
15
Vg (v) Fig. 6. Comparison of the dual-gate driving mode with the back-bias driving mode.
Y. Kaneko et al. / Back-bias effect on a-Si thin-film transistors
parallel shift of the above-threshold region in Id-Vg characteristics (see fig. 6), it explains why
the on-current defined at a fixed gate voltage increases with increasing Vbb. Figure 4 also shows that Vt is less sensitive to the back bias when the amorphous silicon layer is thicker. For both thicknesses, however, the dependency of Vt on Vbb is roughly linear as Vbb ranges from - 2 0 to 20 V. Figure 5 shows-how the absolute value of the slope [dVt/dVbb I Varies with t(a-Si).
4. Discussion
The back-bias effect occurs because the potential at the back surface of the a-Si layer is mainly determined by the field induced by the Vbb and, in turn, strongly affects the potential at the bottom surface of the a-Si layer. This potential determines the threshold voltage, Vt, which is the characteristic voltage at which the electron channel forms at the bottom surface. As measured experimentally, the magnitude of Vt shift therefore increases when the a-Si layer is thinner. Even though a-Si TFTs differ from conventional metal-oxide-semiconductor (MOS) transistors by having an insulator layer between semiconductor and biasing electrode and by having a quite different configuration of electrodes, the back-bias effect causes the Vt of an a-Si TFT to shift in the same direction that the substrate-bias effect shifts the Vt of an MOS transistor. Unfortunately, the relationship between the back bias and the Vt has not been formulated, because of the difficulty in formulating Vt based on the exact physical significance which is filling all the deep states in a-Si. The linear dependence of on Vbb, however, gives some clues to the formulation of Vt. The results of on-current increase explain the reported increase of drain current observed in dual-gate driving [6]. Figure 6 compares the dual-gate driving mode with the back-bias driving mode (i.e., the data at constant back biases). As stated previously, the curves are parallel in the above-threshold region (Vg greater thzin about 3 V). It is obvious that the data for dual-gate driv-
267
ing can be reproduced by the data of back-bias experiments. In other words, according to the data shown in fig. 4, during dual-gate driving, the Vt at each gate voltage decreases continuously as Vg is increased. The drain current therefore becomes larger than the value that could be obtained by the conventional bottom-gate driving. The dependence of off-current on the Vbb is interpreted as follows. Even though the date voltage turns off the electron channel of TFTs, the back bias controls carrier conduction at the back surface by modulating band bending in a-Si. When Vbb = 0 V, the off-current is held at the lowest level, which is almost the same as those of the TFTs without the back-gate electrode. When Vbb 0 V, carriers flowing in the channel at the back surface (back channel) dominate the off-current. The type of majority carrier in the back channel depends on the polarity of Vbb. When Vbb < 0 V, the majority carriers are holes and the off-current increases as the a-Si band bends up at the back surface. When Vbb > 0 V, on the other hand, the majority carriers change from holes to electrons. The difference between the magnitude of the hole conduction and the electron conduction is due to the mobility difference between holes and electrons and to the presence of the ohmic contact n + layer. Subthreshold characteristics deteriorate for both positive and negative Vbb. When the Vbb = 0 V, the subthreshold slope OVg/O logl0(Id) is 0.61 V/decade, whereas the slope is 1.1 when Vbb = --20 V, and 4.5 when Vbb = 20 V. Although the subthreshold slope is conventionally discussed in relation to the density of states in the amorphous silicon [10], the deterioration discussed here may not be caused by changes in the density of states. Instead, the current component flowing at the back surface in these experiments is expected to make the subthreshold slope less steep. Finally, the effect of the fixed charges in the SiN passivation layer can easily be deduced from the back-bias effect. Fixed charges at or near the back surface produce an effect similar to the back-bias effect; positive fixed charges correspond to positive back bias. If the polarity of the fixed charges is negative, the energy band of amorphous silicon at the back surface bends up,
268
Y. Kaneko et al. / Back-bias effect on a-Si thin-film transistors
the same as when a negative back bias is applied. The threshold voltage can therefore be inferred to increase according to the results of back-bias experiments. If the fixed charges are positive, the threshold voltage decreases and the off-current increases drastically. In both cases, the subthreshold slope decreases. In addition, if the a-Si layer was thin (e.g., < 0.1 ~m), the fixed charges at the back surface would seriously damage the switching characteristics of TFTs: those charges, if any, should be eliminated. The subthreshold deterioration that occurs with polyimide passivation [5], as well as its interpretation in terms of surface polarization, are consistent with the results of our back-bias experiments. In any case, the fixed charges at the back surface are undesirable for stable operation of a-Si TFTs.
5. Conclusions
Back-bias effects of a-Si TFTs have been determined: both on-current and off-current have been shown to depend on the back bias. The apparent enhancement of the on-current is caused by the change in threshold voltage, which shifts in a direction similar to the shift associated with the substrate-bias effect of conventional MOS transistors. The dependency of the threshold voltage
on the back bias is linear and the slope becomes steeper as the a-Si becomes thinner. To stabilize TFT characteristics, charges at the back surface built-up by the unstable electrical conditions should be removed. The authors wish to thank Hideaki Yamamoto for preparing the samples and Toshikazu Shimada for his valuable discussions.
References [1] Y. Kaneko, A. Sasano and T. Tsukada, IEEE Trans. Electron Devices 36 (1989) 2953. [2] Y. Kaneko, N. Koike, K. Tsutsui and T. Tsukada, Appl. Phys. Lett. 56 (1990) 650. [3] P.G. LeComber, J. Non-Cryst. Solids 115 (1989) 1. [4] T.L. Credelle, in: Proc. Int, Display Research Conf., San Diego, CA, 1988 (IEEE, New York, 1988) p. 208. [5] T. Ogawa, H. Wakemoto, H. Takezawa and S. Hotta, in: Extended Abstracts, 22nd Int. Conf. Solid State Devices and Materials, Sendai, Japan, 1990 (Japan Society of Applied Physics, Tokyo, 1990) p. 1039. [6] H.C. Tuan, M.J. Thompson, N.M. Johnson and R.A. Luian, IEEE Electron Device Lett. EDL-3 (1982) 357. [7] A. Sasano, H. Matsumaru, Y. Kaneko and T. Tsukada, J. Non-Cryst. Solids 97&98 (1987) 1295. [8] S.M. Sze, Physics of Semiconductor Devices (Wiley, New York, 1981). [9] Y. Kaneko, A. Sasano and T. Tsukada, J. Appl. Phys. 69 (1991) 73011 [10] T. Leroux, Solid-State Electron. 29 (1986) 47.
IOURUaL or NON-CRYSTALLINESOLI~
Back-bias effect on the current-voltage characteristics of amorphous silicon thin-film transistors * Y. Kaneko, K. Tsutsui and T. Tsukada Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan Received 24 October 1991 Revised manuscript received 2 June 1992
The electrical potential of the back-surface of amorphous silicon thin-film transistors is controlled by a back bias, Vbb, applied to the back-gate electrode of a dual-gate structure. The threshold voltage of the transistor moves in the negative direction when Vbb is positive; this movement is similar to the substrate-bias effect of conventional metal-oxide-semiconductor transistors. The type of majority carriers of the off-current is determined by the polarity of the Vbb: electrons for Vbh > 0 V and holes for Vbb < 0 V. Amorphous silicon thin-film transistors that operate more stably can therefore be made by optimizing the electrical conditions at or near the back surface of the amorphous silicon layer.
1. Introduction
2. Experiments
Amorphous silicon thin-film transistors (a-Si TFTs) have been used to drive image sensors and liquid crystal displays [1,2], and the most common structure of a-Si TFTs is the bottom-gate inverted staggered type with a silicon nitride (SIN) gate insulator [3,4]. Although, little is known about how TFT characteristics are affected by the electrical conditions of the interface between a-Si and the passivation (back-surface), polyimide passivation has been reported to degrade the subthreshold characteristics [5]. To achieve highly stabilized operation, it is necessary to more closely study the back-bias effect on the TFT characteristics. This paper describes the way in which the current-voltage characteristics of a-Si TFTs are affected by an electrically modulated back surface.
2.1. Sample preparation
* This paper was presented at 14th ICAS, Garmisch-Partenkirchen, Germany, August 19-23, 1991. Correspondence to: Dr Y. Kaneko, Central Research Laboratory, Hitachi Ltd., PO Box 2, Kokubunji, Tokyo 1985, Japan. Telefax: + 81-423 27 7780.
The typical rf plasma (13.56 MHz) deposition and photolithography process was used to fabricate conventional dual-gate a-Si TFTs [6] (fig. 1). The a-Si TFT consists of a Cr bottom gate electrode, a SiN gate insulator, intrinsic and phos-
Back Gate (AI) \
Back Bias Vbb Passivation ? (SIN)
g[
(Ci
a-Si
Fig. 1. Cross-section of a dual-gate a-Si TFT.
0022-3093/92/$05.00 © 1992 - Elsevier Science Publishers B.V. All rights reserved
Kaneko et el. / Back-bias effect on a-Si thin-film transistors
phorus-doped a-Si layers ( i + n + ) , and Cr/A1 source-drain electrodes. The ohmic contact layer, 40 nm thick n + a-Si, between the source and drain was removed by dry etching. To obtain an off-current of < 10-12 A, the intrinsic a-Si was overetched to a depth of > 20 nm [7]. Sample TFTs were p r e p a r e d with gate insulators 0.34 p~m thick and with a-Si thicknesses, t(a-Si), of 0.12, 0.27, 0.49 and 0.79 ~xm. The passivation layer was a 0.8 txm thick stress-free SiN layer deposited at a t e m p e r a t u r e of 170°C. An A1 back-gate electrode was formed on the passivation layer. The channel in these samples was 12 ~ m long and 500 txm wide.
2.2. I,t-V~ measurements For each sample, drain current, I d, vs. gate voltage, Vg, characteristics were measured twice in the dark at a t e m p e r a t u r e of 25 +_ I°C. In a back-bias experiment, a dc back-bias, Vbb, was applied to the back gate. In each measurement, this Vbb, which was applied in addition to the conventional gate voltage, Vg, and the 10 V drain voltage, Vd, was kept constant at a value between - 20 and 20 V. These results were compared with the characteristics measured when Vbb = gg, i.e., the dual-gate driving mode [6]. A Hewlett-Packard 4140B pA m e t e r / d c voltage m e t e r was used for the measurements. In all these experiments, the accuracies of GId/I d and GV/V were respectively 0.5% and 0.1%. The threshold voltage, Vt, and the field effect mobility,/z, were evaluated by applying the gradual channel approximation [8] to the saturated drain current. That is, the Vt and /x values were derived from the differential curves o f (Id)l/2-Vg. by using the relation (Id) 1/2= (tzCiW/2L)I/Z(vg - V t ) ; where W, L, and Ci are channel width, channel length, and the gate insulator capacitance per unit area. Experimental errors included i n / z were up to _+0.025 c m Z / V s. Because the channel quality of the interface between the a-Si and the SiN passivation layer was not optimized, the threshold voltage of the T F T drifted during the Ia-Vg m e a s u r e m e n t under a constant bias of Vbb. The amount of the drift was larger than those observed in the con-
265
ventional single gate TFTs [9]. This Vt drift could prevent observation of the net back-bias effect, so these TFTs were annealed at 200°C for 1 h to initialize the Vt before each ld-Vg measurement. This initialization procedure reduced the errors in the Vt values to < 0.2 V. These errors in # and Vt caused the observed on-current to vary between measurements, but Glo,/lon values were typically within 6% of each other.
3. Results
Both the on-current (Vg = 10 V) and off-current (Vg = - 5 V) of the characteristics depended on Vbb (fig. 2). As Vbb was increased from - 2 0 to 20 V, the off-current at first decreased, reaching a minimum value around Vbb = 0 V, and then increased. These results indicate that the polarity of the majority carriers of the off-current strongly depends on the polarity of the back bias; this effect is discussed below. On-current increased monotonically with increasing back bias. The degree of on-current enhancement is clearly shown in fig. 3. The on-current, /on, is normalized by Ion0 (10.2 txA), which is the on-current at a Vbb of 0 V. As Vbb ranges
10 -4
10
-6
t(a-Si) = O.12 #m Vd = 10 V ~
,#-oO-E.,,==
j E 10-8
,&O-A
A A
O
O
o o
.__ 1 0 - 1 0
Am Am
,,
Vbb (V)
J= Iz
o •
•
-20
•
-10
o 0
Q
A []
10 -12
10 20
O 10 -14
-10
,
!
,
0
t
10
,
20
Vg (V) Fig. 2. ld-Vg characteristics of duaL-gate TFTs measured when a constant dc voltage Vbb was applied to the back gate.
266
Y.. Kaneko et al. / Back-bias effect on a-Si thin-film transistors 0.2 t(a-Si)
~tm
O
I o n 0 = 1 0 . 2 ~A in0 = 0.52 cm 2/Vs
o a
= 0.12
O
~,2 tO
> >
O
Ion /Iono'~b'O
O
o.1
O 0
o
•
•
O
0(~
0
0
0
o
•
I
I
0.2
' -20
' ' -10
0
'
I
I
0.6
0.8
I
,
.0
t(a-Si) (lam)
I
I'0
I
0.4
~t/la0 |
0-30
i
i
20
30
Fig. 5. Dependence of the back-bias effect on the a-Si thickness.
Vbb (V) Fig. 3. Dependence of normalized on-current and mobility on back bias. Errors included in on-current and mobility are + 0.5 FxA and _+0.025 c m 2 / V s, respectively.
from - 2 0 to 20 V, the on-current increased by a factor of more than six. Two characteristic parameters of the on-current increase were investigated: the electron field effect mobility, /x, and the threshold voltage, Vt. These parameters were evaluated in the saturation region by using the gradual channel approximation stated previously. Figure 3 shows the change in the field effect mobility by plotting a normalized form, /x//x0,
where ix0 is the mobility at a Vbb of 0 V and is equal to 0 . 5 2 cmZ/V s. Over the same Vbb range, the ratio /x/ix 0 increases slightly, from 0.92 to 1.05. These results prove that the back bias has little effect on the field effect mobility. The threshold voltage instead changed significantly with Vbb (fig. 4). The Vt moves toward the positive direction when Vbb is negative and vice versa. Because this voltage shift corresponds to a
30 O
t(a-Si) = 0.12 I,tm
,J
O Vbb = Vg (Dual-Gate Driving) 2O 0 0 []
>
[]
t(a-Si) 0 • 0.12 pm []:0.791am
0
[]
--Vbb --
v
O []
= Cons tant 12V lOV 8v
o//,
/////"" ~//
4v
6 I []
O
t--
[]
[]
~
10 --
[]
0 0
0 0
-230
-20
- 0
0
;
0
'
20
0 30
Vbb (V) Fig. 4. Threshold voltage, Vt, vs. the back-bias voltage, Vbb. Errors included in Vt are _+0.2 V.
0
5
10
15
Vg (v) Fig. 6. Comparison of the dual-gate driving mode with the back-bias driving mode.
Y. Kaneko et al. / Back-bias effect on a-Si thin-film transistors
parallel shift of the above-threshold region in Id-Vg characteristics (see fig. 6), it explains why
the on-current defined at a fixed gate voltage increases with increasing Vbb. Figure 4 also shows that Vt is less sensitive to the back bias when the amorphous silicon layer is thicker. For both thicknesses, however, the dependency of Vt on Vbb is roughly linear as Vbb ranges from - 2 0 to 20 V. Figure 5 shows-how the absolute value of the slope [dVt/dVbb I Varies with t(a-Si).
4. Discussion
The back-bias effect occurs because the potential at the back surface of the a-Si layer is mainly determined by the field induced by the Vbb and, in turn, strongly affects the potential at the bottom surface of the a-Si layer. This potential determines the threshold voltage, Vt, which is the characteristic voltage at which the electron channel forms at the bottom surface. As measured experimentally, the magnitude of Vt shift therefore increases when the a-Si layer is thinner. Even though a-Si TFTs differ from conventional metal-oxide-semiconductor (MOS) transistors by having an insulator layer between semiconductor and biasing electrode and by having a quite different configuration of electrodes, the back-bias effect causes the Vt of an a-Si TFT to shift in the same direction that the substrate-bias effect shifts the Vt of an MOS transistor. Unfortunately, the relationship between the back bias and the Vt has not been formulated, because of the difficulty in formulating Vt based on the exact physical significance which is filling all the deep states in a-Si. The linear dependence of on Vbb, however, gives some clues to the formulation of Vt. The results of on-current increase explain the reported increase of drain current observed in dual-gate driving [6]. Figure 6 compares the dual-gate driving mode with the back-bias driving mode (i.e., the data at constant back biases). As stated previously, the curves are parallel in the above-threshold region (Vg greater thzin about 3 V). It is obvious that the data for dual-gate driv-
267
ing can be reproduced by the data of back-bias experiments. In other words, according to the data shown in fig. 4, during dual-gate driving, the Vt at each gate voltage decreases continuously as Vg is increased. The drain current therefore becomes larger than the value that could be obtained by the conventional bottom-gate driving. The dependence of off-current on the Vbb is interpreted as follows. Even though the date voltage turns off the electron channel of TFTs, the back bias controls carrier conduction at the back surface by modulating band bending in a-Si. When Vbb = 0 V, the off-current is held at the lowest level, which is almost the same as those of the TFTs without the back-gate electrode. When Vbb 0 V, carriers flowing in the channel at the back surface (back channel) dominate the off-current. The type of majority carrier in the back channel depends on the polarity of Vbb. When Vbb < 0 V, the majority carriers are holes and the off-current increases as the a-Si band bends up at the back surface. When Vbb > 0 V, on the other hand, the majority carriers change from holes to electrons. The difference between the magnitude of the hole conduction and the electron conduction is due to the mobility difference between holes and electrons and to the presence of the ohmic contact n + layer. Subthreshold characteristics deteriorate for both positive and negative Vbb. When the Vbb = 0 V, the subthreshold slope OVg/O logl0(Id) is 0.61 V/decade, whereas the slope is 1.1 when Vbb = --20 V, and 4.5 when Vbb = 20 V. Although the subthreshold slope is conventionally discussed in relation to the density of states in the amorphous silicon [10], the deterioration discussed here may not be caused by changes in the density of states. Instead, the current component flowing at the back surface in these experiments is expected to make the subthreshold slope less steep. Finally, the effect of the fixed charges in the SiN passivation layer can easily be deduced from the back-bias effect. Fixed charges at or near the back surface produce an effect similar to the back-bias effect; positive fixed charges correspond to positive back bias. If the polarity of the fixed charges is negative, the energy band of amorphous silicon at the back surface bends up,
268
Y. Kaneko et al. / Back-bias effect on a-Si thin-film transistors
the same as when a negative back bias is applied. The threshold voltage can therefore be inferred to increase according to the results of back-bias experiments. If the fixed charges are positive, the threshold voltage decreases and the off-current increases drastically. In both cases, the subthreshold slope decreases. In addition, if the a-Si layer was thin (e.g., < 0.1 ~m), the fixed charges at the back surface would seriously damage the switching characteristics of TFTs: those charges, if any, should be eliminated. The subthreshold deterioration that occurs with polyimide passivation [5], as well as its interpretation in terms of surface polarization, are consistent with the results of our back-bias experiments. In any case, the fixed charges at the back surface are undesirable for stable operation of a-Si TFTs.
5. Conclusions
Back-bias effects of a-Si TFTs have been determined: both on-current and off-current have been shown to depend on the back bias. The apparent enhancement of the on-current is caused by the change in threshold voltage, which shifts in a direction similar to the shift associated with the substrate-bias effect of conventional MOS transistors. The dependency of the threshold voltage
on the back bias is linear and the slope becomes steeper as the a-Si becomes thinner. To stabilize TFT characteristics, charges at the back surface built-up by the unstable electrical conditions should be removed. The authors wish to thank Hideaki Yamamoto for preparing the samples and Toshikazu Shimada for his valuable discussions.
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