Bias temperature instability in scaled CMOS technologies: A circuit perspective

Microelectronics Reliability 81 (2018) 31–40

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Bias temperature instability in scaled CMOS technologies: A circuit perspective

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A. Kerber , T. Nigam Reliability Engineering, GLOBALFOUNDRIES Inc., 400 Stone Break Road extension, Malta, NY 12020, USA

A R T I C L E I N F O

A B S T R A C T

Keywords: High-k dielectrics Metal gate BTI RTN SRAM Ring-oscillators CMOS

Bias temperature instability has impacted scaling of conventional poly-Si/SiON CMOS technologies and remains a critical device reliability mechanism for metal gate/high-k stacks in planar and FinFET device architecture. The material and modeling aspects have been extensively studied using discrete MOSFETs and more recently expanded to CMOS circuits to demonstrate its impact on digital circuit aging. In this paper we summarize our understanding of the BTI mechanism in scaled CMOS technologies and discuss the correlation between discrete device degradation and circuit/SRAM aging.

1. Introduction Bias temperature instability has emerged as the key reliability limiter for technology scaling in sub 45 nm nodes [1]. It was first stated as a challenge for CMOS technology in the 130 nm node with the transition from buried channel to surface channel PMOS devices [2]. Presence of Nitrogen in SiO2 to reduce electrical gate oxide thickness and to enable good short channel control lead to significant effort in understanding the underlying physics and material optimization to minimize its magnitude. BTI effort in literature can be broadly characterized into three areas: material impact, defect study (generation vs charge trapping) and circuit level implication. Impact of material on BTI has been discussed extensively in the literature [1,3] from both gate oxide perspective and for different channel material [4]. Incorporation of Nitrogen, leads to enhanced charge trapping reducing the voltage acceleration exponent (VAE) and time slope for NBTI [5], while the introduction of SiGe channel reduces NBTI due to band off set changing carrier injection [4,6]. Introduction of HfO2 based metal gate (MG)/high-k (HK) dielectric stacks in scaled technology nodes lead to the occurrence of PBTI in NMOS devices [7]. PBTI is attributed to charge trapping in the HK dielectric and is a strong function of the SiO2 like interlayer thickness, the HK layer thickness and presence of materials such as La for work function adjustment [8–11]. In this work, all the data presented was collected on MG/HK but the methodology/concepts can be extended to other materials. The physical understanding for BTI is linked to two aspects, defect generation at the interface/bulk and charge trapping into preexisting

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defects cause by the presence of holes in NBTI and electron trapping in HK MG for PBTI. Extensive modeling effort has been carried out to understand voltage acceleration factor for the power law model typically between 3 and 5 for NBTI and 7 and 9 for PBTI, time slope (0.16–0.25) and activation energy (0.1–0.2 eV) [5,12]. Generation of interface states during NBTI stress leads to both mobility degradation and threshold voltage shift while for PBTI only threshold voltage shift is measured [13]. An additional key observation for BTI is the observed recovery post DC stress and recovery during AC stress from low stress frequency up to the GHz range. Presence of recovery provides significant circuit level relief enhancing product lifetime. Circuit level impact of BTI can be categorized into three families, degradation in logic components which is governed by mean threshold voltage (VT) shift and recovery, memory elements like SRAM that is dominated by mean VT shift and BTI induced increase in variability for small devices, finally analog application where devices experience a DC like stress with AC modulation for product lifetime assessment. In recent years, the focus in BTI optimization has shifted towards circuit level solutions which include aging aware design [14–16] and statistical modeling of time-zero (T0) processing induced variability along with aging related BTI variability [17]. In this publication, we will provide an overview of typical test structures being used to study the mean degradation and impact of variability. Such studies have been done on both Planar and FinFET technology with HfO2 based MG/HK and some aspects were also verified on Poly/SiON hardware. This learning can be applied to any material system or FET architecture. The observed voltage acceleration,

Corresponding author. E-mail address: [email protected] (A. Kerber).

https://doi.org/10.1016/j.microrel.2017.12.006 Received 17 October 2017; Received in revised form 2 December 2017; Accepted 2 December 2017 0026-2714/ © 2017 Elsevier Ltd. All rights reserved.

Microelectronics Reliability 81 (2018) 31–40

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Fig. 2. Schematic voltage – time trace for constant voltage stress (CVS) and voltage ramp stress (VRS) procedure with intermittent sense measurement.

Fig. 1. Schematic of device structures used to obtain statistical relevant device degradation data. In addition to the conventional single FET (a) and multi-finger FET (b), stacked FETs (c) and transistor arrays (d) are implemented. Stacked FETs are tailored to determine the mean degradation while transistor arrays enable 3σ data collection on a single wafer.

time slope and activation energy values are presented. Impact of FET architecture (Planar vs FinFET) shows an improved PBTI while NBTI is similar or slightly degraded. Recovery in PBTI and NBTI is discussed for the gate-first (GF) [18,19] and the replacement metal gate (RMG) [20,21] integration approach. The paper focuses on discussing the impact of BTI on logic circuits via ring oscillator stress, decoupling BTI and HCI in digital circuits along with self-heating impact in FinFET and SOI technologies. BTI induced variability models, RTN and device mismatch for SRAMs are also addressed.

Fig. 3. Schematic illustration of the ring-oscillator design with shared ground (GND) and separate power supply pins for the oscillator (VDD RO) and divider (VDD divider). The enable pin can be used to define a dynamic (enable = “1”) and static (enable = “0”) stress mode [24, reprinted with permission from IEEE].

2. Experimental The MG/HK devices used throughout this work cover RMG [22] and GF integration schemes [18]. Both planar and FinFET device architectures have been investigated. Tests are mainly carried out at elevated chuck temperature (125 °C) using single gate, multi-finger devices and novel device layouts like stacked FETs or transistor arrays to obtain relevant statistical reliability data with focus on BTI. The device structures are summarized in Fig. 1 [23]. Discrete devices and RO are stressed with either a conventional constant voltage stress (CVS) with stress-sense delay in the range of 10 μs to few ms or voltage ramp stress as shown in Fig. 2. The schematic of a typical RO circuit used for reliability characterization is shown in Fig. 3. To reduce the required tester bandwidth, a frequency divider is placed between RO circuit and the probe pads. To minimize the duration of the sense measurement, synchronized switching of the supply voltage by the SMUs is introduced [24] (see Fig. 4). Static and dynamic stress modes can be realized by biasing enable = “0” and enable = “1”, respectively. In addition supply currents at stress and sense readouts are recorded for diagnostic purposes.

Fig. 4. Voltage time traces of VDD RO, VDD divider, output and enable terminals. Note the time resolved switching of supply voltages to RO, divider and enable terminal essential for the fast stress-and-sense RO characterization methodology [24, reprinted with permission from IEEE].

3. BTI in discrete devices

measurements using either state-of-the-art semiconductor parameter analyzers or experimental characterization tools. Both commercial and experimental setups used throughout this work have yielded matching results. The relevance of the reduced sense measurement interval for projection of BTI degradation to long term and low voltage use conditions becomes evident from the data shown in Fig. 5 for RMG planar devices which was obtained using a large stacked FET and a multiple sense readout procedure [29]. For pFET devices at short stress times, the ultra-fast (10 μs) and fast (2 ms) readout show several mV differences which become less evident as the stress time and degradation

Discrete device characterization as function of voltage, time and temperature is discussed in this section. Reaction-Diffusion model [25] and charge trapping models [26] are widely used to describe the NBTI phenomenon while electron trapping in oxygen vacancies in the high-k dielectric is proposed as origin for PBTI [7]. Recovery effects related to NBTI [27] and PBTI [28] have dominated the discussion on characterization methodology for the past 10 years. Strong efforts have been made to reduce the sense measurement interval from the original slow intermittent sweep measurements to fast (ms) or ultra-fast (μs) spot 32

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Fig. 5. Threshold voltage versus stress time for planar RMG nFET and pFET devices stressed at a chuck temperature of 125 °C using fast (2 ms) or ultra-fast (10 μs) sense delays [reprinted with permission from MRS Advances].

Fig. 7. Temperature dependence of BTI degradation for SOI-FinFET (upper panel) and bulk FinFET (lower panel) devices. Arrhenius activation energy (Ea) for NBTI is matching closely and only a minor difference is noticed for PBTI [12, reprinted with permission from IEEE].

level increases. Since fast and ultra-fast readout merge with increasing stress time, the impact of sense measurement interval diminishes greatly. For nFET devices, even at short stress times there is negligible difference between fast and ultra-fast sense measurements further supporting the notion that ms sense measurements are sufficient to capture the PBTI degradation in RMG planar devices for stress time > 1000 s. The voltage dependence of the BTI mechanism is summarized in Fig. 6 for SOI-FinFET and bulk-FinFET devices. As can be seen the power law VAE of the SOI and bulk-FinFET devices are in good agreement suggesting that the substrate type does not play a role in the BTI mechanism. It should be noted that a higher VAE is typically reported for nFET devices compared to pFET devices and is consistent with literature data [12]. In addition to the VAE, we investigated the temperature dependence of the BTI mechanism for both substrate types across a temperature range from room temperature (30 °C) to 175 °C and found that the Arrhenius activation energy (Ea) for NBTI is matching for the two substrate types. For PBTI, however, minor differences are noticed, as can be seen by the data in Fig. 7.

Impact of device architecture is shown in Fig. 8, where a lower PBTI is observed in RMG FinFET technology as compared to planar RMG devices while NBTI is similar or degraded [30–32]. The reduction in PBTI is attributed to reduction in field across the stack while NBTI is limited by 110 interface [33] and interlayer oxide properties. For digital CMOS circuits operating at arbitrary frequencies, AC stress is equally important and thus should be tested to verify and comprehend potential relief for CMOS circuit reliability. AC NBTI and PBTI recovery is summarized in Fig. 9 for GF planar and RMG FinFET devices [23]. Both gate stack integrations schemes and device architectures show negligible frequency dependence for NBTI. Also for PBTI in RMG FinFET devices no frequency dependence is noticed from subHz to 10 kHz frequency while for GF planar devices a weak dependence is observed with a lower fraction remaining at lower stress frequencies. In general, NBTI shows higher AC recovery compared to PBTI, independent of process integration scheme and choice of device architecture. Since there are minor differences observed for the different integration options, the AC recovery factors need to be determined for each technology node separately. The AC recovery observed on discrete

Fig. 8. Comparison of measured BTI degradation in RMG using planar and FinFET device architecture at 125 °C chuck temperature. Lower PBTI is measured for FinFET devices as compared to planar while NBTI is slightly enhanced [32, reprinted with permission from IEEE].

Fig. 6. Voltage dependence of BTI degradation at fixed stress time for SOI-FinFET (upper panel) and bulk FinFET (lower panel) devices. Note the close matching in power law acceleration factors for both device structures [12, reprinted with permission from IEEE].

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channel gate control over planar bulk or PDSOI devices [36]. It should be noted that for both technologies the local variance scales inversely with the gate area with no sign of saturation up to the largest tested device area. This implies that Poisson scaling is very well preserved on local scale for both planar and FinFET devices [23]. The variance of large area device, however, saturates and reaches a limit, which can be ascribed to process variance limit, when site-to-site and wafer-to-wafer variation is taken into account. To determine this limit for BTI induced ΔVT variance, testing of a large sample is required which can be achieved by inline reliability testing employing the VRS test methodology [37,38]. The example for the 32/28 nm process variance limit is given by the dashed lines in Fig. 10. The ~9 μV2 variance corresponds to a σ value of ~3 mV for a mean shift of ΔVT = 50 mV based on the inline reliability monitoring data [39]. The process variability component of 1.06 = (1 + σ/ΔVT) can be translated into an interlayer thickness variation using a factor of 1.8 ×/Å, determined in ref. [10], resulting in 0.1 Å σ-value for the thickness variation. Since the process variance limit is attributed to interlayer thickness modulation and same process controls are expected for FinFET technologies a similar BTI variance limit is predicted for FinFET devices. The modeling of the BTI induced ΔVT distribution in discrete ultrascaled devices has been investigated in recent years and various approaches have been suggested. Two popular approaches use a Poisson process to randomly introduce charge trap carriers and their impact is approximated either by a normal distribution in the limit case [40] or individual charge carries are considered having an exponentially distributed impact on ΔVT [41]. Both models predict a skew in the tail of the ΔVT distribution particularly at small level of degradation (30 mV and below) which may be the result of random telegraph noise [42]. An alternative approach is to simply use normal distributions to describe the BTI induced variation which explains the data reasonably well for a ΔVT = 50 mV and above [43,44] as shown by the data in Fig. 11. Another factor adding to the complexity of stochastic BTI characterization is the occurrence of random telegraph noise (RTN) like events which skew the tail of the distribution, in particular, when the mean voltage shift is small (see Fig. 11). The impact of RTN in scaled device can readily be seen when a large number of transistors is measured two times and the voltage shift between those readings computed and plotted as cumulative distribution (Fig. 12). For a small fraction of samples a ΔV ~ 20 mV and higher can be observed which can impact

Fig. 9. Frequency dependence of pFET AC NBTI and nFET AC PBTI for GF planar (left) and RMG FinFET devices (right). Note that the remaining fraction for NBTI ranges from ~ 40% to ~ 60% while for PBTI it ranges from ~ 70% to ~ 90%. Negligible frequency dependence is observed for NBTI from sub-Hz to 10 kHz and only a weak dependence for PBTI in GF planar devices is seen [reprinted with permission from Elsevier].

devices is also extended and confirmed in ring oscillator based assessment in Section 4. 3.1. BTI induced variability in discrete devices Aside from determining the mean BTI degradation for DC and AC circuit operation, the stochastic variation of the time-zero VT and BTI induced ΔVT is of particular interest for SRAM circuits. Time-zero variation has widely been studied for many technology nodes and dopant variation has been identified as the main source in scaled bulk planar devices [34]. The BTI induced variance follows similar trends and the variance scales inversely with the device area following the Poisson process [35]. The data for time-zero VT and the BTI induced ΔVT are summarized for GF planar and RMG FinFET devices in Fig. 10. Moving from highly doped GF planar devices to lower doped RMG FinFET devices improved the time-zero variance by at least 4× due to reduced dopant fluctuation. This has been a key driver for the introduction of FinFET technologies in addition to the superior short

Fig. 11. Measured and simulated xBTI voltage shift distributions for degradation up to ± 50 mV using RMG planar devices. Note, for small mean degradation RTN clearly skews the distributions in the high percentile while for larger degradation RTN becomes a minor contributing factor in particular for nFET devices [42, reprinted with permission from IEEE].

Fig. 10. Comparison of time-zero and BTI induced variance versus device area for GF planar 32/28 nm and 14 nm RMG bulk-FinFET devices at ΔVT = 50 mV. The variance scales inversely with gate area locally and saturates to process variance limits for large gate areas across wafer. Note the improvement in time-zero variance for 14 nm FinFETs [reprinted with permission from MRS Advances].

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Fig. 12. Cumulative distribution of the voltage shift for nFET and pFET devices determined by using a diagnostic RTN test. The σ-value for the VT repeatability measurement is ~ 1.5 mV (dashed line) with tails significantly deviating due to random charge trapping events [42, reprinted with permission from IEEE].

Fig. 14. Temperature dependence of RO degradation (Δf/f) for SOI-FinFET and bulk FinFET devices stressed in dynamic mode. Arrhenius activation energy (Ea) for RO degradation is matching closely the NBTI mechanism [12, reprinted with permission from IEEE].

the stochastic BTI distribution when degradation levels are small as shown by the simulations in Fig. 11. Future work should focus on decoupling or accounting for RTN during BTI degradation in scaled devices since initial work indicates that RTN is present at time-zero and does not increase during BTI stress [42].

These acceleration factors indicate BTI as the dominant degradation mechanism at elevated stress temperature and wafer-level test conditions for 101 stage ROs. The temperature dependence of the RO Δf/f degradation measured over a temperature range from 30 °C to 175 °C also suggest that the dominant contributor at typical wafer level stress times is the NBTI mechanism for bulk- and SOI FinFETs (Fig. 14). It should also be noted that the variation in Δf/f for the several ROs tested in Figs. 12 and 13 is relatively small which is consistent with reduced stochastic variation in logic circuits invoking larger number of transistor and thus the circuit degradation is determined by the average degradation of the BTI and HCI mechanism. Note that only a few samples are required for RO characterization since the total gate area of typical RO circuit used for technology development is large enough to suppress the stochastic variation. In Fig. 15, frequency degradation data are plotted on a log-normal scale for ~40 oscillators stressed with a single stress voltage for a specified stress time. The 3.09-sigma variation

4. Bias temperature instability in digital CMOS circuits To correlate discrete device level reliability data to CMOS circuit degradation it is desirable to use a circuit block which can be tested with minimal updates to the test infrastructure. RO circuits provide such property and can be powered with standard source measurement units (SMUs) and only require either a frequency counter or digital storage scope to measure the output frequency. Typical degradation data for 101 stage bulk-FinFET ROs stressed at various stress voltages and at 125 °C chuck temperature is shown in Fig. 12. The data was collected utilizing the fast stress-and-sense RO characterization methodology [24]. The degradation is well modeled with a power law time evolution (n ~ 0.25) and power law voltage acceleration (VAE ~ 7.5).

Fig. 15. Cumulative distribution of Δf/f degradation at nominal use voltage for oscillators stressed at fixed stress time (tref) and stress voltage (Vref). The 3.09 sigma variation or 1000 ppm failure fraction is comprehended by a scale parameter of kWC = 1.28 [32, reprinted with permission from IEEE].

Fig. 13. RO frequency degradation (Δf/f) measured at wafer-level and 125 °C chuck temperature using a fast stress-and-sense characterization methodology [24]. Lines represent power law degradation model in voltage and time [12, reprinted with permission from IEEE].

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Fig. 18. RO frequency degradation (Δf/f) measured at wafer-level and 30 °C chuck temperature. At high stress voltage the increase in RO degradation is attributed to HCI contributions. Lines represent power law degradation model in voltage and time for BTI, HCI and HCI + BTI [12, reprinted with permission from IEEE].

Fig. 16. Frequency degradation versus sense voltage for RMG FinFET oscillators for 3 different VT flavors. Sense voltage dependence can be described by an exponential model over 300 mV VDD range [reprinted with permission from Elsevier].

degradation at 125 °C is summarized in Fig. 17 for RO with varying number of stages covering a range of ~1000 ×. A negligible impact of stress frequency on the frequency degradation is observed when comparing RO with same design and gate stack process. It is worthwhile to note that for RMG FinFET process the RO degradation for dynamic stress is significantly reduced compared to static stress which is attributed to the reduced PBTI in FinFET and significant NBTI recovery effects, consistent with discrete device level recovery discussed in Section 3. Lack of frequency dependence points to a BTI limited degradation at elevated temperature typically used in commercial products.

or 1000 ppm failure fraction is given by a scale parameter of kWC = 1.28. To benchmark the RO frequency degradation across different device flavors and suppliers, it is important to comprehend the impact of the sense condition. For the same amount of BTI induced ΔVT, the impact on the frequency degradation is reduced when a higher sense voltage is chosen. The same also applies when comparing circuits with low VT devices to circuits where devices with high VT are being used to reduce the power consumption. The overdrive impact can simply be modeled using an exponential dependence as summarized by the data in Fig. 16.

4.2. Decoupling BTI and HCI component in RO circuit degradation 4.1. BTI induced RO circuit degradation

The key to distinguish between HCI and BTI degradation is thorough study of the time evolution and the voltage/temperature dependence. HCI degradation typically exhibits a higher power law time slope (n > 0.3) and higher voltage acceleration exponent (VAE ~ 10) along with a lower activation energy (~ 0.05 eV) for nFET devices [12] compared to the BTI mechanism. Thus the impact of HCI is only to be expected for high voltage stress and low temperature condition at typical wafer level test times of 10 ks. When reducing the chuck temperature from 125 °C to 30 °C and boosting the stress voltages a change in the time evolution of the Δf/f degradation can be observed, as shown in Fig. 18 for bulk-FinFET devices. The increase in the time evolution of the Δf/f degradation at high stress voltage is attributed to the HCI mechanism. The Δf/f degradation at 30 °C can be modeled by combining a power law model for BTI and a power law model for HCI as illustrated by the lines in Fig. 18. To verify the contributions of HCI to EOL degradation long term tests at reduced stress voltages need to be carried out to confirm the HCI voltage dependence in digital circuits. In addition to bulk-FinFET RO we have studied 101 stage RO built with SOI-FinFETs devices at a chuck temperature of 30 °C and summarized the data in Fig. 19. As can be seen bulk- and SOI FinFET RO exhibit similar BTI degradation and HCI contribution leading to an increase in time evolution at high stress voltage. This is another confirmation that the basic device degradation mechanism in FinFET device is not dependent on the substrate type.

More frequently, RO circuits are used to study BTI and HCI in CMOS circuits by subjecting them to conventional CVS tests [24,45,46]. The impact of stress frequency and stress mode on the RO frequency

Fig. 17. RO degradation (Δf/f) for dynamic (enable = “1”) and static stress mode (enable = “0”) for different RO designs with varying number of stages by ~ 1000× using RMG FinFET devices stressed at 125 °C. Note that within each design and gate stack process the frequency dependence in the degradation is negligible [reprinted with permission from IEEE].

4.3. Self-heating in ultra-thin body devices A growing area of concern for scaled CMOS devices is self-heating since the thermal coupling to the Si substrate is reduced for bulk FinFET 36

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Fig. 21. Temperature change versus number of fins per active area (RX) at constant power per fin for bulk-FinFETs normalized to the 5 fin device (left panel). Comparison of self-heating induced average temperature change in n- and pFET sensor for SOI-FinFET and bulk-FinFET devices based on hardware calibrated thermal TCAD model (right panel) [12, reprinted with permission from IEEE].

Fig. 19. Comparison of RO frequency degradation (Δf/f) between bulk- and SOI FinFET device architecture measured at wafer-level and 30 °C chuck temperature for a 101 stage design. Both technologies exhibit comparable BTI degradation and contribution from HCI mechanism at high stress voltage [32, reprinted with permission from IEEE].

therefore study the variation of temperature change with increasing number of fins per RX. In Fig. 21 (left panel) the normalized ΔT is plotted versus number of fins per RX considering test structures with 2, 3, 4, 5 and 20 fin per RX. 2 fin devices exhibit about ½ the self-heating compared to 5 fin devices while 20 fin devices show only a moderate increase of ~25%. A comparison of the average self-heating in bulk-FinFET devices and FinFETs fabricated on SOI substrates is summarized in the right panel of Fig. 21. As can be seen the self-heating induced average temperature change in the n- and pFET sensor is ~4.7 × higher for FinFET devices fabricated on SOI compared to bulk Si substrates based on hardware calibrated thermal TCAD model. These results suggest that in bulkFinFET devices heat flow to the Si substrate through the fins remains effective in limiting the temperature rise in the device [12]. Moving from bulk FinFETs to fully gate surrounded devices like SOI FinFETs, FDSOI devices or nanowires leads to enhanced temperature increase due to self-heating posing a challenge for modeling HCI and characterization of circuit aging at high frequency operation and elevated stress voltages. To address the issue of self-heating in digital circuits operating at high frequency, RO circuits were designed with different number of stages while the internal load capacitance was kept the same. The 101 stage RO is running around ~500 MHz and compared to the 13 stage RO running around ~4 GHz at nominal operation condition. For bulk-FinFET the 13 stage RO shows the same frequency degradation at short stress times as the 101 stage RO which suggests that self-heating is negligible at high voltage stress condition (lower panel of Fig. 22). The increase in degradation at long stress times for the 13 stage RO is due to enhanced HCI contribution as the number of switching events is ~8 times higher compared to the 101 stage RO shows. In case of SOI-FinFET RO (upper panel of Fig. 22) the degradation of the 13 stage RO at short stress time (~ 10 s) is enhanced by ~1.75 × compared to the 101 stage RO suggesting a temperature rise at high voltage stress condition of ~ 30 °C based on the Arrhenius model for RO degradation provided in Fig. 14. The temperature rise of ~30 °C is also consistent with the thermal TCAD model in Fig. 21 when computing the average DC power dissipation per fin at stress condition from the supply current of the RO. In the 101 stage oscillator the temperature rise is reduced by a factor of ~8 due to the lower stress frequency. These results confirm the strong self-heating for SOI-FinFETs while bulk-FinFETs are less impacted due to increased heat flow to the Si substrate.

technologies [47]. The issue of self-heating in PDSOI devices has been known for several generations [48] and comprehended when assessing hot carrier injection (HCI) where heat generation is most pronounced [49]. To mitigate self-heating, the hot carrier stress condition was reduced from Vg = Vd stress condition to Vg < Vd. The temperature increase due to self-heating for typical test structure across a wide range of operation conditions covering hot carrier stress conditions in RMG bulk FinFET devices, is summarized in Fig. 20. The average device temperature increases linearly with the dissipated power per fin and to first order both device types show similar temperature change using a 20 fin per RX test structure when compared at same power dissipation per fin suggesting comparable thermal coupling to the substrate and metal wiring. It should also be noted that the absolute temperature increase at the highest stress condition shown in Fig. 20 is < 30 °C which only moderately impacts the hot carrier assessment given the low activation energy of HCI. The magnitude of self-heating in CMOS circuits is strongly dependent on the density of the active devices and their proximity. We

Fig. 20. Temperature change versus power dissipation per fin derived from a 20 fin per active area (RX) device based on the threshold voltage change in the sensor FET. Moderate temperature change is observed in bulk-FinFETs operated in DC mode at conditions similar to HCI stress [12, reprinted with permission from IEEE].

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Fig. 24. Linear drain current versus gate voltage characteristic of ~ 2500 single bulkFinFET SRAM devices and the average current of 64 fins. 64 fin average shows substantially reduced stochastic variation [12, reprinted with permission from IEEE].

Fig. 22. Comparison of frequency degradation for 13 and 101 stage RO for SOI-FinFET (upper panel) and bulk-FinFETs (lower panel). For bulk-FinFETs at short stress time 13 and 101 stage RO show same degradation while for SOI-FinFETs the 13 stage RO shows a 1.75 × higher degradation due to self-heating.

[50]. Thus, for modeling static noise margin degradation for large memory arrays, knowledge of the mean BTI degradation for static and dynamic operation and the stochastic model parameters describing the variation is important. In addition, potential correlation of BTI degradation to time-zero VT values [43,44] should be comprehended in the modeling of the minimum use voltage for large SRAM arrays. To determine SRAM functionality of large memory arrays, the BTI induced variance beyond 3σ level needs to be determined and modeled. In particular, single devices with high voltage shift are of great concern since these limit the minimum use voltage of SRAM circuits. Obtaining > 3σ level data from discrete devices is difficult and may require dedicated test structures like small transistor arrays [39] or fully integrated addressable devices [51]. The time-zero characteristics for pull-up (PU), pull-down (PD) and pass-gate (PG) transistors in Fig. 24 were obtained using a 8 × 8 transistor matrix using single fin devices. In addition to the individual transistor characteristic the average current of the 64 transistors is shown which exhibits substantially reduced variation. In addition to determining the ΔVT distribution of individual

Furthermore, comparing high frequency with standard RO degradation provides an effective means to address the self-heating concern in digital circuits for future technology nodes. 5. Bias temperature instability in SRAM Assessing the impact of BTI in SRAM circuits relies on accurate modeling of BTI induced VT mismatch. To gain confidence in the applicability of the stochastic SRAM BTI model it is important to establish the correlation between the discrete devices and the cross-coupled-inverter (CCI) used in SRAM. The example of a dynamic stress configuration for CCI is shown in Fig. 23 where the left sense node (SNL) is subjected to an AC signal which alters between the stress voltage and ground subjecting all four transistors to either NBTI or PBTI stress. When the individual transistors are measured before and after the stress and the pre- and post-stress spice models are obtained then the measured transfer characteristics match very well with the simulated results

Fig. 25. Device mismatch distributions for single-fin PD and PU devices measured at time-zero, at the end of stress (EOS) and at the end of an extended recovery period (EOR). Stress time and voltage were chosen to yield comparable shift as projected at end-of-life use condition. No change in mismatch for PD devices while PU devices show a small degradation in sigma value which improves after recovery [12, reprinted with permission from IEEE].

Fig. 23. Measured and simulated pre- and post-stress transfer characteristic for a CCI in GF planar devices subjected to AC stress [50]. Note that measured and simulated characteristics are in very good agreement. To model static noise margin for large memory arrays mean and standard deviation for time zero characteristic and BTI induced degradation are essential.

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6. Summary Bias temperature instability dominates typical digital CMOS circuit and SRAM devices aging at stress and end-of-life operation conditions. Comprehending recovery effects associated with BTI are important for quantitative correlation between device degradation and RO circuit aging. The RO degradation kinetic is consistent with the device level models and can be used to decouple BTI and HCI components in digital circuits using high stress voltage at reduced ambient temperature. Stochastic variations including the impact of RTN are critical for modeling SRAM degradation while for RO degradation the average device degradation remains more relevant. Self-heating effects are a growing concern for FinFET devices which can be noticed as enhanced RO degradation in SOI-FinFET while they remain negligible in bulkFinFET RO. Acknowledgment Fig. 26. Correlation of stress induced SRAM ΔVmin shift versus time zero Vmin for a 32 nm gate-first MG/HK SOI CMOS process based on dynamic stress mode and stress time of 1000 h. Samples with high Vmin show reduced Vmin degradation compared to low Vmin samples consistent with literature data for discrete CCI circuits [50].

The author would like to acknowledge the discussions and the support by the Reliability Engineering team at GLOBALFOUNDRIES. References

discrete small FET devices, the mismatch distribution of two neighboring devices is also considered an important parameter for SRAM cell design at time zero and end-of-life (EOL) [35]. In Fig. 25 mismatch distributions for nFET PD and pFET PU devices are shown for single-fin devices arranged in an 8 × 8 matrix configuration. The devices were stressed for 300 s at a stress voltage to yield degradation levels comparable to EOL nominal use operation condition followed by an extended recovery period of several days to verify the impact of recovery on the mismatch distributions. As can be seen for nFET devices the mismatch distribution at the end-of-stress (EOS) is unchanged from the time-zero distribution and also at the end-of-recovery (EOR) the distribution is in agreement with the time-zero distribution. This can be explained by the comparatively small PBTI degradation in FinFET technology and by a weak correlation of ΔVT with time-zero VT previously reported for planar CMOS technologies [43,44]. For pFET devices, conversely, degradation of the mismatch distribution is noticed at EOS compared to the time-zero distribution. At EOR a substantial reduction in the NBTI induced mismatch degradation is seen, similar to recovery of the NBTI induced voltage shift. The main contributing factor for increased mismatch degradation in pFET devices at EOL is the substantial improvement in time-zero mismatch due to reduced dopant fluctuation in FinFET technology [36] and the significant NBTI contribution [30]. To illustrate the impact of dynamic stress on SRAM Vmin degradation 256 kb arrays were stressed to 1000 h for a 32 nm gate-first MG/HK SOI CMOS process. In Fig. 26, the measured Vmin degradation is plotted versus the normalized time-zero Vmin and a clear correlation is evident consistent with the device level data shown in ref. [44]. Samples with lower Vmin exhibit higher degradation while samples with higher Vmin show reduced shift and in some cases Vmin improvement can actually be seen. These results indicate that the stress can improve the balance and mismatch of the cell which was also observed in discrete CCI circuits [50]. The assessment of time-zero and stress induced variability at both device and array level is critical to predict circuit level design and aging concerns. The key areas to focus during technology development to ensure SRAM reliability are 1) coupling of time-zero Vt to EOL shift, 2) decoupling Vt shift from RTN signal for tails of the distribution and 3) recovery and its impact on mismatch and static noise margin (SNM) degradation.

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