Bipolar transistor design for improved low current performance

Solid-State ElectronicsVol. 34, No. 7, pp. 701-707, 1991 Printed in Great Britain.All rights reserved

0038-1101/91 $3.00+ 0.00 Copyright © 1991 PergamonPress pie

BIPOLAR T R A N S I S T O R D E S I G N FOR I M P R O V E D LOW CURRENT PERFORMANCE JAMES R. PARKERand DAVID J. ROULSTON Department of Electrical Engineering, University of Waterloo, Waterloo, Ontario, Canada N2L 3G1

(Received 30 March 1990; in revised form 28 November 1990) Abstract--It is shown that by reducing the doping in the vicinity of the emitter-base junction, the low bias emitter-base capacitance can be greatly reduced and the low-current transistor cut-off frequency (ft) increased by several times relative to a conventional double-diffused transistor profile of the same vertical scaling. It is also shown that the reduction in emitter-base capacitance leads to improved noise performance in fiber-optic photodiode preamplifier applications. A low emitter-base concentration or LEBC transistor structure is examined where a very lightly doped or intrinsic layer is inserted between the neutral base and emitter regions. Expressions for the delay time in this intrinsic region are studied and analytic design equations are developed for maximizing transistor ft at a given collector current bias.

1. INTRODUCTION While the desire for faster, smaller and more efficient devices is always present, there is also a need for application-specific design and optimization at the transistor level. One such case is low current, low noise communications and opto-electronic circuits where tailoring of the device characteristics to match the operating bias conditions can yield significantly improved performance without major and expensive advances in process technology. In general, the electrical parameters of the bipolar transistor (i.e. current gain and forward delay time) are functions of the bias and vary with the collector current, Ic. Usually a circuit is designed such that the transistors operate at a collector current associated with the minimum transistor delay time or maximum transition frequency, ft. Operating transistors at lower current densities offers several general advantages including lower power requirements, reduced shot noise and reduced heat dissipation. Low current operation is desirable in front-end photodiode pre-amplifier circuits for example, where optimum noise performance is obtained at collector currents much less than that of peakf~. It has been shown[l] that the mean square equivalent input noise current, i2n, due to a bipolar transistor front end has a minimum which occurs at a collector current given by:

Icopt = 2xCo VT B Vfll3 ] ½

L~J

(I)

where C O is the total capacitance at the input node, B is the bit-rate, fl is the transistor current gain, and 12 and 13 are Personick noise bandwidth integrals. An example of this is given in F_ig. 1 where FTOT, a normalized measure of i~, as computed by BIPOLE[2], and the transistor ft are plotted against collector current density for a uniformly-doped transistor profile (STEP). For a bit rate of 25 Mbit/s, Icop, ssE 34/7-c

701

for noise performance occurs at approx. 5 A/cm 2 while the peak of theft curve is at around 500 A/cm 2. Increased speed at low current densities also raises the possibility of combining photodiodes and higher performance bipolar devices on the same substrate. Typically, the lightly-doped epitaxial layer requirements of the photodiode reduce the current capability and peak ft of on-chip transistors and thus place constraints on the available circuit response. At lower collector currents, the transistor delay time is dominated by the junction capacitance terms. By reducing Re and Cjc, the shape of theft curve can be changed and the low current fall-off reduced. This suggests another advantage; if the current dependency of the transistor ft can be reduced, this provides a greater tolerance in bias conditions for the device and increases the latitude and flexibility available to circuit designers. The curve of Fig. 1 shows that ft increases monotonically with increasing I c at lower currents. This can be seen from the expression: 1 2=ft

-

Cnt g=

z~ + zf

(2)

where C~t = Cje + Cjc + Cdi~is the total input capacitance including junction and diffusion components, gm= Ic/Vt is the transconductance, %e is the transistor delay due to the junction capacitance terms and "~f: C d i f f / g m is the transistor forward transit time. At low current densities, Cje and Cic vary only slowly with I c and thus ft is directly proportional to the collector current approaching a peak value, 1/(2m:) at higher current densities. Beyond this ft falls off rapidly due to the onset of high-current effects such as base widening or Kirk Effect[3]. To make operation at lower currents attractive, the delay time associated with the junction capacitance terms must be reduced.

702

JAMES R. PARKER a n d DAVID J. ROULSTON -i9

i 0 i°

10 9

10 8

'U/ /~

,r~

10 7

--

~ J ~' ' AI~

1 o -27 ~-

~ + --e--

106 ,3x102

,3

FTOT-STEP ft ST025 ft STEP FTOT-ST02! 3x102

10 - 2 2 ,3x104

COLLECTOR CURRENT DENSITY (A/cm 2 ) Fig. 1. BIPOLE noise figure of merit FTOT, and transistor f as functions of collector current density, Jc for a step junction profile with no LEBC region (STEP) and one with an LEBC region width of 0.25 #m (ST025) (B = 25 Mbits/s, Ca = 0.1 pF). In a typical bipolar transistor under normal bias conditions, the capacitance per unit area of the emitter-base junction, Cje, is much larger than that of the collector-base, Cj¢. The gradient of the doping profile is high at the emitter-base junction leading to a large capacitance and the collector-base junction is usually reverse-biased which increases its depletion width and reduces Cjc. Results of BIPOLE simulations show that even under zero bias, Cje is typically an order of magnitude greater per unit area than Cjc. It follows that attempts to improve low current f should first concentrate on the emitter-base capacitance term.

2. E M I T T E R - B A S E PROFILE S T U D I E S

An N + N P N or low emitter concentration (LEC) structure was first reported in 197415]. It was suggested that the N + N barrier in the emitter would

~,

retard the flow of minority carriers in the emitter and lead to large current gains. However, it has been shown[6] that the minority carrier current is primarily determined by the heavily doped emitter region and thus the gain does not differ significantly from the standard double-diffused case. The principle of the LEC transistor can be extended for low current density applications by reducing the N emitter layer doping to form an N+IP emitter-base structure with an intrinsic or very lightly doped layer separating the neutral base and emitter profiles. The shape of the neutral base profile and thus the base transit time, tbb , can then be made independent of the emitter profile with the emitter-base depletion layer extending almost completely into the lightly doped region. Transistor current gain is not adversely affected by the widened junction area because there is little recombination in the lightly doped region and hole injection into the emitter is governed primarily by the heavily doped neutral emitter which is not affected by the addition of the LEBC layer. Similar N+IP junction designs have recently been proposed for reducing the value of the peak electric field and thus the leakage currents in modern shallow, heavily doped emitter-base junctions[7]. LEBC profiles were generated for study here assuming Gaussian diffusions for the N ~ emitter and P base regions with an additional N layer of uniform doping, Nlebc, and width, Wlebc, appended to the diffused emitter profile adjacent to the base. Figure 3 shows the resulting structure for Nlebc= 1013cm -3 and Wleb~= 0.2/~m. Figure 4 shows the SEDAN[4] computed f vs J~ curves for the same profile with several values of W~euc. In all cases, the N + emitter, the base, and the collector portions of the profile were unchanged. The case corresponding to W~e~ = 0 (NOLEBC) is also shown for reference. The results indicate that the presence of the intrinsic or N region increases the low c u r r e n t f by at least 2 3 times in the 1-100 A/cm 2

1 021

I 021

102°t~

1 020

1019~-

1 019

/

4-" I

E 1018

1017 x

x

z 1016

Z

v

\

E 1 018 (.9

L)

\

i111

1017

r

10 ~5 1014

0.0

,,,

t i I, i i i [ , , ii

0.5

.0 1.5 2.0 DEPTH (/~m)

2.5

Fig. 2. Vertical impurity profile for a typical double-diffused bipolar transistor.

1 014

0.0

I

0.2

I

O.4 0.6 0.8 DEPTH (/xm)

I

.0

Fig. 3. Vertical impurity profile for an LEBC transistor with an LEBC region width, WLebc= 0.2/~m.

Bipolar transistor design for improved low current performance

A plot of the total emitter-base capacitance as a function of V~ as calculated by SEDAN is shown for a conventional and an LEBC device in Fig. 5. At low forward bias, the LEBC C~ is much less but for V~ greater than 0.7 V, the advantage of the LEBC region disappears as the higher diffusion capacitance of the LEBC device overtakes the junction delay. The point at which the capacitance curves intersect can be varied by varying the doping and width of the LEBC region. Increasing the doping of the LEBC area extends the cross-over point to higher current densities at the expense of a reduction in the low-current f improvement.

10 l° • w,E, c = o ~,.,, * w,E~c = 0 . 0 5 ~,,', lO 9

-F

• ~,~c

= o 1 ,,,rn

"/ /

I 1

,,/.,~_~---

108

107

106

1 0 -2

COLLECTOR

I 10 2

CURRENT (A/cm 2 )

10 4

range and even more at lower current densities. As WI~~ is increased, the_ft continues to rise at very low current densities with some degradation at higher current values due to increased minority carrier charge storage in the lightly doped emitter-base space charge layer. The decrease in the current dependency of f is evidenced in that at Jc= 10A/cm 2, the Wlebc = 0.1 #m structure is still operating at 10% of its peak f value compared to only 2% for the case with no LEBC region. At 100 A/cm 2, the figures are 25 and 10% respectively. At higher collector current densities, the W~eb~value for m a x i m u m f improvement decreases. As the emitter-base depletion layer becomes narrower with larger forward bias, a smaller LEBC region is required to avoid excess charge storage and high level injection effects in the lightly doped layer. 10-4

/f '$ LEBC

10 -5

It is necessary to establish limits to the improvement possible using LEBC structures and to characterize the additional delay, q~b~, due to the presence of a lightly-doped region between the emitter and base. It is also desirable to develop a physical understanding of the trade-off between conventional depletion capacitance, Cje, and the capacitance, Cl~, due to stored free carrier charge in the LEBC region. Obviously, the optimum point in terms o f f for any given collector current is that where the sum of the two components is minimized. Several papers have been published dealing with either LEC structures or the closely related I2L device which also features an epitaxial emitter layer[6,8,9]. The common assumption made in all these cases is that the LEC region can be treated as a quasi-neutral layer, surrounded by a low-high junction on the N ÷ emitter side and an N P junction on the base side. The condition of neutrality means n = Nle ~ + p, and therefore, dp/dx =dn/dx within the LEC region. SEDAN simulations show that with increasing forward bias, the LEBC region does become quasineutral and the gradient of the hole concentration tends toward that of the free electrons. This leads to a triangular distribution of minority charge in the LEBC layer similar to that in the neutral base. Thus, the delay due to the LEBC region, Zle~, becomes proportional to W~bc and approaches a value of:

w~o~

E L~ ~-

3. CHARACTERIZATION OF THE LEBC JUNCTION DELAY

DENSITY

Fig. 4. SEDAN calculated f vs collector current density J~ for a typical transistor profile with Wi,b~= 0 (NOLEBC) and for several different LEBC widths (NI~~ = 1013 cm-3).

£-.

703

"l~lebcH- 4 D n

(3)

10-6

10 -7

10

-8

~ i i I ~ i p I ~ i i I i i

0.0

0.2

0.4 Vbe

0.6

I I I

0.8

I

I

1.0

(V)

Fig. 5. Total emitter-base capacitance as a function of V~ as calculated by SEDAN for transistors with no LEBC region (NOLEBC) and W]ebc= 0.2/am (LEBC).

which is identical to the expression for the base in high level injection. This agrees with the high current limit developed in[8] and is similar to the expression of[6]. This also confirms that the N - region (N ~< 10~4cm-3) can be considered intrinsic. Note that at high current levels r~e~ becomes constant and proportional to the square of the LEBC region width. This accounts for the reduction inft at higher currents relative to conventional double-diffused structures and indicates that this can be kept to a minimum if desired by keeping W~eb¢less than the width of the base. For example, if Wl,b~ is one half of the base

704

JAMESR. PARKERand DAVIDJ. ROULSTON

width, and assuming the base stays in low level injection, the high current delay due to the LEBC region will be approximately one-eighth of the base delay, %b. A n u m b e r of simulations were done on step junction transistor profiles with uniformly doped N ÷emitter and base regions (as could be obtained from MBE fabrication) and the effects of the LEBC region were isolated by integrating the free carrier density over the width W~b¢to obtain estimates of the LEBC capacitance and its associated delay time at a given bias. These were defined as follows: AQLebc rlebc- AJc

(4)

AQIe~

c~o~c= AF~0"

(5)

The same technique was used to compute a delay, %,, by taking the limits of the integration over the region from the emitter contact to the centroid of the base doping and a total overall delay, % , as the integral over the entire structure. The corresponding capacitances, Cbo and Ctot, were also calculated. The delay components, Zieb~, r~ and "ttot were calculated as a function of Jc for a step junction profile with Witheof 0.25/~m. The LEBC term and the total emitter-base delay, %e, are plotted in Fig. 6. The overall delay is dominated by the emitter-base at current densities up to about 100A/cm z and tends toward a constant value at high current densities which is comparable to the base delay, tbb = 1.25 X 10 ~0S. The LEBC delay term accounts for most of "['bewith a slight drop in significance at very low currents and is particularly important in the 1-100 A/cm z range. Previous results[8] indicated that 10 - 4

• TLEBC (SEDAN) • TBE ,

)

10 - 6

I.J

~

10 -8

>< k12

c3 10 -lc

10-12

I

1

10 - 4

COLLECTOR

I

I

10 - 2

I

~

1

CURRENT

I 10 2

I

I 10 4

DENSITY

Tl~b~would become constant at high current levels and equal to W~ebc2/4Dn.For this profile, that corresponds to a value of approx. 2 × 10 - n s which agrees well with the S E D A N computed curves. It has been shown that Zleb~is the d o m i n a n t delay in the 1-100 A/cm 2 range and that it decreases with increasing current. The interesting thing to observe is the shape of the Zl~b~VS I c curve of Fig. 6. The z~ curve shows clearly a point of inflection where the slope of the curve (on a log-log scale) changes from unity at the lower currents to approx. 1/2 at higher current values. This indicates that the base-emitter delay is changing from a 1lie dependency at low currents to a 1/x/~~ dependency at increased forward bias. At current densities below 1 A/cm 2, the depletion capacitance is the major source of delay, as in the normal transistor, and the value of the capacitance Cj¢ is relatively constant at q / Wick. As the collector current is increased, z~e~ becomes d o m i n a n t and the total delay becomes proportional to 1/x//~. This agrees with the results oti8] for IZL transistors with epitaxial emitters. At even higher currents, z~,~ becomes constant, and in this case, small, compared to the base delay, tbb. Note that for calculation of Zl,b¢, the free carriers are integrated from the fixed physical boundaries of the LEBC region for all biases, while[8] defines the epitaxial layer delay as being due only to the quasineutral area in the LEBC emitter. Thus, the above computed %b~ includes the quasi-neutral component and some of the depletion capacitance term as well. This explains why the slope of the computed Z~eb¢VS I c curve deviates from 1/2 at low currents where Cj~ is dominant. The expression developed in[8] for the delay in the lightly-doped emitter as a function of lc is given by:

W~

qn ~Wle~

(6)

This expression has been plotted for the step junction case with WLEBC= 0.25 /lm and is shown in Fig. 6 along with the ~le~ calculated from S E D A N data. The following values have been assumed for eqn (6): n i = 1.4 × 101° cm-3; D n = 10 cmZ/s and Js = (qn~Dn)/(N, Wb) = 2.133 X 10 11A/cm 2. The agreement is good (within a factor of 2) over the range where *~b~is dominant. This could easily be improved by using better approximations for the collector saturation current, J~ and the other parameters of eqn (6). Assuming the variation of Zl,~ with collector current can be described using an equation similar to eqn (6), we can now develop an analytic expression for the LEBC width which should maximize the f at a given collector current.

( A / c ~ 2) Fig. 6. Calculated values of zt¢~ and z~ as a function of J~ from SEDAN simulations for a uniformly doped step junction profile with a 0.25#m LEBC region. This is compared to the value for ~1,~ predicted by eqn (6).

4. LEBC DESIGN FOR M A X I M U M

ft

At low current densities where the optimal LEBC width is increased, it follows that Nleb~must be kept

Bipolar transistor design for improved low current performance low to maintain depletion. For the Jc values of interest here, the doping of the LEBC region approaches intrinsic and the N~,~ term in the denominator of eqn (6) can be neglected. Thus, to investigate the optimal low current performance, we start by taking the limit as N~b¢ tends to 0:

W~

qn~ I,Vl~~ /4Jcn2~l/2.

lim ~le~= ~ +

Niche~ 0

(7)

This can be simplified to W2¢bc

,

/'/WlebeWb"~

I/N'~ leJ'~l/z

Equation (8) shows that Z~b~ is directly proportional to the width of the LEBC region for a given collector current. We can now use this expression to find an optimum in terms of the overall delay at low currents. The total low current delay is essentially equal to the base-emitter delay (we have shown this previously) which can now be expressed analytically as the sum of Z~b~and the conventional depletion term,

Cje/grn. "['tot ~ "~be~ ~'lebc "~ Cje gm"

Substituting the expressions for these two components gives:

\so) 3

(9)

where the W ~ term of eqn (8) has been neglected at low currents. The minimum overall delay at a given Jc can be found by taking the derivative with respect to W ~ and setting it to zero. dz~ d--~-l~ s~= const.

o= \

/

Yo

705

Equation (11) also predicts that the optimal width will decrease as the desired collector current rises. Substituting the above value for Wte~optinto eqn (8) at Jc = 1 A/cm 2 predicts a value for z~,~ of 3 x 10 -9 s. This is in excellent agreement with SEDAN computed values over a range of LEBC widths based on the previous delay calculations. The values for these delays and capacitances are summarized in Table 1. For a desired Jc of 1 A/cm 2, it was found that the overall delay, "~totis minimized for an LEBC width between 0.1 and 0.2 #m as is % , the delay associated with the entire emitter-base junction area (including both depletion and free carrier terms). This is not unexpected as the emitter-base junction delay usually dominates at low current levels. It also confirms that the optimum point is indeed a trade-off between the free carrier contribution Zle~ which decreases with decreasing W~eb~and the depletion capacitance term which increases with decreasing Wleb¢. The above analysis was repeated for the typical double-diffused profile of Fig. 2. Into this profile were incorporated LEBC regions of differing widths as in the earlier analysis. The SEDAN simulations showed the same trend as observed in the uniformly doped cases, with the most improvement at Jc = 1 A/cm z found for an LEBC width of approx. 0.15pm. The optimal LEBC structure from the TYP profile analysis of above, (Wto~=0.15pm), was used to examine the effect of increasing N~ob~.In this case, no difference was observed in the ft vs Jc characteristics for values ofNje ~ up to 1016 c m 3. For heavier doping levels, the intrinsic layer was no longer completely within the emitter-base junction and the effect on the ft curve was the same as if W~eb~has been reduced. This confirms the original conclusion that the LEBC section should be kept depleted to achieve the maximum benefit from it. The lower the intended current of operation, and the wider the intrinisic layer, the lower the doping must be to satisfy this condition.

(io) 5. TRANSISTOR NOISE PERFORMANCE COMPARISON

Solving for WI~~ gives: TM

= L\

(11)

j

as the expression for the optimal LEBC width for a given collector current density. Using a value for J~ extracted from the SEDAN curve of J¢ vs Vbo, eqn (11) predicts a W~ob~optof 0.14pm for the step junction profile studied earlier.

One application for bipolar transistors with improved low-current performance is in low-noise amplifiers where the collector current bias for minimum noise operation is considerably less than that for peak f . Often, circuit designers are forced to operate at higher collector currents than the minimum noise value to avoid the drop in ft and current gain, fl at lower bias. We show here that in addition to in-

Table 1. Major transistor delays and capacitances as calculated from SEDAN data for devices with several different LEBC region widths (um)

(ns)

(nF/cm 2)

(ns)

(nF/cm 2)

(ns)

(nF/cm z)

rb~/z,ot

0.05 0.10 0.17 0.25 0.50

2.53 3.28 3.48 3.80 6.88

74.9 94.6 100 111 198

6.36 4.82 4.13 4.29 7.12

188 139 119 123 208

6.88 5.33 4.64 4.80 7.63

204 154 134 138 223

0.92 0.90 0.90 0.89 0.93

706

JAMES R. PARKER and DAVID J. ROULSTON

creased ft, the noise contribution of the lightly-doped emitter-base structure devices is reduced relative to the conventional bipolar transistor. The three major sources of noise in the bipolar transistor are the shot noise in the collector and base currents and the thermal noise of the base resistance. For systems where the input signal is a current (i.e. optical fiber or sensor preamplifiers with a photodiode input), the derivation of the noise characteristics at frequences above fa becomes very similar to the FET preamplifier case. In terms of a bit-rate, B: Zn __ -- 4KTrB(27zCa)2B313 + 2 q l b B l 2

2qI~ (2nC,)2B313. + g~

(12)

Here Ca is the sum of detector and stray capacitances at the input, C, and C~ are the input capacitances of the transistor itself, and 12 and 13 are noise bandwidth integrals dependent on the input and output pulse shapes[10]. The transistor input impedance, Z, is assumed to be predominantly capacitive and large compared to rB. The assumption of a capacitive input impedance is valid with the condition that we consider a noise bandwidth, or bit-rate B, which is much higher than the transistor fl-cutoff frequency, fa. A simple figure of merit for the noise performance of the bipolar transistor based on the above analysis and eqn (1) can be defined[10]: ~1/2

FOM = - - . C,

(13)

The SEDAN device simulator was used for comparisons of performance based on the FOM figure of merit. Figure 7 plots FOM vs Jc as calculated from SEDAN simulations for three step junction profiles with LEBC widths of 0, 0.17 and 0.25~m. In this figure Ct is taken as the transistor input capacitance only (i.e. Cd is assumed zero). The peak FOM for the • STEP

0 ST017

• ST025

4.0 o x

,3.0

ol,

2.0

1.0 0.0

., 0 -8

10 - 4

10 2

I

10 - 4

Jc ( A / c m 2 )

Fig. 7. Noise figure of merit (FOM) vs collector current density Jc for step junction profiles with LEBC region widths of 0, 0.17 and 0.25~m.

0.25 # m profile is over four times better than that with no LEBC region. The current for peak FOM occurs in both cases at approx. 10 2 A/cm 2. Inclusion of the detector capacitance Cd reduces the relative improvement by partially masking any differences in internal device Ct. As Cd is increased, the reduction in C~ becomes dominated by Cd and any improvement becomes negligible. Also, the collector current for peak FOM is shifted upward and at high values of It, the increased diffusion capacitance of the LEBC profiles offsets any reduction in Cj~. A second of merit, FTOT, is available using the BIPOLE program which calculates a normalized mean-square equivalent input noise current, i~n, as a function of bias. The bit-rate, B is specified and the results are given for two values of Cd; 0.1 and 0.5 pF. A lower value of FTOT indicates better noise performance. The BIPOLE analysis offers the advantage of automatically extracting important circuit parameters (in this case, rB) as functions of Ic and thus readily lends itself to equivalent circuit calculations. Figure 1 plots both transistorf and FTOT against I~ for the same LEBC and conventional profiles as Fig. 7. The bit-rate is 25 Mbit/s and Cd is 0.1 pF. BIPOLE predicts a minimum in the noise contribution for a collector current density of 2.7 A/cm 2. At this bias both the f is improved and FTOT is reduced by a factor of 3 with the LEBC profile. For a Cd of 0.5 pF, the optimum bias is raised to more than 10 A/cm 2 and the improvement FTOT is 1.6 times. Note that the BIPOLE analysis predicts an improvement in FTOT even at higher currents because BIPOLE overestimates the high current f of th, se types of profiles. The FOM analysis and earlier f studies have shown that the overall input capacitance of the LEBC devices becomes larger than that for conventional devices at high currents because of the excess free carrier storage in the lightly-doped LEBC region. Both the analysis and the simulations indicate that the minimum mean-square input noise current is directly proportional to the input capacitance, C~ = Cd + C. + C,. When C, is large, the noise contribution at the input due to the shot noise of the collector current is increased. If the transistor input capacitance is a significant part of C,, then the noise performance should be improved by vertical doping profiles which reduce the low-current emitter-base capacitance. The same methanism which results in imp_rovedf at low currents is also beneficial in terms of i~. Since/coot is proportional to the bit-rate B, the performance gain becomes more pronounced at lower bit-rates where circuit designers have typically been constrained from operating due to low-current drop off in fl and ft. 6. CONCLUSIONS

It has been shown that it is possible to improve the low current frequency response of the bipolar

Bipolar transistor design for improved low current performance transistor by lowering the doping level in the vicinity of the emitter-base junction, This has been verified by simulations of low emitter-base concentration or LEBC transistor structures with a very lightly doped or intrinsic region inserted between the neutral base and emitter. Such profiles are realizable either by MBE or MOCVD or possibly by direct implantation of the base profile into a lightly doped epitaxial layer. Results from both BIPOLE and SEDAN simulations suggest improvements of several times in ft over conventional double-diffused profiles in the 1-100 A/cm 2 range. At higher currents, the p e a k f of the LEBC devices is reduced due to charge storage in the lightly doped region. This additional delay has been shown to become significant when the LEBC region width becomes comparable to the basewidth. Analytical expressions have been verified for the emitter-base delay as a function of collector current in the LEBC transistors [eqn (8)] and an expression developed [eqn (11)] for the LEBC region width for maximum ft at a given operating bias. The minimum mean-square equivalent noise current for a fiber-optic photodiode preamplifier is directly proportional to the total input capacitance, Ct. Both analysis and simulation results have shown that when the transistor junction capacitance is a significant part of the total input impedance, LEBC

707

transistor designs can improve the low current noise performance in addition to increasing device f . Acknowledgement--This work was supported in part by the

National Science and Engineering Research Council of Canada.

REFERENCES

1. T. Van Muoi, IEEE J. Lightwave Technol. LT-2, 243 (1984). 2. D. J. Roulston, S. G. Chamberlain and J. Sehgal, IEEE Trans. Electron Devices ED-19, 809 (1972). 3. C. T. Kirk, IRE Trans. Electron Devices ED-9, 164 (1962). 4. Z, Yu and R. W. Dutton, SEDAN User's Manual. Stanford University Integrated Circuits Laboratory (1985). 5. H. Yagi and T. Tsuyuki, Proc. Sixth Conf. Solid State Devices, Tokyo (1974). 6. H. C. DeGraff and J. W. Slotboom, Solid-St. Electron. 19, 809 (1976). 7. D. D. Tang, IEEE Electron Device Left. 10(2), 67 (1989). 8. K. W. Kwan, A. Brunnschweiler and D. J. Roulston, Solid-St. Electron. 26, 305 (1983). 9. B. L. Grung, Solid-St. Electron. 21, 821 (1978). 10. R. G. Smith and S. D. Personick, Semiconductor Devices for Optical Communication, Chap. 4. Springer, New York (1980).