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Bright future for laser trimming
World Abstracts on Microelectronics and Reliability
Parasitaroefl'ekte bei bipolaren integrierten Schaitungen. JOACHIM GOERTH. Radio Mentor Electronic, suppL 41. (11) 452 (Nov. 1975). (In German). Parasitic effects with bipolar integrated circuits. In an integrated circuit all components are arranged with as short a distance as possible and made in the same crystal lattice. This is the reason for effects which are undesired and therefore classified as parasitic. The dominant results of these effects are parasitic transistors or thyristors and inversion layers or additional capacities. After a short review on the four layer structure of
183
an integrated circuit the author explains the origin and the effect of the vertical parasitic transistor with the substrate as collector, the epitaxial layer as base and the base region of the wanted transistor as emitter. The vertical parasitic transistor is normally in the off-state. But there are biasing conditions of the wanted transistor to polarize the parasitic one for the on-stage. These cases are discussed in detail. But parasitics are also possible with lateral transistor structures, three cases of this type with npn or pnp as parasitic transistor are mentioned.
6. MICROELECTRONICS--COMPONENTS, SYSTEMS AND EQUIPMENTS A review of random access MOS memories. R. W. MITTERER. First European Solid State Circuits Conference (ESSCIRC), Canterbury p. 125. 2 5 Sept. 1975. The progress achieved internationally in the field of M O S - R A M devices for EDP main memories is described in this paper. Under the continuous pressure to cut costs, storage density and capacity have been increased by a factor of 20 since 1969 so that memory technology has become the pacemaker for large scale integration. Improvements in the readout technique are discussed by taking the 4096 bit memory device Siemens $193 as an example. A more efficient peripheral circuitry, such as internal clock generation, TTL-compatible interface, dynamic address decoders and an integrated output amplifier make it easier for the user to employ these modern components. A number of unavoidable compromises in testing and encapsulation of the devices and in circuit simulation and optimization are dealt with. After a brief review of other storage principles a forecast of the development of dynamic MOS memories is given in conclusion.
(t976). First-order Ricatti equations are obtained for the capacitive 3-wire transmission line of a one-dimensional MOS capacitance which give an order of magnitude improvement in numerical computation time over the transmission matrix solution of the lumped section equivalent circuit model of the transmission line.
A large-scale integrated circuit for low power communication receivers. F. J. H1GHTON. First European Solid State Circuits Col~[brence (ESSCIRC), Canterbury p. 93. ~ 5 Sept. 1975. This paper describes an integrated circuit designed for S.S.B. or A.M. portable receivers and provides the functions of I.F. amplifier, product detector, limiting I.F. amplifier, audio amplifier and a.g.c, generator on one chip. The aim has been to make the circuit as self-contained as possible whilst keeping the quiescent operating current to within 6 mA. The circuit contains its own supply regulator allowing operation from a 15V to 7.5V supply. Thus it will be possible with the inclusion of a simple tuned I/P stage to receive A.M. transmissions up to 30 MHz producing an audio output sufficient to drive a pair of 300 D earphones. For S.S.B. transmissions beyond 30 MHz an R.F. mixer and beat frequency oscillator is required. The circuit has been designed to operate over the full military temperature range.
A physical analysis of the operating temperature limits of complementary MOS transistor integrated circuits. H. MART1NOT, P. ROSSEL, G. VIALARET and G. SARRABAYROUSt/. First European Solid State Circuits Conference (ESSCIRC), Canterbury p. 103.2-5 Sept. 1975. The aim of this work is to determine the maximum and minimum operating temperatures of COS MOS circuits in ceramic packages and to study the performances of these devices within the enlarged temperature range.
MNOS non-volatile quad latch. J. F. DICKSON and D. BOSTOCK. First European Solid State Circuits Conference (ESSCIRC), Canterbury p. 68. 2-5 Sept. 1975. Metal-NitrideOxide-Silicon (MNOS) technology provides the capability of producing semiconductor memory cells, the contents of which are not only electrically alterable, but also retained in the absence of applied power. Bright future for laser trimming. WARREN B. COZZENS. Electronic Engineering p. 58 (Feb. 1976). Trimming electronic components by laser enables high tolerance devices to he produced economically. Warren B. Cozzens details developments to date and discusses materials developments and future trends.
Exact capacitance of a Iossless MOS capacitor. M. J. MCNUTT and C. T. SAH. Solid-State Electronics 19, 225
Characterization of CCD technology on 64 x 128 element photosensor. J. L. BERGER, Y. THENOZ and D. WOEHRN. First European Solid State Circuits Conference (ESSCIRC), Canterbury p. 119. ~ 5 Sept. 1975. The device studied is an array of 128 CCD registers, each of 64 cells, addressed by 128 cell input and output registers. The registers are controlled by two phases and made of two layers of metallization: the first layer is polycrystalline silicon on thin oxide; the second layer is aluminium on thicker oxide to give unidirectional transfer. Although the array can be used with an electrical input, the characteristics were measured with optical input: after an integration time of 32 msec, the array is emptied line by line at a frequency of 1 MHz.
Relays and Iogis ICs can be working partners. PATRICK M. CRANEY. Electronics p. 107 (Jan. 22 1976). Direct interface of mechanical relays and standard logic families provides economy and power-handling capability for many applications. A 2048-bit n-channel fully decoded electrically writable/ erasable nonvolatile read only memory. M. KIKUCHI, S. OHYA, M. KAMAYA, M. KO1KE and H. YAMAMOTO. First European Solid State Circuits Conference (ESSCIRC), Canterbury p. 66. 2-5 Sept. 1975. In recent years, the advent of microcomputer has greatly increased the demand for electrically programmable read only memories (PROMs). This paper will describe a 2048-bit n-channel fully decoded electrically writable/erasable nonvolatile ROM (EAROM) with novel features. In this device, the memory transistor is a stacked-gate MOS FET and the memory cell consists of two transistors. Memory cells and peripheral circuits are fabricated using n-channel silicon gate technology. Relation between the potential-barrier shape and capacitance -voltage characteristics of MIS structures. A. H. M. SHOUSHA. Solid State Commun. 18, (3) 339 (1976) The relation between the potential-barrier shape and capacitance
Parasitaroefl'ekte bei bipolaren integrierten Schaitungen. JOACHIM GOERTH. Radio Mentor Electronic, suppL 41. (11) 452 (Nov. 1975). (In German). Parasitic effects with bipolar integrated circuits. In an integrated circuit all components are arranged with as short a distance as possible and made in the same crystal lattice. This is the reason for effects which are undesired and therefore classified as parasitic. The dominant results of these effects are parasitic transistors or thyristors and inversion layers or additional capacities. After a short review on the four layer structure of
183
an integrated circuit the author explains the origin and the effect of the vertical parasitic transistor with the substrate as collector, the epitaxial layer as base and the base region of the wanted transistor as emitter. The vertical parasitic transistor is normally in the off-state. But there are biasing conditions of the wanted transistor to polarize the parasitic one for the on-stage. These cases are discussed in detail. But parasitics are also possible with lateral transistor structures, three cases of this type with npn or pnp as parasitic transistor are mentioned.
6. MICROELECTRONICS--COMPONENTS, SYSTEMS AND EQUIPMENTS A review of random access MOS memories. R. W. MITTERER. First European Solid State Circuits Conference (ESSCIRC), Canterbury p. 125. 2 5 Sept. 1975. The progress achieved internationally in the field of M O S - R A M devices for EDP main memories is described in this paper. Under the continuous pressure to cut costs, storage density and capacity have been increased by a factor of 20 since 1969 so that memory technology has become the pacemaker for large scale integration. Improvements in the readout technique are discussed by taking the 4096 bit memory device Siemens $193 as an example. A more efficient peripheral circuitry, such as internal clock generation, TTL-compatible interface, dynamic address decoders and an integrated output amplifier make it easier for the user to employ these modern components. A number of unavoidable compromises in testing and encapsulation of the devices and in circuit simulation and optimization are dealt with. After a brief review of other storage principles a forecast of the development of dynamic MOS memories is given in conclusion.
(t976). First-order Ricatti equations are obtained for the capacitive 3-wire transmission line of a one-dimensional MOS capacitance which give an order of magnitude improvement in numerical computation time over the transmission matrix solution of the lumped section equivalent circuit model of the transmission line.
A large-scale integrated circuit for low power communication receivers. F. J. H1GHTON. First European Solid State Circuits Col~[brence (ESSCIRC), Canterbury p. 93. ~ 5 Sept. 1975. This paper describes an integrated circuit designed for S.S.B. or A.M. portable receivers and provides the functions of I.F. amplifier, product detector, limiting I.F. amplifier, audio amplifier and a.g.c, generator on one chip. The aim has been to make the circuit as self-contained as possible whilst keeping the quiescent operating current to within 6 mA. The circuit contains its own supply regulator allowing operation from a 15V to 7.5V supply. Thus it will be possible with the inclusion of a simple tuned I/P stage to receive A.M. transmissions up to 30 MHz producing an audio output sufficient to drive a pair of 300 D earphones. For S.S.B. transmissions beyond 30 MHz an R.F. mixer and beat frequency oscillator is required. The circuit has been designed to operate over the full military temperature range.
A physical analysis of the operating temperature limits of complementary MOS transistor integrated circuits. H. MART1NOT, P. ROSSEL, G. VIALARET and G. SARRABAYROUSt/. First European Solid State Circuits Conference (ESSCIRC), Canterbury p. 103.2-5 Sept. 1975. The aim of this work is to determine the maximum and minimum operating temperatures of COS MOS circuits in ceramic packages and to study the performances of these devices within the enlarged temperature range.
MNOS non-volatile quad latch. J. F. DICKSON and D. BOSTOCK. First European Solid State Circuits Conference (ESSCIRC), Canterbury p. 68. 2-5 Sept. 1975. Metal-NitrideOxide-Silicon (MNOS) technology provides the capability of producing semiconductor memory cells, the contents of which are not only electrically alterable, but also retained in the absence of applied power. Bright future for laser trimming. WARREN B. COZZENS. Electronic Engineering p. 58 (Feb. 1976). Trimming electronic components by laser enables high tolerance devices to he produced economically. Warren B. Cozzens details developments to date and discusses materials developments and future trends.
Exact capacitance of a Iossless MOS capacitor. M. J. MCNUTT and C. T. SAH. Solid-State Electronics 19, 225
Characterization of CCD technology on 64 x 128 element photosensor. J. L. BERGER, Y. THENOZ and D. WOEHRN. First European Solid State Circuits Conference (ESSCIRC), Canterbury p. 119. ~ 5 Sept. 1975. The device studied is an array of 128 CCD registers, each of 64 cells, addressed by 128 cell input and output registers. The registers are controlled by two phases and made of two layers of metallization: the first layer is polycrystalline silicon on thin oxide; the second layer is aluminium on thicker oxide to give unidirectional transfer. Although the array can be used with an electrical input, the characteristics were measured with optical input: after an integration time of 32 msec, the array is emptied line by line at a frequency of 1 MHz.
Relays and Iogis ICs can be working partners. PATRICK M. CRANEY. Electronics p. 107 (Jan. 22 1976). Direct interface of mechanical relays and standard logic families provides economy and power-handling capability for many applications. A 2048-bit n-channel fully decoded electrically writable/ erasable nonvolatile read only memory. M. KIKUCHI, S. OHYA, M. KAMAYA, M. KO1KE and H. YAMAMOTO. First European Solid State Circuits Conference (ESSCIRC), Canterbury p. 66. 2-5 Sept. 1975. In recent years, the advent of microcomputer has greatly increased the demand for electrically programmable read only memories (PROMs). This paper will describe a 2048-bit n-channel fully decoded electrically writable/erasable nonvolatile ROM (EAROM) with novel features. In this device, the memory transistor is a stacked-gate MOS FET and the memory cell consists of two transistors. Memory cells and peripheral circuits are fabricated using n-channel silicon gate technology. Relation between the potential-barrier shape and capacitance -voltage characteristics of MIS structures. A. H. M. SHOUSHA. Solid State Commun. 18, (3) 339 (1976) The relation between the potential-barrier shape and capacitance