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Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
Solid-State Electronics 71 (2012) 106–112
Contents lists available at SciVerse ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques A. Redolfi a,⇑, S. Kubicek a, R. Rooyackers a, M.-S. Kim a, E. Sleeckx a, K. Devriendt a, D. Shamiryan a, T. Vandeweyer a, T. Delande a, N. Horiguchi a, M. Togo a, J.M.D. Wouters a, M. Jurczak a, T. Hoffmann a, A. Cockburn b, V. Gravey b, D.L. Diehl c a b c
imec Belgium, Kapeldreef 75, 3001 Leuven, Belgium Applied Materials Belgium, Kapeldreef 75, 3001 Leuven, Belgium Applied Materials, 974 E. Arques Ave., Sunnyvale, CA 94085, United States
a r t i c l e
i n f o
Article history: Available online 29 November 2011 Keywords: FinFET Bulk FinFET BFFT STI Field recess Siconi Co-fabrication Co-integration
a b s t r a c t This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20 nm wide fins are fabricated using 193 nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300 nm and the electrically active fin height is 40 nm. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction Bulk FinFET (BFFT) devices are gaining the industrial acceptance momentum for the technology of choice for the 22 nm CMOS node and beyond. Tri-gate devices are suitable for logic, analog and memory applications because they have a good short channel effect (SCE) control and transistor compactness [1]. The fabrication of BFFT devices is highly compatible with the existing technologies and can be stacked with the same Through Silicon Vias (TSV)/packaging technology as developed for planar devices. The key integration issue for BFFT is the fin height control. The Siconi™ process, which is able to selectively remove material in a controlled (digital) manner, enables the fin height control. Originally the Siconi™ process is applied as a pre silicide surface clean. In this paper we demonstrate the Siconi™ process as a tool for a plasma-free dry oxide removal to recess the field instead. This new integration sequence is used in a tri-gate FinFET flow to isolate 20 nm wide fins in pitches from 200 nm down to 90 nm and is demonstrated for a 65 nm CMOS technology node co-fabricating BFFT devices with planar FETs. We also show that it is possible to downscale the proposed flow and we discuss the metrology challenges found during the BFFT fabrication. A double hard mask (HM) process is used to ⇑ Corresponding author. E-mail address: redolfi@imec.be (A. Redolfi). 0038-1101/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2011.10.029
pattern the two portions of the device, a straight fin followed by a tapered support pillar. The flow has five major steps: patterning, trench filling, planarization, field recess and fin re-oxidation. 2. Fabrication and results The shallow trench isolation (STI) is integrated in five major steps as indicated in Fig. 1. This figure shows also SEM images of the target device with CD and pitch of 20 and 200 nm, respectively. Patterning is done with double HM and trenches are filled with TEOS/O3 oxide [2], next planarization is achieved with a Chemical Mechanical Polishing (CMP) step with CeO2-slurry followed by an oxide clearing step with a Fixed Abrasive polishing pad. Field recess is done with Siconi™ and the integration is completed with a 2 nm fin re-oxidation. To obtain a high drive current with good SCE control and compactness, the devices are designed as a multi fingered structure. 2.1. Patterning To achieve 20 nm line width or critical dimension (CD) with 193 nm illumination, a series of trimming processes are introduced as indicated in Table 1. Initial lithography CD is 78 nm for 200 nm pitch or 41 nm for 90 nm pitch. During etching we trim resist and hard mask to finish with 35 nm wide fins that are narrowed down
A. Redolfi et al. / Solid-State Electronics 71 (2012) 106–112
Fig. 1. Left: the five main steps of the integration flow. Center: tri-gate transistor tilted SEM after gate patterning. Right: cross-sectional view of a tri-gate device showing the straight patterned fin, the tapered support pillar and the gate wrapping around the electrically active portion of the fin.
to 22 nm during the densification of the trench filling oxide in steam environment. A final CD around 20 nm is achieved after recessing the trench oxide and re-oxidation of the active portion of the fin. To get a straight fin followed by a tapered support pillar we use a double HM process with a-C and silicon nitride deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) followed by a high temperature densification anneal [3,4]. Formation of a nitride overhang is undesirable because it has a negative influence on the trench filling and gate patterning [5]. During the trench etching, the PECVD nitride film exhibits a small lateral loss and the nitride overhang is avoided. The reasoning behind this approach is that the a-C mask can sustain a SF6 based etching chemistry allowing a straight etch profile as shown in Fig. 2-left. A silicon nitride HM is commonly used in STI processes using Cl2/O2 or HBr/O2 etching chemistries to obtain a tapered profile (Fig. 2-center). A combination of the indicated hard-masks and their respective etching chemistries results in the patterning of an adequate structure for a 3D transistor fabrication with a straight profile at the top and a tapered support pillar at the base (Fig. 2-right). Fig. 3 shows a SRAM cell nicely patterned with this process. By optimizing the different etch steps, fins with a CD of 35 nm, a 120 nm straight and 180 nm tapered part (300 nm total trench depth) and covered by 60 nm nitride to act as CMP stop are patterned down to pitches of 90 nm.
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Fig. 2. Left: straight profile obtained with SF6 based chemistry and a SiOC/a-C HM. Center: tapered profile obtained with Cl2/O2 or HBr/O2 chemistry masked by SixNy HM. Right: BFFT structure obtained from the combined HM (SiOC/a-C on SixNy) and a combination of the appropriate etch chemistries (SF6 and HBr/O2).
Fig. 3. A tilted SEM view of a SRAM after etching, showing the narrow fins nicely defined with the proposed process scheme, silicon nitride is still present on top of the fins.
2.2. Trench fill and planarization Void-free trench fill is achieved with TEOS/O3 SACVD targeting 120 nm overfill for the CMP. This process requires a densification anneal in steam ambient that induces 13 nm CD loss due to oxidation of the fin sidewalls constituting the last trimming step. Fin width after trench filling and densification reduced from 35 nm to 22 nm while the etch rate of the filling oxide in HF 2% reduced from 100 nm/min to 20 nm/min. Fig. 4 shows cross-sectional views of the optimized trench filling process after deposition, densification and decoration in HF 2%. Planarization is done with CMP in a two-steps approach to stop on a 60 nm thick nitride mask. The first CMP step uses CeO2-based slurry to allow a self-stopping planarization which is a crucial step in this integration scheme. Oxide overburden and soft-landing are done in a second CMP step with Fixed Abrasive pad (nitride selec-
Fig. 4. Cross section images after trench filling with TEOS/O3 CVD (top); after the high temperature densification (middle) and after decoration in HF 2% (bottom).
Table 1 CD trimming sequence. CD (nm)
After After After After
litho etch fill densification fin re-oxidation
Line/space (nm) Pitch 1: 200 nm
Pitch 2: 90 nm
78/122 35/165 22/178 20/180
41/49 35/55 22/68 20/70
tive chemicals are dispensed on a pad with CeO2 particles incorporated). Precise stop on nitride establishes a reference for the field recess and the control of the fin height uniformity. Because of its high conformability, TEOS/O3 filling causes an oversize of active areas as shown in Fig. 5. This oversize needs compensation at mask design level in order to get a workable CMP process. The spacing between dummy-active areas needs to be increased to compensate
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Fig. 5. Active area oversize observed after TEOS/O3 oxide deposition. This effect is a consequence of the high conformability of this process.
Fig. 7. Sequence of steps done after CMP to adjust the field height. Splitting the field recess in two steps assures that fin walls are protected by oxide during the wet etch back of the silicon nitride in H3PO4.
Table 2 CMP performance.
Mean (nm) Min (nm) Max (nm) Range (nm) r Unif. (%) Before CMP
Oxide left on nitride
Nitride after CMP
Field oxide after CMP
1.6
57.5
352.0
–
53.3
337.7
2.7
59.8
364.2
–
6.5
26.4
–
1.7
0.95
440 nm Rg: 50 nm
60 nm Rg: 0.9 nm r: 0.2%
490 nm Rg: 54 nm r: 2.7%
r: 3.1%
the amount of oversize and to ensure enough topography after trench filling. Table 2 shows post-CMP values obtained for the oxide thickness left on nitride, the nitride thickness and the oxide thickness in the trenches. The data are the average over 23 measurements points per wafer on 23 wafers, inclusive active regions with high and low densities. We observe full clear out of the nitride top with negligible nitride loss in the measurement pads. Cross-section indicates 15 nm loss on narrow fins (Fig. 6). 2.3. Fin height control Fin height is controlled by a sequence of three steps post CMP, called field recess one (FR1), nitride removal and field recess two (FR2). Initially the field oxide is recessed until the level of the nitride bottom. Next, nitride is removed in a hot phosphoric bath (fins are protected by pad and field oxide) and finally the field is recessed until the desired level of fin height is attained. As indicated in Fig. 7 there are two options for the field recess operations, they can be done by wet etch in HF or by dry etch with Siconi™. Using a wet etch process to recess the field oxide within the trenches has the undesirable characteristic of leaving an oxide foot approximately 10–15 nm in height on the fin sidewall (Fig. 8). Additionally, the wet etch step can open voids in the filling oxide material (Fig. 9). Both issues are attributed to local variations in oxide density and consequent variations in wet etch rate (higher
Fig. 8. HF-based field recess shows oxide footing because the sidewall is covered by thermal oxide which etches slower than the field oxide (A). Siconi™ results in reduced footing because this etching technique is less sensitive to oxide density (B).
at the trench centre and lower at sidewalls because the oxide on the sidewalls is thermally grown and denser than the filling CVD oxide). As the Siconi™ oxide removal rate is less dependent on oxide density, integrating it in the process sequence suppresses the foot and the void formation. The Siconi™ process itself is based on a self-stopping reaction for growth and sublimation of ammonium fluorosilicate. This consumes silicon oxide which makes it suitable for surface cleaning applications. To use it as a dry oxide removal process we tuned the cycles for growth and sublimation so that a well controlled amount of oxide (20 nm) is consumed in each cycle. This method gives a digital character to the etch and is more robust than wet etch as it has little dependence on local oxide density variations as observed in highly isotropic wet etching in HF. To define the 40 nm high fins two Siconi™ cycles are used.
2.4. FET/FinFET co-fabrication FET/FinFET co-fabrication is attractive for integration of planar CMOS circuits with SRAMs [6]. For implementation we introduced a double nitride layer, called bottom and top nitride, separated by a 10 nm thin oxide layer deposited just after STI CMP. The top nitride
Fig. 6. Cross-section SEM after CMP. Nitride left on narrow silicon fins is 42 nm and field oxide is 350 nm both on large spaces as well as close to dense structures.
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2.5. Downscaling to 22 nm node and beyond
Fig. 9. Left: Seams in oxide revealed after HF field recess. Right: Clear improvement with dry etch recess.
is patterned to open the FinFET areas and etched selectively to oxide in highly isotropic SF6-based plasma chemistry. At this etching, the FinFETs are covered by the bottom nitride only while the planar FETs are covered by the bottom and the top nitride. After a first field recess that stops at the base of the bottom nitride, a hot-phosphoric bath is used to etch the bottom nitride that protected the FinFET regions during the STI CMP step and the top nitride that protects the planar regions during the first field recess. Next, a second field recess is done to achieve the target topography for the FinFETs and the planar FETs simultaneously (50 nm for FinFETs and flat for planar FETs). To complete the process, the remaining nitride that protected the planar active regions during the STI CMP is removed with hot phosphoric acid (Fig. 10). Fig. 11 shows a tilted SEM image after the high-k metal-gate patterning. The regions with planar FETs and BFFTs are indicated. The IdVg plot in Fig. 11 and Ion Ioff in Fig. 12 indicates that BFFTs fabricated together with planar FETs have similar static performance as that of a BFFT-only flow. Current leakage increase observed for n-FinFET is not attributed to the the co-fabrication process because the extension implantation was not optimized and the short channel effect was degraded. Standard nFET’s received a different and optimized extension implantation, resulting in better static performance.
We believe that 22 nm node Bulk Finfets will arrive to industrial production with dimensions equal or similar to: 10–20 nm line width, 80 nm pitch and depth between 200 and 300 nm. We were able to downscale our fabrication approach to these dimensions by printing SRAMs with a 193 nm immersion scanner targeting 41 nm line width after lithography and 20 nm after trimming with the same approaches as described previously for a 20/180 nm line/ spacing, however trench depth is reduced from 300 to 280 nm. The heights are 100 nm for the straight fin and 180 nm for the tapered pillar. Fig. 13 shows SRAM cells with 90 nm pitch after lithography and after BFFT etch. Fig. 14 shows 80 nm pitch SRAMs processed until field recess two. These results indicate that the integration approach presented in this paper can be downscaled to 22 nm and beyond. Next we present a short discussion about the migration to 22 nm node. The HM stack has the functions of sustaining the trench etching and also of stopping the CMP. HM non-uniformities and/or HM attack during trench etching or CMP may result in undesirable fin height variations after field recess. Some HM stack candidates are a-C deposited on a-Si, a-C deposited on PECVD nitride with high temperature densification or a combination of a Rapid Thermal Chemical Vapor Deposition (RTCVD) nitride deposited from di-silane covered by an a-C layer. In these alternatives, a-C has the function of etching mask and the underlying layer (SiN or a-Si) acts as a CMP stop. We checked uniformity of blanket deposition for these materials by measuring 225 sites per wafer and found that RTCVD nitride may be an interesting choice with only 0.5% r-uniformity, compared to 1.3% for a-Si and 1.5% for PECVD nitride after a densification anneal. Flowable-CVD is a possible alternative for low temperature trench fill, to avoid fin re-oxidation and CD loss. Field recess obtained after many steps as proposed here for the 65 nm node has the drawback of summing up the non-uniformities of each independent step. A single Siconi™ step tuned to remove all layers non-selectively (such as removing pad nitride, pad oxide
Fig. 10. Schematic representation of the co-fabrication scheme. Left: after STI CMP, the deposition of 10 nm oxide and the top nitride and the patterning of the top nitride. Centre: after the first field recess with dry etching (during the 1st field oxide recess, the planar side is protected by the top nitride) and after the removal of the bottom nitride from the FinFETs together with the top nitride that protected the planar FETs during the oxide recess. Right: after the second field recess in HF and the removal of the bottom nitride from the planar FETs.
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Fig. 11. Left: tilted top SEM showing Planar and FinFET regions after gate patterning. Right: correspondent IdVg curves.
Fig. 12. Ion Ioff curves of n- and p-FETs comparing BFFTs of the co-fabrication process (filled symbols) with a BFFT-only flow (open symbols). In both cases a comparable performance is achieved.
Table 3 Comparison of inline measurement techniques. Technique
Pros
Cons
Top SEM CD
Conventional production method
Profilometry
Depth information
Scatterometry CD (SCD)
Can measure many parameters at once, depends on model
Reflections from the bottom of the BFFT makes measurement unstable (we used mainly manual mode) Cannot measure if spacing is too narrow Works only with dense lines and a fixedetch process (not possible during the development phase)
Fig. 13. Top-view of 90 nm pitch SRAM after lithography and after trench etching.
Fig. 14. 80 nm pitch SRAMs after the second field recess. Top left: top view. Top right: tilted view showing the fin walls protruding from the field oxide. Bottom: cross-sectional SEM.
Fig. 15. Top SEM view and signal generated by the automatic CD-SEM tool.
A. Redolfi et al. / Solid-State Electronics 71 (2012) 106–112
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measurement of fin height and width with nanometer scale accuracy without incurring into high-cost techniques such as TEM analysis. We use three techniques: top SEM CD for line width measurements, profilometry for depth measurements and scatterometry for both. These techniques are compared in Table 3. 2.6.1. Top SEM CD Automatic CD measurements are obtained with an algorithm that analyses a top SEM image of a BFFT line as indicated schematically in Fig. 15. Analysis of the derivative of this signal by an ‘‘inside to outside’’ method gives CD information. As observed in this picture the tapered bottom part of the fin generates a large tail (bright part of the image) that will mask the signal from the top of the fin in the case that fins become too narrow. The ‘‘inside to outside’’ algorithm fails and the wide tail leaves no resolution to change the calculation to ‘‘outside to inside’’. We observed this issue for fins narrower than 20 nm (Fig. 16). Fig. 16. Narrow BFFT lines cannot be measured by conventional top SEM CD.
and field oxide at once) is one solution. Overall performance of these materials through a completely integrated Bulk Finfet module is still an open question. 2.6. Metrology for HVM of Bulk FinFETs Accurate and non-destructive high volume manufacture (HVM) metrology for BFFTs is still a challenge. The difficulties refer to the
2.6.2. Profilometry In this technique a probe running over the surface generates a signal that is used to provide depth information such as fin height or trench depth. For the automation Active–Field–Active (AFA) structures with a minimum of 35 lm separation and 45 lm wide levelling pads are needed thus the measurement of steps within narrow trenches is not possible (Fig. 17-left). More complex 3D scans and spaces e.g. 1.8 lm are feasible, however the measurement is time consuming and cannot be done automatically (Fig. 17-right). Automated measurements with a simple line scan show a typical
Fig. 17. Left: AFA structure necessary for the automation of the profilometry measurements. Automation is only possible for wide structures. Right: 3D scans can reveal structures with spaces up to 1.8 lm but cannot measure directly on the fins.
Fig. 18. Model for scatterometry. Six parameters are measured at once: nitride thickness, fin and support height, support angle, bottom and top CD. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
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matching to scatterometry results around 0.7% for 360 nm deep trenches (including silicon and nitride). The measurement of the fin height after field recess in wide structures matches well with Transmission Electron Microscopy (TEM) however it does not give the information on the oxide footing with the consequence that the knowledge about the electrical fin height remains uncertain. 2.6.3. Scatterometry In scatterometry-CD (SCD), an ellipsometry based metrology, compares the scattered spectrum from the pattern with a parametric model, of the pattern, in a library, which is generated and tested before. The number of parameters that can be extracted depends on the complexity of the model and can include CDs as well as thicknesses, step heights and angles. The method works only for dense structures however, 1 lm separated lines also generate a suitable pattern for the measurements while for really isolated lines no suitable scatterometric pattern could be generated. When the patterning parameters change, the model database needs to be re-made. Therefore, this method is not very useful during the development stages. For the HVM of BFFTs it is a very attractive method because it generates all the parameters of interest in just one measurement, as indicated in Fig. 18. 3. Conclusions A BFFT fabrication flow is proposed with the following key integration points: patterning is done with 193 nm lithography and
SiOC/a-C/SixNy HM and three trimming steps are used to target line widths down to 20 nm. CMP is done with a double step in Ceriaslurry and Siconi™ is introduced as a dry-etching process to selectively remove the field oxide without opening seams in the filling material neither creating an oxide foot at the base of the fin. It was also shown that the process can be easily adapted to a flow for the co-fabrication of Planar CMOS and FinFET devices within a single design and that it can be downscaled to fabricate SRAMs with pitches down to 80 nm. Acknowledgments We would like to express sincere thanks to Emma Seppala Durr for sharing her expertise in trench fill and field recess processes, Katti Guruprasad for the computer simulations, the imec 300 mm line for processing support and Applied Materials for advice and demo runs at their site. References [1] [2] [3] [4] [5] [6]
Horiguchi N, et al. SOI Workshop. Kiev, Ukraine; October 2010. Tilke AT, et al. In: IEEE. Adv Semic Manuf Conf; 2006. Shamiryan D et al. Microelectron Eng 2008;86:96–8. Devriendt K, et al. PESM; 2009. Okano K, et al. IEDM; 2005. Kawasaki H, et al. VLSI Symp; 2006.
Contents lists available at SciVerse ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques A. Redolfi a,⇑, S. Kubicek a, R. Rooyackers a, M.-S. Kim a, E. Sleeckx a, K. Devriendt a, D. Shamiryan a, T. Vandeweyer a, T. Delande a, N. Horiguchi a, M. Togo a, J.M.D. Wouters a, M. Jurczak a, T. Hoffmann a, A. Cockburn b, V. Gravey b, D.L. Diehl c a b c
imec Belgium, Kapeldreef 75, 3001 Leuven, Belgium Applied Materials Belgium, Kapeldreef 75, 3001 Leuven, Belgium Applied Materials, 974 E. Arques Ave., Sunnyvale, CA 94085, United States
a r t i c l e
i n f o
Article history: Available online 29 November 2011 Keywords: FinFET Bulk FinFET BFFT STI Field recess Siconi Co-fabrication Co-integration
a b s t r a c t This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20 nm wide fins are fabricated using 193 nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300 nm and the electrically active fin height is 40 nm. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction Bulk FinFET (BFFT) devices are gaining the industrial acceptance momentum for the technology of choice for the 22 nm CMOS node and beyond. Tri-gate devices are suitable for logic, analog and memory applications because they have a good short channel effect (SCE) control and transistor compactness [1]. The fabrication of BFFT devices is highly compatible with the existing technologies and can be stacked with the same Through Silicon Vias (TSV)/packaging technology as developed for planar devices. The key integration issue for BFFT is the fin height control. The Siconi™ process, which is able to selectively remove material in a controlled (digital) manner, enables the fin height control. Originally the Siconi™ process is applied as a pre silicide surface clean. In this paper we demonstrate the Siconi™ process as a tool for a plasma-free dry oxide removal to recess the field instead. This new integration sequence is used in a tri-gate FinFET flow to isolate 20 nm wide fins in pitches from 200 nm down to 90 nm and is demonstrated for a 65 nm CMOS technology node co-fabricating BFFT devices with planar FETs. We also show that it is possible to downscale the proposed flow and we discuss the metrology challenges found during the BFFT fabrication. A double hard mask (HM) process is used to ⇑ Corresponding author. E-mail address: redolfi@imec.be (A. Redolfi). 0038-1101/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2011.10.029
pattern the two portions of the device, a straight fin followed by a tapered support pillar. The flow has five major steps: patterning, trench filling, planarization, field recess and fin re-oxidation. 2. Fabrication and results The shallow trench isolation (STI) is integrated in five major steps as indicated in Fig. 1. This figure shows also SEM images of the target device with CD and pitch of 20 and 200 nm, respectively. Patterning is done with double HM and trenches are filled with TEOS/O3 oxide [2], next planarization is achieved with a Chemical Mechanical Polishing (CMP) step with CeO2-slurry followed by an oxide clearing step with a Fixed Abrasive polishing pad. Field recess is done with Siconi™ and the integration is completed with a 2 nm fin re-oxidation. To obtain a high drive current with good SCE control and compactness, the devices are designed as a multi fingered structure. 2.1. Patterning To achieve 20 nm line width or critical dimension (CD) with 193 nm illumination, a series of trimming processes are introduced as indicated in Table 1. Initial lithography CD is 78 nm for 200 nm pitch or 41 nm for 90 nm pitch. During etching we trim resist and hard mask to finish with 35 nm wide fins that are narrowed down
A. Redolfi et al. / Solid-State Electronics 71 (2012) 106–112
Fig. 1. Left: the five main steps of the integration flow. Center: tri-gate transistor tilted SEM after gate patterning. Right: cross-sectional view of a tri-gate device showing the straight patterned fin, the tapered support pillar and the gate wrapping around the electrically active portion of the fin.
to 22 nm during the densification of the trench filling oxide in steam environment. A final CD around 20 nm is achieved after recessing the trench oxide and re-oxidation of the active portion of the fin. To get a straight fin followed by a tapered support pillar we use a double HM process with a-C and silicon nitride deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) followed by a high temperature densification anneal [3,4]. Formation of a nitride overhang is undesirable because it has a negative influence on the trench filling and gate patterning [5]. During the trench etching, the PECVD nitride film exhibits a small lateral loss and the nitride overhang is avoided. The reasoning behind this approach is that the a-C mask can sustain a SF6 based etching chemistry allowing a straight etch profile as shown in Fig. 2-left. A silicon nitride HM is commonly used in STI processes using Cl2/O2 or HBr/O2 etching chemistries to obtain a tapered profile (Fig. 2-center). A combination of the indicated hard-masks and their respective etching chemistries results in the patterning of an adequate structure for a 3D transistor fabrication with a straight profile at the top and a tapered support pillar at the base (Fig. 2-right). Fig. 3 shows a SRAM cell nicely patterned with this process. By optimizing the different etch steps, fins with a CD of 35 nm, a 120 nm straight and 180 nm tapered part (300 nm total trench depth) and covered by 60 nm nitride to act as CMP stop are patterned down to pitches of 90 nm.
107
Fig. 2. Left: straight profile obtained with SF6 based chemistry and a SiOC/a-C HM. Center: tapered profile obtained with Cl2/O2 or HBr/O2 chemistry masked by SixNy HM. Right: BFFT structure obtained from the combined HM (SiOC/a-C on SixNy) and a combination of the appropriate etch chemistries (SF6 and HBr/O2).
Fig. 3. A tilted SEM view of a SRAM after etching, showing the narrow fins nicely defined with the proposed process scheme, silicon nitride is still present on top of the fins.
2.2. Trench fill and planarization Void-free trench fill is achieved with TEOS/O3 SACVD targeting 120 nm overfill for the CMP. This process requires a densification anneal in steam ambient that induces 13 nm CD loss due to oxidation of the fin sidewalls constituting the last trimming step. Fin width after trench filling and densification reduced from 35 nm to 22 nm while the etch rate of the filling oxide in HF 2% reduced from 100 nm/min to 20 nm/min. Fig. 4 shows cross-sectional views of the optimized trench filling process after deposition, densification and decoration in HF 2%. Planarization is done with CMP in a two-steps approach to stop on a 60 nm thick nitride mask. The first CMP step uses CeO2-based slurry to allow a self-stopping planarization which is a crucial step in this integration scheme. Oxide overburden and soft-landing are done in a second CMP step with Fixed Abrasive pad (nitride selec-
Fig. 4. Cross section images after trench filling with TEOS/O3 CVD (top); after the high temperature densification (middle) and after decoration in HF 2% (bottom).
Table 1 CD trimming sequence. CD (nm)
After After After After
litho etch fill densification fin re-oxidation
Line/space (nm) Pitch 1: 200 nm
Pitch 2: 90 nm
78/122 35/165 22/178 20/180
41/49 35/55 22/68 20/70
tive chemicals are dispensed on a pad with CeO2 particles incorporated). Precise stop on nitride establishes a reference for the field recess and the control of the fin height uniformity. Because of its high conformability, TEOS/O3 filling causes an oversize of active areas as shown in Fig. 5. This oversize needs compensation at mask design level in order to get a workable CMP process. The spacing between dummy-active areas needs to be increased to compensate
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A. Redolfi et al. / Solid-State Electronics 71 (2012) 106–112
Fig. 5. Active area oversize observed after TEOS/O3 oxide deposition. This effect is a consequence of the high conformability of this process.
Fig. 7. Sequence of steps done after CMP to adjust the field height. Splitting the field recess in two steps assures that fin walls are protected by oxide during the wet etch back of the silicon nitride in H3PO4.
Table 2 CMP performance.
Mean (nm) Min (nm) Max (nm) Range (nm) r Unif. (%) Before CMP
Oxide left on nitride
Nitride after CMP
Field oxide after CMP
1.6
57.5
352.0
–
53.3
337.7
2.7
59.8
364.2
–
6.5
26.4
–
1.7
0.95
440 nm Rg: 50 nm
60 nm Rg: 0.9 nm r: 0.2%
490 nm Rg: 54 nm r: 2.7%
r: 3.1%
the amount of oversize and to ensure enough topography after trench filling. Table 2 shows post-CMP values obtained for the oxide thickness left on nitride, the nitride thickness and the oxide thickness in the trenches. The data are the average over 23 measurements points per wafer on 23 wafers, inclusive active regions with high and low densities. We observe full clear out of the nitride top with negligible nitride loss in the measurement pads. Cross-section indicates 15 nm loss on narrow fins (Fig. 6). 2.3. Fin height control Fin height is controlled by a sequence of three steps post CMP, called field recess one (FR1), nitride removal and field recess two (FR2). Initially the field oxide is recessed until the level of the nitride bottom. Next, nitride is removed in a hot phosphoric bath (fins are protected by pad and field oxide) and finally the field is recessed until the desired level of fin height is attained. As indicated in Fig. 7 there are two options for the field recess operations, they can be done by wet etch in HF or by dry etch with Siconi™. Using a wet etch process to recess the field oxide within the trenches has the undesirable characteristic of leaving an oxide foot approximately 10–15 nm in height on the fin sidewall (Fig. 8). Additionally, the wet etch step can open voids in the filling oxide material (Fig. 9). Both issues are attributed to local variations in oxide density and consequent variations in wet etch rate (higher
Fig. 8. HF-based field recess shows oxide footing because the sidewall is covered by thermal oxide which etches slower than the field oxide (A). Siconi™ results in reduced footing because this etching technique is less sensitive to oxide density (B).
at the trench centre and lower at sidewalls because the oxide on the sidewalls is thermally grown and denser than the filling CVD oxide). As the Siconi™ oxide removal rate is less dependent on oxide density, integrating it in the process sequence suppresses the foot and the void formation. The Siconi™ process itself is based on a self-stopping reaction for growth and sublimation of ammonium fluorosilicate. This consumes silicon oxide which makes it suitable for surface cleaning applications. To use it as a dry oxide removal process we tuned the cycles for growth and sublimation so that a well controlled amount of oxide (20 nm) is consumed in each cycle. This method gives a digital character to the etch and is more robust than wet etch as it has little dependence on local oxide density variations as observed in highly isotropic wet etching in HF. To define the 40 nm high fins two Siconi™ cycles are used.
2.4. FET/FinFET co-fabrication FET/FinFET co-fabrication is attractive for integration of planar CMOS circuits with SRAMs [6]. For implementation we introduced a double nitride layer, called bottom and top nitride, separated by a 10 nm thin oxide layer deposited just after STI CMP. The top nitride
Fig. 6. Cross-section SEM after CMP. Nitride left on narrow silicon fins is 42 nm and field oxide is 350 nm both on large spaces as well as close to dense structures.
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2.5. Downscaling to 22 nm node and beyond
Fig. 9. Left: Seams in oxide revealed after HF field recess. Right: Clear improvement with dry etch recess.
is patterned to open the FinFET areas and etched selectively to oxide in highly isotropic SF6-based plasma chemistry. At this etching, the FinFETs are covered by the bottom nitride only while the planar FETs are covered by the bottom and the top nitride. After a first field recess that stops at the base of the bottom nitride, a hot-phosphoric bath is used to etch the bottom nitride that protected the FinFET regions during the STI CMP step and the top nitride that protects the planar regions during the first field recess. Next, a second field recess is done to achieve the target topography for the FinFETs and the planar FETs simultaneously (50 nm for FinFETs and flat for planar FETs). To complete the process, the remaining nitride that protected the planar active regions during the STI CMP is removed with hot phosphoric acid (Fig. 10). Fig. 11 shows a tilted SEM image after the high-k metal-gate patterning. The regions with planar FETs and BFFTs are indicated. The IdVg plot in Fig. 11 and Ion Ioff in Fig. 12 indicates that BFFTs fabricated together with planar FETs have similar static performance as that of a BFFT-only flow. Current leakage increase observed for n-FinFET is not attributed to the the co-fabrication process because the extension implantation was not optimized and the short channel effect was degraded. Standard nFET’s received a different and optimized extension implantation, resulting in better static performance.
We believe that 22 nm node Bulk Finfets will arrive to industrial production with dimensions equal or similar to: 10–20 nm line width, 80 nm pitch and depth between 200 and 300 nm. We were able to downscale our fabrication approach to these dimensions by printing SRAMs with a 193 nm immersion scanner targeting 41 nm line width after lithography and 20 nm after trimming with the same approaches as described previously for a 20/180 nm line/ spacing, however trench depth is reduced from 300 to 280 nm. The heights are 100 nm for the straight fin and 180 nm for the tapered pillar. Fig. 13 shows SRAM cells with 90 nm pitch after lithography and after BFFT etch. Fig. 14 shows 80 nm pitch SRAMs processed until field recess two. These results indicate that the integration approach presented in this paper can be downscaled to 22 nm and beyond. Next we present a short discussion about the migration to 22 nm node. The HM stack has the functions of sustaining the trench etching and also of stopping the CMP. HM non-uniformities and/or HM attack during trench etching or CMP may result in undesirable fin height variations after field recess. Some HM stack candidates are a-C deposited on a-Si, a-C deposited on PECVD nitride with high temperature densification or a combination of a Rapid Thermal Chemical Vapor Deposition (RTCVD) nitride deposited from di-silane covered by an a-C layer. In these alternatives, a-C has the function of etching mask and the underlying layer (SiN or a-Si) acts as a CMP stop. We checked uniformity of blanket deposition for these materials by measuring 225 sites per wafer and found that RTCVD nitride may be an interesting choice with only 0.5% r-uniformity, compared to 1.3% for a-Si and 1.5% for PECVD nitride after a densification anneal. Flowable-CVD is a possible alternative for low temperature trench fill, to avoid fin re-oxidation and CD loss. Field recess obtained after many steps as proposed here for the 65 nm node has the drawback of summing up the non-uniformities of each independent step. A single Siconi™ step tuned to remove all layers non-selectively (such as removing pad nitride, pad oxide
Fig. 10. Schematic representation of the co-fabrication scheme. Left: after STI CMP, the deposition of 10 nm oxide and the top nitride and the patterning of the top nitride. Centre: after the first field recess with dry etching (during the 1st field oxide recess, the planar side is protected by the top nitride) and after the removal of the bottom nitride from the FinFETs together with the top nitride that protected the planar FETs during the oxide recess. Right: after the second field recess in HF and the removal of the bottom nitride from the planar FETs.
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Fig. 11. Left: tilted top SEM showing Planar and FinFET regions after gate patterning. Right: correspondent IdVg curves.
Fig. 12. Ion Ioff curves of n- and p-FETs comparing BFFTs of the co-fabrication process (filled symbols) with a BFFT-only flow (open symbols). In both cases a comparable performance is achieved.
Table 3 Comparison of inline measurement techniques. Technique
Pros
Cons
Top SEM CD
Conventional production method
Profilometry
Depth information
Scatterometry CD (SCD)
Can measure many parameters at once, depends on model
Reflections from the bottom of the BFFT makes measurement unstable (we used mainly manual mode) Cannot measure if spacing is too narrow Works only with dense lines and a fixedetch process (not possible during the development phase)
Fig. 13. Top-view of 90 nm pitch SRAM after lithography and after trench etching.
Fig. 14. 80 nm pitch SRAMs after the second field recess. Top left: top view. Top right: tilted view showing the fin walls protruding from the field oxide. Bottom: cross-sectional SEM.
Fig. 15. Top SEM view and signal generated by the automatic CD-SEM tool.
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measurement of fin height and width with nanometer scale accuracy without incurring into high-cost techniques such as TEM analysis. We use three techniques: top SEM CD for line width measurements, profilometry for depth measurements and scatterometry for both. These techniques are compared in Table 3. 2.6.1. Top SEM CD Automatic CD measurements are obtained with an algorithm that analyses a top SEM image of a BFFT line as indicated schematically in Fig. 15. Analysis of the derivative of this signal by an ‘‘inside to outside’’ method gives CD information. As observed in this picture the tapered bottom part of the fin generates a large tail (bright part of the image) that will mask the signal from the top of the fin in the case that fins become too narrow. The ‘‘inside to outside’’ algorithm fails and the wide tail leaves no resolution to change the calculation to ‘‘outside to inside’’. We observed this issue for fins narrower than 20 nm (Fig. 16). Fig. 16. Narrow BFFT lines cannot be measured by conventional top SEM CD.
and field oxide at once) is one solution. Overall performance of these materials through a completely integrated Bulk Finfet module is still an open question. 2.6. Metrology for HVM of Bulk FinFETs Accurate and non-destructive high volume manufacture (HVM) metrology for BFFTs is still a challenge. The difficulties refer to the
2.6.2. Profilometry In this technique a probe running over the surface generates a signal that is used to provide depth information such as fin height or trench depth. For the automation Active–Field–Active (AFA) structures with a minimum of 35 lm separation and 45 lm wide levelling pads are needed thus the measurement of steps within narrow trenches is not possible (Fig. 17-left). More complex 3D scans and spaces e.g. 1.8 lm are feasible, however the measurement is time consuming and cannot be done automatically (Fig. 17-right). Automated measurements with a simple line scan show a typical
Fig. 17. Left: AFA structure necessary for the automation of the profilometry measurements. Automation is only possible for wide structures. Right: 3D scans can reveal structures with spaces up to 1.8 lm but cannot measure directly on the fins.
Fig. 18. Model for scatterometry. Six parameters are measured at once: nitride thickness, fin and support height, support angle, bottom and top CD. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
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matching to scatterometry results around 0.7% for 360 nm deep trenches (including silicon and nitride). The measurement of the fin height after field recess in wide structures matches well with Transmission Electron Microscopy (TEM) however it does not give the information on the oxide footing with the consequence that the knowledge about the electrical fin height remains uncertain. 2.6.3. Scatterometry In scatterometry-CD (SCD), an ellipsometry based metrology, compares the scattered spectrum from the pattern with a parametric model, of the pattern, in a library, which is generated and tested before. The number of parameters that can be extracted depends on the complexity of the model and can include CDs as well as thicknesses, step heights and angles. The method works only for dense structures however, 1 lm separated lines also generate a suitable pattern for the measurements while for really isolated lines no suitable scatterometric pattern could be generated. When the patterning parameters change, the model database needs to be re-made. Therefore, this method is not very useful during the development stages. For the HVM of BFFTs it is a very attractive method because it generates all the parameters of interest in just one measurement, as indicated in Fig. 18. 3. Conclusions A BFFT fabrication flow is proposed with the following key integration points: patterning is done with 193 nm lithography and
SiOC/a-C/SixNy HM and three trimming steps are used to target line widths down to 20 nm. CMP is done with a double step in Ceriaslurry and Siconi™ is introduced as a dry-etching process to selectively remove the field oxide without opening seams in the filling material neither creating an oxide foot at the base of the fin. It was also shown that the process can be easily adapted to a flow for the co-fabrication of Planar CMOS and FinFET devices within a single design and that it can be downscaled to fabricate SRAMs with pitches down to 80 nm. Acknowledgments We would like to express sincere thanks to Emma Seppala Durr for sharing her expertise in trench fill and field recess processes, Katti Guruprasad for the computer simulations, the imec 300 mm line for processing support and Applied Materials for advice and demo runs at their site. References [1] [2] [3] [4] [5] [6]
Horiguchi N, et al. SOI Workshop. Kiev, Ukraine; October 2010. Tilke AT, et al. In: IEEE. Adv Semic Manuf Conf; 2006. Shamiryan D et al. Microelectron Eng 2008;86:96–8. Devriendt K, et al. PESM; 2009. Okano K, et al. IEDM; 2005. Kawasaki H, et al. VLSI Symp; 2006.