- Email: [email protected]
Cable Vibration Control Supported by SOC Architecture
Cable Vibration Control Supported by SOC Architecture Maciej Rosół*, Krzysztof Kołek** *AGH University of Science and Technology, Institute of Automatics, Al. Mickiewicza 30, 30-059 Kraków, Poland (Tel: +48 12 617 20 97; e-mail: [email protected]). ** AGH University of Science and Technology, Institute of Automatics, Al. Mickiewicza 30, 30-059 Kraków, Poland (Tel: +48 12 617 20 94; e-mail: [email protected]). Abstract: In the paper the System-On-the-Chip (SOC) based on a FPGA circuit is presented to collect input data, perform conditioning and to generate the control signals for the cable system equipped with the MR damper. The FPGA configuration and SOC programming techniques are shown. Experimental results of a semi-active vibration control system controlled by the SOC module are considered. A research is conducted how to mitigate or reduce vibrations by control algorithms. 1. INTRODUCTION SOC is an idea of integrating all components computes or other electronic system into a single integrated circuit. It may contain digital, analog, mixed-signal, and often radiofrequency functions – all on one chip. A typical application is found in the area of embedded systems. There are different technological approaches to implement the SOC systems. One of them is Field Programmable Gate Array circuits (FPGA). It gives a high level of elasticity as the FPGA units may be reconfigured unlimited number of times to find a hardware configuration fitting the requirements. 2. SOC TECHNIQUE The capacity of the FPGA circuits is high enough to implement microprocessors and typical I/O blocks (applied in microprocessor systems) within a single chip (Sapiński et al. 2008). A single FPGA may contain most of the blocks located typically at a system PCB board. The example of a SOC configuration is given in Fig. 1. FPGA
PHY
Serial link
CAN
PHY
uP 16-bit
RAM uP 8-bit
DRAM
Bridge uP 32-bit
DPRAM
Ethernet
Interface
Digital I/O
RAM
A/C C/A
Fig. 1. An example of the SOC configuration
PHY
A single FPGA contains one or more processors, applied to control SOC subsystems. The processors are not implemented as a part of the silicon circuit, but they are defined as a configuration of the FPGA cells. Such processors are called soft-processors. The subsystems may be connected by bridges or by dual-port RAM blocks (DPRAM). The subsystems are equipped with his own processor, may be assigned to specific system tasks. The program and data memory can be either internal RAM blocks or external memories (DRAM). The I/O channels can be either simple digital I/Os or more complex interfaces to A/D and D/A converters. As well the communication channel blocks (IP cores) can be embedded into the FPGA (serial links, Ethernet blocks or CAN network blocks). Outside the FPGA chip the blocks are located that cannot be implemented within the FPGA: EEPROM memory D/A and A/D converters and signal conditioning circuits (PHY). The main advantage of the SOC approach is that the system architecture can be modified according to new requirements. All the I/O blocks can be replaced by new implementations. A number of blocks can be increased and new block types can be added on request. Even each processor can be replaced by a new one. Finally, the most important fact is that the modifications do not require any hardware changes. In the FPGA-based SOC systems each function can be implemented either by a programming way or can be implemented as a dedicated FPGA block. The programming approach requires that a processor executes a sequence of instructions. It is flexible but programs react more slowly comparing to the propagation times of the FPGA cells. The hardware approach requires that signals are processed directly by a piece of FPGA fabric. The combinational blocks and registers are connected to implement the processing algorithm. It consumes much more FPGA resources than the programming approach but may process data even one thousand times faster. The implementation duality gives the opportunity to redesign the programming functions into FPGA hardware blocks if a higher speed is required. The example is a quadrature
incremental encoder block. For the low-resolution encoders the encoder waves can be read and processed by a program. For high-resolution encoders the frequency of the encoder waves may be defined as a few MHz and a dedicated
hardware block is necessary. In the FPGA-based SOC systems such function transfer from the software to hardware implementation is easy and harmless.
Fig. 2. The configuration of the SOC at the FPGA circuit Fig. 2 presents the screen snapshot of the XILINX Platform Studio applied to develop the SOC for the cable plant. The PowerPC 405 processor is used as the CPU. The On-Chip Memory (OCM) blocks are interfaces to the instruction and data memories. The On-Chip Peripheral Bus (OPB) connects peripheral devices to the processor. Timer blocks generate precise sampling time pulses. The general purpose I/O blocks are used as interfaces to A/D and D/A controllers. Simultaneously they act as controllers of analog multiplexer and programmable gain amplifier. The interfaces to the onboard push buttons and the LCD display create a simple user interface. The high speed RS-232 UART enables the SOC to communicate to the PC. This link is used to send commands to the system and to receive the results of experiments. As the real-time platform is applied the Xilkernel environment. Xilkernel is a small modular real-time microkernel dedicated to XILINX embedded SOC systems. The programming language is C. The main features of the Xilkernel are: − − − −
POSIX compatible API functions, two user-selectable scheduling polities: priority based and round-robin, semaphores, mutex, message queues and shared memory synchronisation and inter-process communication methods, user level interrupt handling functions.
The Xilkernel is highly scalable. It can be accommodated to a given system by excluding the unnecessary services. The observed jitter of the Xilkernel timer tasks is less than 600 ns. 3. EXPERIMENTS The schematic diagram of the experimental setup with the suspended cable is shown in Fig. 3 (Sapiński et al. 2006). The measurement-control system is based on a PC with an I/O board installed and supported by software MATLAB/Simulink and RTW/RTWT running on Windows. The system is equipped with the RD-1097-1 damper, a force sensor measuring force acting along the damper axis, laser sensors measuring transverse cable displacements (at the damper fixing point xd and the shaker fixing point xm) and accelerometers measuring transverse cable accelerations at maximally 12 locations. The damper is slide-mounted which enables to investigate its performance at a distance from the support in the range (1, 2.5) m. Force measurements are taken with a strain sensor MEGATRON, series K1100 with measuring range 2 kN. The structure of the control system comprises the Virtex-4 FX12 LC development platform, external A/D converter, power controller, PC running Windows operating system. The Virtex-4 FX12 LC board is directly connected to the system. The displacements at xm and xd are measured by laser sensors connected to the analog inputs of the A/D converter. PWM control signals are generated in the relevant digital outputs of the FPGA chip. These signals regulate the current in the MR damper.
The PC with RS232 port and ISE Foundation Software with Embedded Development Kit running on Windows is used to develop control algorithms and to acquire the experimental data.
the EDK environment (Xilinx 2009). It includes the Xilinx Platform Studio IDE tool as well as all the documentation and IPs that are required for designing Xilinx Platform FPGAs with the embedded PowerPC hard processor.
The VIRTEX-4FX FGPA circuits contain the PowerPC hardware processor applied as the CPU in the SOC system (Kołek et al. 2007). The PowerPC processor runs the XILINX Micro Kernel real-time operating system and is responsible for all measurement and control tasks. The controller is implemented as a single task triggered at a constant sampling period. The SOC system is developed in
The PC and FPGA board are connected by two cables: JTAG and serial. The first one is applied to change the configuration of the FPGA circuit and to download the code for the PowerPC processor. The second link is used during the program execution to send commands to the control system and to receive data acquisition buffers.
Fig. 3. The diagram of the experimental setup
The cable length is L=30 m, cable mass per unit length is mc=1.8 kg/m and the tension force is assumed to be Tc=27 kN. The cable is initially excited manually at the cable midpoint. The damper force is adjusted according to the analog output signal of the power controller. 3.1 Control algorithm The optimal damping coefficient of a viscous damper attached to the cable can be calculated using theoretical analysis of vibrations. An approximate formula to determine the optimal viscous damping coefficient copt for the damper attached to the cable at a small distance from the support is given by Krenk (Krenk 2000): n c opt =
1 L nπ x d
Tc m c
(1)
where: n is the mode number, xd is the distance of the damper from the support (Handle 1 on Fig. 3), L is the cable length, Tc is the cable tension and mc is the cable mass per unit length.
The idea of the algorithm proposed for semi-active friction devices was introduced by Inaudi (Inaudi 1997) and next applied for vibration control in cables (Maślanka 2007, Weber et al. 2007 and Zhou et al. 2006). The current for the MR damper is calculated by the following formula (Sapiński et al. 2008):
i=
n πϖAd (copt − C4 ) − 4C2 4C1 + πϖAd C3
where: C1 − C 4 are parameters of the system, ϖ
(2) is the
circular frequency of the current mode and Ad is the amplitude measured and calculated in the period to period steps. The similar approach has been published in the (Weber et al. 2009). The following parameters are identified:
C1 = 62 , C2 = 1.5 , C3 = 48 ,
C4 = 14 and
ϖ = 2.08 * 2π for the first mode. The algorithm is implemented as C-language program. 3.2 Experimental results The following four figures illustrate the selected results of the control experiments. The experimental results are obtained for controlled friction damping according to formula (2) (the Inaudi approach). The presented data are divided into three phases: swinging-up (the cable is excited), free vibration (the cable executed a free vibrations) and controlled vibration (the controller is switched-on). The moments at which the free vibration and controlled phases are started are indicated in the graphs. Fig. 5. Displacement at the MR damper fixing-point
Fig. 4. Cable displacement at the mid-point Fig.4 shows the displacement of the mid-point of the cable (xm = 15 m distance from the support). The first 8.5 seconds of the experiment shows the cable swinging-up phase. Next the free vibrations (8.5 s – 45.5 s) and the controlled vibration (>45.5 s) phases are observed. One can notice the influence of the controller to the damping of the oscillations. During the free vibrations phase the damper force decays exponentially due to the linear behavior of the cable damper system. Fig. 5 presents similar displacement data for the MR damper fixing point xd = 1.1 m. It is apparent that cable vibration decays much faster in the case of the controlled vibration phase. Fig. 6 presents the current in the MR damper coil. The current is calculated all the time but only during the controlled vibration phase it acts the MR damper (from 0 s – 45.5 s the MR current is set to zero). Figure 7 shows the respective force generated by the MR damper. From the start time point of the experiment to 45.5 s the MR damper works as a passive one with current equal to 0.0 A. Obviously the maximum force value is achieved for the maximum displacement amplitude.
Fig. 6. Current at the MR damper coil
Fig. 7. Damping force of the MR damper Fig 8 presents force vs. displacement characteristics. One can observe that the force is proportional to the amplitude of the
vibrations (in fact, due to the nature of the MR damper, it is proportional to the velocity).
Fig. 8. Damping force vs. piston displacement of the MR damper 6. CONCLUSIONS The application of the controller as a part of an FPGA circuit consists of two stages. The first one establishes hardware configuration. The unique feature of the FPGA approach is that the hardware configuration is developed just by clicking a mouse. A new configuration is just downloaded to the target FPGA circuit. The second stage is more classical. Its aim is to develop a program that interacts with the FPGA blocks (device drivers) and performs measurements and realtime control tasks. The hardware reconfiguration is nearly as flexible as programming design in a classical programming language. The system can be extended by a new type of measurements (for example sigma-delta A/Ds) or by a new type of communication channels (for example Ethernet or industrial networks like CAN). The most important is that such significant configuration changes require only minor hardware changes. It must look very promising if applied to develop control applications, where a wide range of control configurations, sensors and actuators is used. REFERENCES Inaudi J.A. (1997), Modulated homogeneous friction: a semiactive damping strategy. Earthquake Engineering and Structural Dynamics, 26, pp. 361–376. Kołek K., Rosół M. and Other (2007), FPGA Technology in an MR Damper Control of Mechanical System Vibration, 8th Conference on Active Noise and Vibration Control Methods, Krasiczyn-Poland, June 11-14, pp. 496-504. Krenk S. (2000), Vibrations of a taut cable with an external damper, Journal of Applied Mechanics, 67, pp. 772–776. Maślanka M. (2007), Free vibrations of a cable with an attached MR damper -experimental analysis of amplitude dependent damping. Proceedings of the 7th International Symposium on Cable Dynamics, Vienna, Austria, pp. 415–422.
Sapiński B., Snamina J. and Other (2006), Facility for testing of magnetorheological damping systems for cable vibrations, Mechanics. AGH University of Science and Technology Press, 25(3), pp. 135–142. Sapiński B. /editor/ (2008), Real-Time Control of Magnetorheological Dampers in Mechanical Systems, AGH University of Science and technology Press, Cracow, pp. 68-70. Weber F., Distl H. and Feltrin G. (2007), Damping of stay cables by controlled friction type dampers. Proceedings of the 7th International Symposium on Cable Dynamics, Vienna, Austria, December 10-13, pp. 271–278. Weber F., Distl H., Feltrin G and Motavalli M. (2009), Cycle energy control of MR dampers on cables, Journal of Smart Materials and Structures, 18(1), 015005, (16pp). Zhou Q., Nielsen S.R.K. and Qu W.L. (2006), Semi-active control of three-dimensional vibrations of an inclined sag cable with magnetorheological dampers. Journal of Sound and Vibration, 296, pp. 1–22. Xilinx Corp. (2009), Platform Studio and EDK Documentation, http://www.xilinx.com/ise/embedded/ edk_docs.htm.
PHY
Serial link
CAN
PHY
uP 16-bit
RAM uP 8-bit
DRAM
Bridge uP 32-bit
DPRAM
Ethernet
Interface
Digital I/O
RAM
A/C C/A
Fig. 1. An example of the SOC configuration
PHY
A single FPGA contains one or more processors, applied to control SOC subsystems. The processors are not implemented as a part of the silicon circuit, but they are defined as a configuration of the FPGA cells. Such processors are called soft-processors. The subsystems may be connected by bridges or by dual-port RAM blocks (DPRAM). The subsystems are equipped with his own processor, may be assigned to specific system tasks. The program and data memory can be either internal RAM blocks or external memories (DRAM). The I/O channels can be either simple digital I/Os or more complex interfaces to A/D and D/A converters. As well the communication channel blocks (IP cores) can be embedded into the FPGA (serial links, Ethernet blocks or CAN network blocks). Outside the FPGA chip the blocks are located that cannot be implemented within the FPGA: EEPROM memory D/A and A/D converters and signal conditioning circuits (PHY). The main advantage of the SOC approach is that the system architecture can be modified according to new requirements. All the I/O blocks can be replaced by new implementations. A number of blocks can be increased and new block types can be added on request. Even each processor can be replaced by a new one. Finally, the most important fact is that the modifications do not require any hardware changes. In the FPGA-based SOC systems each function can be implemented either by a programming way or can be implemented as a dedicated FPGA block. The programming approach requires that a processor executes a sequence of instructions. It is flexible but programs react more slowly comparing to the propagation times of the FPGA cells. The hardware approach requires that signals are processed directly by a piece of FPGA fabric. The combinational blocks and registers are connected to implement the processing algorithm. It consumes much more FPGA resources than the programming approach but may process data even one thousand times faster. The implementation duality gives the opportunity to redesign the programming functions into FPGA hardware blocks if a higher speed is required. The example is a quadrature
incremental encoder block. For the low-resolution encoders the encoder waves can be read and processed by a program. For high-resolution encoders the frequency of the encoder waves may be defined as a few MHz and a dedicated
hardware block is necessary. In the FPGA-based SOC systems such function transfer from the software to hardware implementation is easy and harmless.
Fig. 2. The configuration of the SOC at the FPGA circuit Fig. 2 presents the screen snapshot of the XILINX Platform Studio applied to develop the SOC for the cable plant. The PowerPC 405 processor is used as the CPU. The On-Chip Memory (OCM) blocks are interfaces to the instruction and data memories. The On-Chip Peripheral Bus (OPB) connects peripheral devices to the processor. Timer blocks generate precise sampling time pulses. The general purpose I/O blocks are used as interfaces to A/D and D/A controllers. Simultaneously they act as controllers of analog multiplexer and programmable gain amplifier. The interfaces to the onboard push buttons and the LCD display create a simple user interface. The high speed RS-232 UART enables the SOC to communicate to the PC. This link is used to send commands to the system and to receive the results of experiments. As the real-time platform is applied the Xilkernel environment. Xilkernel is a small modular real-time microkernel dedicated to XILINX embedded SOC systems. The programming language is C. The main features of the Xilkernel are: − − − −
POSIX compatible API functions, two user-selectable scheduling polities: priority based and round-robin, semaphores, mutex, message queues and shared memory synchronisation and inter-process communication methods, user level interrupt handling functions.
The Xilkernel is highly scalable. It can be accommodated to a given system by excluding the unnecessary services. The observed jitter of the Xilkernel timer tasks is less than 600 ns. 3. EXPERIMENTS The schematic diagram of the experimental setup with the suspended cable is shown in Fig. 3 (Sapiński et al. 2006). The measurement-control system is based on a PC with an I/O board installed and supported by software MATLAB/Simulink and RTW/RTWT running on Windows. The system is equipped with the RD-1097-1 damper, a force sensor measuring force acting along the damper axis, laser sensors measuring transverse cable displacements (at the damper fixing point xd and the shaker fixing point xm) and accelerometers measuring transverse cable accelerations at maximally 12 locations. The damper is slide-mounted which enables to investigate its performance at a distance from the support in the range (1, 2.5) m. Force measurements are taken with a strain sensor MEGATRON, series K1100 with measuring range 2 kN. The structure of the control system comprises the Virtex-4 FX12 LC development platform, external A/D converter, power controller, PC running Windows operating system. The Virtex-4 FX12 LC board is directly connected to the system. The displacements at xm and xd are measured by laser sensors connected to the analog inputs of the A/D converter. PWM control signals are generated in the relevant digital outputs of the FPGA chip. These signals regulate the current in the MR damper.
The PC with RS232 port and ISE Foundation Software with Embedded Development Kit running on Windows is used to develop control algorithms and to acquire the experimental data.
the EDK environment (Xilinx 2009). It includes the Xilinx Platform Studio IDE tool as well as all the documentation and IPs that are required for designing Xilinx Platform FPGAs with the embedded PowerPC hard processor.
The VIRTEX-4FX FGPA circuits contain the PowerPC hardware processor applied as the CPU in the SOC system (Kołek et al. 2007). The PowerPC processor runs the XILINX Micro Kernel real-time operating system and is responsible for all measurement and control tasks. The controller is implemented as a single task triggered at a constant sampling period. The SOC system is developed in
The PC and FPGA board are connected by two cables: JTAG and serial. The first one is applied to change the configuration of the FPGA circuit and to download the code for the PowerPC processor. The second link is used during the program execution to send commands to the control system and to receive data acquisition buffers.
Fig. 3. The diagram of the experimental setup
The cable length is L=30 m, cable mass per unit length is mc=1.8 kg/m and the tension force is assumed to be Tc=27 kN. The cable is initially excited manually at the cable midpoint. The damper force is adjusted according to the analog output signal of the power controller. 3.1 Control algorithm The optimal damping coefficient of a viscous damper attached to the cable can be calculated using theoretical analysis of vibrations. An approximate formula to determine the optimal viscous damping coefficient copt for the damper attached to the cable at a small distance from the support is given by Krenk (Krenk 2000): n c opt =
1 L nπ x d
Tc m c
(1)
where: n is the mode number, xd is the distance of the damper from the support (Handle 1 on Fig. 3), L is the cable length, Tc is the cable tension and mc is the cable mass per unit length.
The idea of the algorithm proposed for semi-active friction devices was introduced by Inaudi (Inaudi 1997) and next applied for vibration control in cables (Maślanka 2007, Weber et al. 2007 and Zhou et al. 2006). The current for the MR damper is calculated by the following formula (Sapiński et al. 2008):
i=
n πϖAd (copt − C4 ) − 4C2 4C1 + πϖAd C3
where: C1 − C 4 are parameters of the system, ϖ
(2) is the
circular frequency of the current mode and Ad is the amplitude measured and calculated in the period to period steps. The similar approach has been published in the (Weber et al. 2009). The following parameters are identified:
C1 = 62 , C2 = 1.5 , C3 = 48 ,
C4 = 14 and
ϖ = 2.08 * 2π for the first mode. The algorithm is implemented as C-language program. 3.2 Experimental results The following four figures illustrate the selected results of the control experiments. The experimental results are obtained for controlled friction damping according to formula (2) (the Inaudi approach). The presented data are divided into three phases: swinging-up (the cable is excited), free vibration (the cable executed a free vibrations) and controlled vibration (the controller is switched-on). The moments at which the free vibration and controlled phases are started are indicated in the graphs. Fig. 5. Displacement at the MR damper fixing-point
Fig. 4. Cable displacement at the mid-point Fig.4 shows the displacement of the mid-point of the cable (xm = 15 m distance from the support). The first 8.5 seconds of the experiment shows the cable swinging-up phase. Next the free vibrations (8.5 s – 45.5 s) and the controlled vibration (>45.5 s) phases are observed. One can notice the influence of the controller to the damping of the oscillations. During the free vibrations phase the damper force decays exponentially due to the linear behavior of the cable damper system. Fig. 5 presents similar displacement data for the MR damper fixing point xd = 1.1 m. It is apparent that cable vibration decays much faster in the case of the controlled vibration phase. Fig. 6 presents the current in the MR damper coil. The current is calculated all the time but only during the controlled vibration phase it acts the MR damper (from 0 s – 45.5 s the MR current is set to zero). Figure 7 shows the respective force generated by the MR damper. From the start time point of the experiment to 45.5 s the MR damper works as a passive one with current equal to 0.0 A. Obviously the maximum force value is achieved for the maximum displacement amplitude.
Fig. 6. Current at the MR damper coil
Fig. 7. Damping force of the MR damper Fig 8 presents force vs. displacement characteristics. One can observe that the force is proportional to the amplitude of the
vibrations (in fact, due to the nature of the MR damper, it is proportional to the velocity).
Fig. 8. Damping force vs. piston displacement of the MR damper 6. CONCLUSIONS The application of the controller as a part of an FPGA circuit consists of two stages. The first one establishes hardware configuration. The unique feature of the FPGA approach is that the hardware configuration is developed just by clicking a mouse. A new configuration is just downloaded to the target FPGA circuit. The second stage is more classical. Its aim is to develop a program that interacts with the FPGA blocks (device drivers) and performs measurements and realtime control tasks. The hardware reconfiguration is nearly as flexible as programming design in a classical programming language. The system can be extended by a new type of measurements (for example sigma-delta A/Ds) or by a new type of communication channels (for example Ethernet or industrial networks like CAN). The most important is that such significant configuration changes require only minor hardware changes. It must look very promising if applied to develop control applications, where a wide range of control configurations, sensors and actuators is used. REFERENCES Inaudi J.A. (1997), Modulated homogeneous friction: a semiactive damping strategy. Earthquake Engineering and Structural Dynamics, 26, pp. 361–376. Kołek K., Rosół M. and Other (2007), FPGA Technology in an MR Damper Control of Mechanical System Vibration, 8th Conference on Active Noise and Vibration Control Methods, Krasiczyn-Poland, June 11-14, pp. 496-504. Krenk S. (2000), Vibrations of a taut cable with an external damper, Journal of Applied Mechanics, 67, pp. 772–776. Maślanka M. (2007), Free vibrations of a cable with an attached MR damper -experimental analysis of amplitude dependent damping. Proceedings of the 7th International Symposium on Cable Dynamics, Vienna, Austria, pp. 415–422.
Sapiński B., Snamina J. and Other (2006), Facility for testing of magnetorheological damping systems for cable vibrations, Mechanics. AGH University of Science and Technology Press, 25(3), pp. 135–142. Sapiński B. /editor/ (2008), Real-Time Control of Magnetorheological Dampers in Mechanical Systems, AGH University of Science and technology Press, Cracow, pp. 68-70. Weber F., Distl H. and Feltrin G. (2007), Damping of stay cables by controlled friction type dampers. Proceedings of the 7th International Symposium on Cable Dynamics, Vienna, Austria, December 10-13, pp. 271–278. Weber F., Distl H., Feltrin G and Motavalli M. (2009), Cycle energy control of MR dampers on cables, Journal of Smart Materials and Structures, 18(1), 015005, (16pp). Zhou Q., Nielsen S.R.K. and Qu W.L. (2006), Semi-active control of three-dimensional vibrations of an inclined sag cable with magnetorheological dampers. Journal of Sound and Vibration, 296, pp. 1–22. Xilinx Corp. (2009), Platform Studio and EDK Documentation, http://www.xilinx.com/ise/embedded/ edk_docs.htm.