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Capacitance voltage measurements on n-type InAs MOS diodes
CAPACITANCE VOLTAGE MEASUREMENTS N-TYPE InAs MOS DIODES* School
ON
R. J. SCHWARTZ, R. C. DOCKERTY and H. W. THOMPSON, JR. of Electrical Engineering, Purdue University, Lafayette, Indiana 47907. U.S.A. (Received
27 February
1970; in revisedform
3 August
1970)
Abstract-The electrical properties of the interface between pyrolytically deposited SiO, and InAs have been investigated by measuring the admittance of Al-SiO,-InAs MOS diodes at room temperature and 77°K. The room temperature measurements yield a rather high surface state density of 2.5 x lOI states/eV/cm’. The surface state density undergoes an anomalous decrease to 2.8 X 10” states/eV/cm2 at 77°K. A charge which is linearly dependent on the voltage across the oxide is trapped in the oxide. Conduction through the oxide causes the diodes to enter a deep depletion condition at 77°K. R&me-Les propriCtts tlectriques de l’interface entre le SiO, et le InAs pyrolytiquement dCposCs ont CtC ktudites en mesurant I’admission de diodes Al-SiO,-InAs MOS B tempkrature ambiante et B 77°K. Les mesures prises 21 tempkrature ambiante produisent une densitt d’Ctat de surface plut6t 6levCe de 23 X lOI* &ats/eV/cm*. La densit d’ttat de surface subit un dtcroissement anomal jusqu’8 2,8 X 1OL1 Ctats/eV/cmz B 77°K. Une charge qui est fonction IinCaire de la tension B travers I’oxyde est prisonnibe dans I’oxyde. La conduction $ travers l’oxyde est la cause d’une forte condition d’Cpuisement des tlectrodes B 77°K. ZusammenfassungDurch Messung der Admittanz von Al-SiO,-InAs-MOS-Dioden bei Raumtemperatur und bei 77 K wurden die elektrischen Eigenschaften der GrenztWhe zwischen pyrolytisch abgeschiedenem SiO, und InAs untersucht. Die Zimmertemperaturwerte lieferten eine ziemlich hohe Dichte von 23. 10’2/eV cm* fir die OberflfchenzustBnde. Diese unterliegt einer abnormal groRen Abnahme auf 2,8. IO”/eV cm* bei 77 K. Eine linear vom Spannungsabfall iiber das Oxyd abhLngige Ladune. ist im Oxvd lokalisiert. Die Leitune durch das Oxvd fiihrt bei 77 K zu einer starken Verarmungsz&e in den dioden
QSC charge within the semiconductor QdOlc voltage dependent charge within the oxide YS, surface state admittance/A
NOTATION
electrode area capacitance of MOS diode capture probability for electrons oxide capacitance oxide capacitance/A semiconductor capacitance surface state capacitance oxide thickness average field in the oxide intrinsic carrier concentration fast surface state density magnitude of the electronic charge equivalent fixed charge in the oxide equivalent fixed charge in the oxide/A charge in fast surface states gate voltage (measured with reference semiconductor bulk) voltage across the oxide surface potential of the semiconductor “This work supported Project Agency.
in part by NASA
AV
7
6J
difference between measured gate voltage and gate voltage calculated in the absence of oxide charge permittivity of free space relative dielectric constant of the SO, Fermi energy in the bulk (in units of kT) mid-gap energy at the semiconductor surface (in units of kT) surface state time constant metal semiconductor work function difference angular frequency INTRODUCTION
to the
Institutional
METAL-insulator-semiconductor structures have been extensively employed to study the surface properties of silicon[l-31, and to a lesser extent, Grant 115
No. NCR-1
S-005-021
and the Advanced
Research
116
R. J. SCHWARTZ.
R. C. DOCKERTY
gallium arsenide[4]. Much of the motivation for these studies has come from the fact that field effect transistor performance is strongly dependent upon the properties of the semiconductor surface. The number and frequency response of the surface states at the insulator-semiconductor boundary can have a dominant effect on the performance of an insulated gate field effect transistor. Relatively little information is available about the surface properties of other potentially useful semiconductors such as InAs. While Kunig[S] has reported on the fabrication of thin film SiO,-InAs transistors with field effect mobilities as high as 7SOOcm”/ Vsec, there have been no reports on the electrical properties of the surface states which exist at an SiO,-InAs interface. This investigation is a study of the SiO,-InAs interface of an MOS structure such as is shown in Fig. I. In the course of this investigation we have found that the surface states which exist at a deposited SiO,-single crystal InAs interface are extremely fast (all states respond at 20 MHL at room temperature). The investigation also revealed that electrical charge was trapped in the oxide at a rate which was linearly proportional to the voltage applied across the oxide. This voltage dependent oxide trapping, as well as hysteresis effects and low temperature deep depletion effects, are attributed to electrical leakage through the oxide.
FIG. 1. Metal-oxide-semiconductor
structure.
EXPERIMENTAL PROCEDURE Sample
preprrrution
Czochralski grown, single crystal, rl-type indium arsenide was used throughout this study. The IZtype wafers were not intentionally doped. The doping level was 2.2 x 10’” atoms/en? for all samples reported below. After mechanical polishing. the indium arsenide wafers were cleaned in a succession of organic solvent rinses. Immediately prior to the insulation deposition, the wafers were given a further chemical cleaning and were then etched in a 2% bromine in methanol solution for one minute. This was followed by successive rinses
and H. W. THOMPSON,
JR
in methanol, trichloroethylene, and isopropyl alcohol. The bromine etch was found to polish the (I IO) and (100) faces. but resulted in pitting of the (I IIA) and( I I IB) faces. Because of this pitting only the (100) and (I 10) surfaces were used to fabricate the SiO,-MOS capacitors. SiO: was deposited to a thickness of l2002000 A on the surface of the InAs by means of the reaction between SiH., and O,, using the technique described by Goldsmith and Kern[6]. The substrate temperature was maintained at 400°C during deposition of the SiO, layer. Oxide thickness could be estimated during deposition from the interference colors. The thickness was later verified by the use of step etching and multiple beam interferometer techniques. Oxide layers deposited in this manner were uniform in thickness over the central region of the wafer with a decrease in thickness of up to 25% at the edges. All measurements were confined to regions of uniform thickness. Vacuum evaporated 5-9’s aluminum was used as a gate electrode. Geometry definition wab obtained either by the use of photolithographic techniques or by evaporation through beryllium-copper masks. The metal contact area was 2.5 x IO-:’ cmz. Electrical contact to the InAs substrate was made by means of large area conductive silver epoxy contacts. This procedure was found to yield low resistance ohmic contact to the bulk InAs. The series resistance was low enough at both room temperaiure and at 77°K such that there was no Ggnificant ePiect on the measured value of the diode capacitance at frequencies as high as 20 MHz. Several wafers were annealed immediately after the oxide was deposited. In these cases, the InAs wafer was cut in half after the oxide deposition, and one half was retained for measurement, while the other half was annealed and then measured. Annealing was carried out at 4OO”C-600°C’ in quartL tubes with either oxygen or nitrogen flowing over the sample throughout the anneal. The effects of high fields applied at elevated temperatures (B-7‘ stress) were studied by applying electric fields of LIP to 4 X IO” V/cm to the oxide while maintaining the sample at 115°C‘. Throughout this discussion the polarity of the voltage applied to the metal electrode is specified with reference to the semi-conductor bulk. Admittance measurements of the structure shown in Fig. I were made at I and IO kHr using a General Kadio I6 I 5-A capacitance bridge. while
MEASUREMENTS
ON
N-TYPE
a Boonton Model 74C-S8 capacitance bridge was used at 100 KHz, and a Boonton Model 33A r-f admittance bridge was used at 1,5,10 and 20 MHz. Measurements were performed at room temperature and 77°K. In all cases, the a.c. signal was maintained at a level which was sufficiently small so that the problems associated with harmonic generation were avoided. Measurements were performed in the dark unless specified otherwise. EXPERIMENTAL
InAs
MOS
117
DIODES c IPFI 80
L
RESULTS
A typical capacitance-voltage (C-V) curve for an Al-SiO,-InAs diode is shown in Fig. 2. The data from which Fig. 2 was plotted was taken sufficiently slowly (approximately 30 seconds delay after a change in bias voltage) that a stable value of capacitance was obtained at each value of bias voltage. The entire curve was traversed in this manner. The hysteresis exhibited by this curve is typical of measurements at both room temperature and 77°K. Clockwise traversal of the hysteresis loop, such as is shown in Fig. 2, is indicative of hole or electron trapping in the oxide [7]. Two experiments were performed which tend to confirm the presence of electron trapping in the insulator. In the first experiment, the amount of hysteresis was measured as a function of the magnitude of the maximum negative bias applied to the gate. The hysteresis increased as the maximum negative gate bias increased in accordance with both the trapping model of Hofstein and Warfield [8] and the conduction model of Hu et al.[7]. The effect is similar to that reported by Deal et al.[2] for silane deposited SiO, on silicon. In the second experiment, a sample was subjected to various negative bias-temperature (B-T) stresses between C-V measurements. The results of this experiment are shown in Fig. 3. Only the C-V data obtained by varying the bias voltage from positive to negative values are shown. The first application of 2.5 X lo6 V/cm for 1.75 hr at I 15°C produced a pronounced shift in the curve toward positive bias values (Curve B, Fig. 3). Such a shift is indicative of positive ion motion in the oxide. Similar shifts in SiO,-Si structures have been found to be due to the migration of sodium ions toward the gate electrode during B-T stress. A second application of B-T stress, this time at 3.3 X 10’ V/cm and 115°C for 1-75 hr, resulted in a partial reversal of the previous shift (Curve C, Fig. 3). Further B-T stress (3.3 X lo6 V/cm, 1lS”C,
Fig.
2. Hysteresis in the C-V measurements all samples at 295°K and 77°K.
Fig. 3. The effect of bias-temperature capacitance.
stress
typical
of
on the MOS
for 5.5 hr) produced a continued shift in the C-V curve toward negative bias (Curve D, Fig. 3). The observed shift of the C-V curve toward negative bias after the application of a strong negative bias is consistent with emission of electrons from oxide traps into the semiconductor. When a strong negative bias was applied to the metal of a previously unstressed diode at 77”K, only the shift toward more negative bias values was observed, indicating that the electronic process was dominant at low temperatures. Figures 4 and 5 show the dependence of the capacitance of the Al-SiO,-InAs structure upon bias voltage at 295°K and 77°K for the (110) surface. The data of Figs. 4 and 5 were taken on the same sample. Similar results were obtained on the (100) surfaces. Theoretical curves for the case where there is no oxide charge and no surface states are also shown for comparison (Curve B). At both 77°K and room temperature the experi-
118
R. J. SCHWARTZ,
R. C. DOCKERTY
and
H. W. THOMPSON.
JR
N , ss x2.46 X 10’2states/ev/cme Ofix=2.5X 10’Oel. charge/cm* 0 slow=o~*75
Nss=2A6X10’t Oiix = 0
states/ev/crn OE
%lOW =0
0 Measured Valuer f=20 MHz T= 295” K Cox= 120.7 pF
InAs
0.E
Surface
0.7
Nss= I
QSIOW =0
________________________Q~ 8 0.E
--+-AFig. 4. Experimental and theoretical values of the capacitance function of the bias voltage at 295°K.
as a
mental C-V curves are displaced from the theoretical in the direction of negative bias. In addition, the transition from maximum capacitance to minimum capacitance is spread over an extremely wide voltage range. At room temperature the capacitance is constant for large negative voltages while at 77°K the capacitance was observed to continue to decrease with increasing negative voltage until the breakdown voltage of the oxide was reached. Room temperature capacitance measurements are independent of frequency between
Iexp c,ni where trinsic
(K-P~,)
(1)
c,, is the capture probability. IQ is the incarrier concentration and (P*..~-pcLH) is the
MEASUREMENTS
ON N-TYPE
119
InAs MOS DIODES
0 Measured Values
< IlO>
ve
InAs
Surface
(Volts)
Fig. 5. Experimental and theoretical values of the capacitance as a function of bias voltage, for the same diode as shown in Fig. 4, at 77°K. difference between the mid-gap energy and the Fermi level at the surface in units of kT. If the capture probabilities are comparable for SiO,-Si and InAs-SiO, interfaces, then the time constant r will be approximately 10e4 that of silicon for a comparable ( ps - pB) because of the fact that the intrinsic carrier concentration of InAs is IO4 as large as that of silicon. There is of course no assurance that the capture probabilities will be similar for SiO,-Si and SiO,-InAs interfaces. In each case, as the bias voltage was changed, 2-10 set were required before the capacitance reached a constant value. The observed drift in the measured capacitance was toward increasing values of capacitance after the bias was changed from one value to a more negative value.
The effects of annealing in nitrogen and oxygen are shown in Figs. 7 and 8. In each case the primary effect of the anneal was to cause a decrease in the oxide capacitance, as long as the annealing temperature was held below 600°C. A similar decrease in the oxide capacitance was observed by Goldsmith and Kern[6] when SiO,, deposited at 325°C on silicon, was heat treated in argon at 770°C for I2 min. The change appears to be attributable to a decrease in the SiO, dielectric constant. At an annealing temperature of 600°C in an oxygen ambient, the surface state density increases to the point where C became independent of gate bias. A typical conductance curve for G-V measurements, measured at 10 MHz, is shown in Fig. 9. AS can be seen in Fig. 9, a well defined peak
120
R. J. SCHWARTZ,
I -40
,
I
Fig.
6. Capacitance
and
H. W. THOMPSON,
JR.
,
0
-20
“Q
R. C. DOCKERTY
~“Olll,
dispersion
curves
for SiO,
on the
(110) surface of InAs at 77°K. Fig. 9. MOS conductance
for the diode of Fig. 4.
occurred in the conductance measurements at 77°K. No peaks were observed for conductance measurements performed at room temperature. The behavior of the (100) and the (1 IO) surfaces were found to be similar for all measurements. DISCUSSION It is not possible
Fig. 7. The effect
of a 2 hr anneal atmosphere.
at 410°C in a nitrogen
Fig. 8. The effect of a 2 hr anneal atmosphere.
at 400°C in an oxygen
to explain both the very large negative shift (AP’) of the C-V curves and the extremely wide C,,, to Cmin transition region shown in Figs. 4 and 5 through the usual fixed oxide charge and fast surface states model. If fast surface states were present in sufficient numbers to yield a transition region as broad as that which is observed, the capacitance associated with these states would be so large that it would effectively mask the capacitance modulation with bias. The usual procedure for determining the fast surface state density involves a measurement of the capacitance at a frequency which is sufficiently high that none of the surface states can respond. The voltage difference between the measured and calculated value is then used to compute the amount of surface charge. The use of this technique was not possible in this study as the presence of a series resistance of approximately 1.5 ohms at room temperature limited the highest frequency at which reliable capacitance measurements could be made to 20 MHz. As has been noted above, no dispersion was observed up to 20 MHz at room temperature so a true “high frequency curve” could not be obtained. At 77°K
MEASUREMENTS
ON N-TYPE
dispersion was observed but some surface states appear to be responding even at 20 MHz. Two different techniques were utilized to estimate the fast surface state density at room temperature and at 77°K. At room temperature it is observed that the capacitance reached a constant value for large negative bias voltages. Since the capacitance was independent of both bias voltage and frequency in that range, it was assumed that all surface states were responding, the number of states was constant with surface potential, and that the semiconductor capacitance was constant (i.e. the surface was inverted). Under these assumptions the value of C/C,, is given by
(2) The value of C,, was obtained from measurements of capacitance in strong accumulation (positive bias). The value of Csc(minJwas calculated using the known doping of the InAs. The resulting value of C,, was then used to calculate N,, assuming all surface states were active. N-=3. This value of N,, was then used to calculate Curve C of Fig. 4. A similar procedure was not possible for the analysis of measurements performed at 77°K since the measured capacitance continued to decrease as the bias became more negative indicating that the surface did not become inverted. The curves shown in Fig. 5 indicate that at 77°K the surface goes into a deep depletion condition as the bias approaches large negative values. Also, the dispersion which is shown in Fig. 6 shows that not all surface states are responding as the measurement frequency is increased above I MHz. The surface state density which is determined at room temperature is not valid for 77°K as can be seen for Curve C, Fig. 5, where the theoretical curves using the surface density obtained at room temperature was assumed. However, at 77°K the conductance shown in Fig. 9 can be utilized to estimate the surface state density, if we assume that the admittance of the surface states is given by [9] Y,,=~In(lt~~~~)+j~
S.S.E.Vol.
14No.2-C
+tan-r
(07).
(4)
InAs MOS DIODES
121
The conductance term will have a maximum at 07 = 2. Thus, the value of N,, can be estimated at the gate bias for which the surface state conductance peaks. The value of N,, was determined, using the peak value of the surface state conductance. Curve D, Fig. 5, is the calculated capacitance using the value for N,, determined above. In Curve D, Fig. 5, it is assumed that the surface enters a deep depletion condition for large negative bias at 77°K. The deep depletion assumption will be discussed in greater detail below. It is possible to fit experimental data, such as that of Figs. 4 and 5, to any desired degree of precision by postulating, in addition to the fast states and a fixed charge Q,,, the existance of slow states with the proper voltage dependence. These slow states have the property that the charge trapped in them can respond to the d.c. bias but not to the signal frequencies used to measure the capacitance. The slow surface state charge required to match the measured curves is given by %%A Qr,ou = C,rAV=dAV where AV is the difference between the measured gate voltage and the computed gate voltage and C,, is the oxide capacitance. This procedure will in general lead to a rather arbitrary dependence of Q SlOUon surface potential. In the case of SiO, on InAs, if QsroIL’is plotted as a function of the voltage across the oxide, V,,, it is found that Q,,, is a linear function of the voltage across the oxide. Figure IO shows such a plot for the data of Figs. 4 and 5. The experimentally measured value of C,, which was used to compute the curves of Fig. 10 decreased by 15% between room temperature and 77°K. At room temperatures C,, = 121 pF and at 77”K, C,, = 103 pF. A similar decrease was observed in the capacitance of an aluminum-SiO,aluminum capacitor which was fabricated under the same deposition conditions as the MOS structures. This decrease in C,, appears to be due to a decrease in the SiO, dielectric constant as the temperature is decreased. Figure I I shows a plot of AV at 77°K for a set of three diodes with oxide thickness of 920 A;, 1150 A, and 1460 A. The various thicknesses were obtained by adjusting the deposition time while holding all other deposition parameters constant. The value of A V is found to
122
R. J. SCHWARTZ.
R. C. DOCKERTY
I
I
,
and
H. W. THOMPSON.
I
30
I
I
20 Vox
Fig. IO. The insulator
charge
JR
’
IO (Volts)
as a function
of gate voltage.
T=770K Oxide Thickness
I, 70
I 60
Fig.
I
I
50
,
1,
40 VOX (volts)
0.0
X
1460;
A
1150 ii
I,,
30
I I. b V fw various oxide thicknesses.
20
,
60 i
,
IO
1 O0
MEASUREMENTS
ON
N-TYPE
be independent of the oxide thickness in this range. We also note that the slopes of the curves of Fig. 10 are the same even though E, decreases by 15% between 295°K and 77°K. Thus it appears that
A discussion of the possible origin of Qsloul will be deferred until the calculation of Curves A in Figs. 4 and 5 is described. In the presence of (&row the gate voltage is given by
The effect of Qslou, (Y V,, is to expand a plot of capacitance vs. voltage along the voltage axis. This then leads to the observed broad transition region from maximum to minimum capacitance. Curve A of Fig. 4 has been computed utilizing the parameter values noted in the figure. The computation of the total capacitance was performed using the equations derived by Markus [ lo]. Curve A of Fig. 5 was computed in a similar manner except that it was assumed that the diode entered a deep depletion condition for large negative biases such that no minority carriers were present at the surface, even for voltages which were sufficiently negative to cause inversion under equilibrium conditions. It has been shown by Hielscher and Preier[l 11 that the presence of conduction in the insulator can lead to a deep depletion situation in MOS structures. This appears to be the cause of the deep depletion which is observed in Fig. 5. This is in contrast to the deep depletion behavior observed by Gray and Brown[l2] for a thermally grown SO,-silicon interface where deep depletion was caused by the slow build up of minority carriers due to the very low generation rate of minority carriers at 77°K. This situation should not occur for InAs at 77°K because of the much smaller band gap and lower minority carrier lifetime. In fact, a typical response time for the inverted surface should be the order of IO set and deep depletion would not be observed with a d.c. bias applied. However, if a mechanism such as conduction through the oxide is present for the removal of minority carriers from the surface as fast as they are generated, deep depletion will be observed as reported by Hielscher
InAs
MOS
DIODES
123
and Preier. That this was, in fact, the cause of the deep depletion is substantiated by the fact that a stable capacitance value was reached at each new bias value on the order of IO set after changing the bias value. This is further supported by the fact that when strong illumination was placed on the sample, the capacitance increased slightly but returned to its original value as soon as the light was removed. If the deep depletion was due to a process similar to that in silicon at 77”K, the capacitance would not return to the original value upon removal of the illumination. Apparently the generation rate of minority carriers is sufficiently high at room temperature to allow the surface to become inverted. The presence of conduction through the oxide also offers an explanation for both the hysteresis to the voltage and the fact that QsloWis proportional across the oxide. If trapping occurs within the bulk of the oxide the charge in the traps and the distribution of the charge within the oxide will depend upon the magnitude and polarity of the bias voltage. Such trapping can lead to hysteresis effects such as were observed. Hu et al. [7] have discussed similar effects for silicon nitride on silicon. Also, the presence of simple space-chargelimited-flow will lead to a charge within the oxide which is linearly proportional to the applied voltage. Rose [ 131 has pointed out that the amount of charge within an insulator which conducts with spacecharge-limited-flow in the presence of traps is independent of temperature even though the current how is strongly temperature dependent. This is consistent with the observation that the slope of a Qslowvs. V,, curve has the same value as 77°K and room temperature. Attempts to measure the oxide conduction current at 77°K were unsuccessful due to the extremely small values involved. Hence, the presence or absence of space change limited flow must be regarded as speculation. One Puzzling aspect of the above observations is that the surface state density N,, appears to change from 2.4 x lOI state/eV/cm2 at 29S”K to 2.8 X 10” state/eV/cm2 at 77°K. This is particularly puzzling since those states which remain at 77°K do not exhibit any dispersion below I MHz. One possible explanation is that there is more than one type of surface state active at room temperature, one of which fails to respond at 77°K. However, there is no additional evidence to support such a hypothesis.
124
R. J. SCHWARTZ,
There which
are two assumptions are open to question.
that surface state density potential. ment
While
there
between
curves,
the
for a constant tance
SiO,-InAs
The
the
surface
first of these is
This
of
electrons
and
hysteresis,
experimental
state density
as the capaci-
involves
in the surface
potential,
the
normally
absence
under
of
deep
argument
minority
depletion
carriers conditions
used by Nicollian
true,
even in
region,
at the
surface
precludes
and Goetzberger
in this region.
the values of N,,,
the for a
In spite of these which were
are thought to be reasonably
accurate,
in view of the fact that the use of the values for N,,, determined in this manner, leads to a linear voltage dependence of trapped oxide charge at both room temperature and 77°K. Other values of N,Y, have been used, as a test, to calculate the curves of Fig. IO and it is found that the curves are no longer linear. CONCLUSIONS
The surface
behavior
of
conductance can
the
the
by de-
associated observed
transition
region
at 77°K. The presence of very fast surface states at room temperature has been observed. There appears to be an anomalous between
of deep
and
explain
the broad capacitance
and the presence
N,,q is
since
9 appears
problems, determined,
affected
decrease
room temperature
depletion
in the surface state density
and 77°K.
for
inversion
single time constant however,
is strongly properties
and Goetzberger
peak of Fig. be a weak
JR.
fluctuation
4 to determine
is especially
the conduction
what would
the
such as was reported
by Nicollian
[9], then the use of equation though
sensitive
in the accumu-
4. If there is a significant
This
evidence
particularly
use of equation
in question.
structure
conduction
SiO,.
in N,,, especially
system
MOS
electrical
posited
lation region. The second assumption
the SiO,-Si
H. W. THOMPSON,
trapping
of surface
not conclusive
is not
and
to be good agree-
is independent
calculated
measurement
to slow variations
in the above analysis
appears
this is probably
R. C. DOCKERTY
of a pyrolitically
deposited
REFERENCES A. S. Grove. B. E. Deal, E. H. Snow and C‘. T. Sah, Solid-St. Ekrron. 8. 14.5 ( 1965). 2. B. E. Deal, P. J. Fleming and P. L. Castro. J. Elect trocl~r,m. SOC. 115.300 (I 968). 3. A. Waxman and K. H. Zaininger, Appl. P/Z?.\. I%(/. 12, IO9 ( 1968). ‘1 R. Hall and J. P. White, Solid-St. ~Yi~~c~tron. 8. 1 I I ( 1965). 5. H. E. Kunig, Solid-St. Electron. 11, 335 (1968). Rec. 28. I53 6. N. Goldsmith and W. Kern, R.C.A. ( 1967). 7. S. M. Hu, D. R. Kerr and 1.. V. Crregor, Appl. Phys. Letr. 10,97 ( 1967). 8. S. R. Hofstein and G. Warfield. Solid-St. Electron. 8. 321 (1965). 9. E. H. Nicollian and A. C;oetzberger-, He// S~sl. 7 rch. J. 46, I055 ( 1967). IO. P. M. Markus, IBM .I. Res. Dwc~lop. 8.496 ( 1964). 1I. F. H. Hielscher and H. M. Preier. Solid-St. Elrc~tron. 12.527 (1969). 12. D. M. Brown and P. V. Gray. J. E/ec,/roc,l~c,rn.SOC,. 115.760 ( 196X). I?. A. Rose. Phys. Rec. 97. I S38 ( 1955). I.
ON
R. J. SCHWARTZ, R. C. DOCKERTY and H. W. THOMPSON, JR. of Electrical Engineering, Purdue University, Lafayette, Indiana 47907. U.S.A. (Received
27 February
1970; in revisedform
3 August
1970)
Abstract-The electrical properties of the interface between pyrolytically deposited SiO, and InAs have been investigated by measuring the admittance of Al-SiO,-InAs MOS diodes at room temperature and 77°K. The room temperature measurements yield a rather high surface state density of 2.5 x lOI states/eV/cm’. The surface state density undergoes an anomalous decrease to 2.8 X 10” states/eV/cm2 at 77°K. A charge which is linearly dependent on the voltage across the oxide is trapped in the oxide. Conduction through the oxide causes the diodes to enter a deep depletion condition at 77°K. R&me-Les propriCtts tlectriques de l’interface entre le SiO, et le InAs pyrolytiquement dCposCs ont CtC ktudites en mesurant I’admission de diodes Al-SiO,-InAs MOS B tempkrature ambiante et B 77°K. Les mesures prises 21 tempkrature ambiante produisent une densitt d’Ctat de surface plut6t 6levCe de 23 X lOI* &ats/eV/cm*. La densit d’ttat de surface subit un dtcroissement anomal jusqu’8 2,8 X 1OL1 Ctats/eV/cmz B 77°K. Une charge qui est fonction IinCaire de la tension B travers I’oxyde est prisonnibe dans I’oxyde. La conduction $ travers l’oxyde est la cause d’une forte condition d’Cpuisement des tlectrodes B 77°K. ZusammenfassungDurch Messung der Admittanz von Al-SiO,-InAs-MOS-Dioden bei Raumtemperatur und bei 77 K wurden die elektrischen Eigenschaften der GrenztWhe zwischen pyrolytisch abgeschiedenem SiO, und InAs untersucht. Die Zimmertemperaturwerte lieferten eine ziemlich hohe Dichte von 23. 10’2/eV cm* fir die OberflfchenzustBnde. Diese unterliegt einer abnormal groRen Abnahme auf 2,8. IO”/eV cm* bei 77 K. Eine linear vom Spannungsabfall iiber das Oxyd abhLngige Ladune. ist im Oxvd lokalisiert. Die Leitune durch das Oxvd fiihrt bei 77 K zu einer starken Verarmungsz&e in den dioden
QSC charge within the semiconductor QdOlc voltage dependent charge within the oxide YS, surface state admittance/A
NOTATION
electrode area capacitance of MOS diode capture probability for electrons oxide capacitance oxide capacitance/A semiconductor capacitance surface state capacitance oxide thickness average field in the oxide intrinsic carrier concentration fast surface state density magnitude of the electronic charge equivalent fixed charge in the oxide equivalent fixed charge in the oxide/A charge in fast surface states gate voltage (measured with reference semiconductor bulk) voltage across the oxide surface potential of the semiconductor “This work supported Project Agency.
in part by NASA
AV
7
6J
difference between measured gate voltage and gate voltage calculated in the absence of oxide charge permittivity of free space relative dielectric constant of the SO, Fermi energy in the bulk (in units of kT) mid-gap energy at the semiconductor surface (in units of kT) surface state time constant metal semiconductor work function difference angular frequency INTRODUCTION
to the
Institutional
METAL-insulator-semiconductor structures have been extensively employed to study the surface properties of silicon[l-31, and to a lesser extent, Grant 115
No. NCR-1
S-005-021
and the Advanced
Research
116
R. J. SCHWARTZ.
R. C. DOCKERTY
gallium arsenide[4]. Much of the motivation for these studies has come from the fact that field effect transistor performance is strongly dependent upon the properties of the semiconductor surface. The number and frequency response of the surface states at the insulator-semiconductor boundary can have a dominant effect on the performance of an insulated gate field effect transistor. Relatively little information is available about the surface properties of other potentially useful semiconductors such as InAs. While Kunig[S] has reported on the fabrication of thin film SiO,-InAs transistors with field effect mobilities as high as 7SOOcm”/ Vsec, there have been no reports on the electrical properties of the surface states which exist at an SiO,-InAs interface. This investigation is a study of the SiO,-InAs interface of an MOS structure such as is shown in Fig. I. In the course of this investigation we have found that the surface states which exist at a deposited SiO,-single crystal InAs interface are extremely fast (all states respond at 20 MHL at room temperature). The investigation also revealed that electrical charge was trapped in the oxide at a rate which was linearly proportional to the voltage applied across the oxide. This voltage dependent oxide trapping, as well as hysteresis effects and low temperature deep depletion effects, are attributed to electrical leakage through the oxide.
FIG. 1. Metal-oxide-semiconductor
structure.
EXPERIMENTAL PROCEDURE Sample
preprrrution
Czochralski grown, single crystal, rl-type indium arsenide was used throughout this study. The IZtype wafers were not intentionally doped. The doping level was 2.2 x 10’” atoms/en? for all samples reported below. After mechanical polishing. the indium arsenide wafers were cleaned in a succession of organic solvent rinses. Immediately prior to the insulation deposition, the wafers were given a further chemical cleaning and were then etched in a 2% bromine in methanol solution for one minute. This was followed by successive rinses
and H. W. THOMPSON,
JR
in methanol, trichloroethylene, and isopropyl alcohol. The bromine etch was found to polish the (I IO) and (100) faces. but resulted in pitting of the (I IIA) and( I I IB) faces. Because of this pitting only the (100) and (I 10) surfaces were used to fabricate the SiO,-MOS capacitors. SiO: was deposited to a thickness of l2002000 A on the surface of the InAs by means of the reaction between SiH., and O,, using the technique described by Goldsmith and Kern[6]. The substrate temperature was maintained at 400°C during deposition of the SiO, layer. Oxide thickness could be estimated during deposition from the interference colors. The thickness was later verified by the use of step etching and multiple beam interferometer techniques. Oxide layers deposited in this manner were uniform in thickness over the central region of the wafer with a decrease in thickness of up to 25% at the edges. All measurements were confined to regions of uniform thickness. Vacuum evaporated 5-9’s aluminum was used as a gate electrode. Geometry definition wab obtained either by the use of photolithographic techniques or by evaporation through beryllium-copper masks. The metal contact area was 2.5 x IO-:’ cmz. Electrical contact to the InAs substrate was made by means of large area conductive silver epoxy contacts. This procedure was found to yield low resistance ohmic contact to the bulk InAs. The series resistance was low enough at both room temperaiure and at 77°K such that there was no Ggnificant ePiect on the measured value of the diode capacitance at frequencies as high as 20 MHz. Several wafers were annealed immediately after the oxide was deposited. In these cases, the InAs wafer was cut in half after the oxide deposition, and one half was retained for measurement, while the other half was annealed and then measured. Annealing was carried out at 4OO”C-600°C’ in quartL tubes with either oxygen or nitrogen flowing over the sample throughout the anneal. The effects of high fields applied at elevated temperatures (B-7‘ stress) were studied by applying electric fields of LIP to 4 X IO” V/cm to the oxide while maintaining the sample at 115°C‘. Throughout this discussion the polarity of the voltage applied to the metal electrode is specified with reference to the semi-conductor bulk. Admittance measurements of the structure shown in Fig. I were made at I and IO kHr using a General Kadio I6 I 5-A capacitance bridge. while
MEASUREMENTS
ON
N-TYPE
a Boonton Model 74C-S8 capacitance bridge was used at 100 KHz, and a Boonton Model 33A r-f admittance bridge was used at 1,5,10 and 20 MHz. Measurements were performed at room temperature and 77°K. In all cases, the a.c. signal was maintained at a level which was sufficiently small so that the problems associated with harmonic generation were avoided. Measurements were performed in the dark unless specified otherwise. EXPERIMENTAL
InAs
MOS
117
DIODES c IPFI 80
L
RESULTS
A typical capacitance-voltage (C-V) curve for an Al-SiO,-InAs diode is shown in Fig. 2. The data from which Fig. 2 was plotted was taken sufficiently slowly (approximately 30 seconds delay after a change in bias voltage) that a stable value of capacitance was obtained at each value of bias voltage. The entire curve was traversed in this manner. The hysteresis exhibited by this curve is typical of measurements at both room temperature and 77°K. Clockwise traversal of the hysteresis loop, such as is shown in Fig. 2, is indicative of hole or electron trapping in the oxide [7]. Two experiments were performed which tend to confirm the presence of electron trapping in the insulator. In the first experiment, the amount of hysteresis was measured as a function of the magnitude of the maximum negative bias applied to the gate. The hysteresis increased as the maximum negative gate bias increased in accordance with both the trapping model of Hofstein and Warfield [8] and the conduction model of Hu et al.[7]. The effect is similar to that reported by Deal et al.[2] for silane deposited SiO, on silicon. In the second experiment, a sample was subjected to various negative bias-temperature (B-T) stresses between C-V measurements. The results of this experiment are shown in Fig. 3. Only the C-V data obtained by varying the bias voltage from positive to negative values are shown. The first application of 2.5 X lo6 V/cm for 1.75 hr at I 15°C produced a pronounced shift in the curve toward positive bias values (Curve B, Fig. 3). Such a shift is indicative of positive ion motion in the oxide. Similar shifts in SiO,-Si structures have been found to be due to the migration of sodium ions toward the gate electrode during B-T stress. A second application of B-T stress, this time at 3.3 X 10’ V/cm and 115°C for 1-75 hr, resulted in a partial reversal of the previous shift (Curve C, Fig. 3). Further B-T stress (3.3 X lo6 V/cm, 1lS”C,
Fig.
2. Hysteresis in the C-V measurements all samples at 295°K and 77°K.
Fig. 3. The effect of bias-temperature capacitance.
stress
typical
of
on the MOS
for 5.5 hr) produced a continued shift in the C-V curve toward negative bias (Curve D, Fig. 3). The observed shift of the C-V curve toward negative bias after the application of a strong negative bias is consistent with emission of electrons from oxide traps into the semiconductor. When a strong negative bias was applied to the metal of a previously unstressed diode at 77”K, only the shift toward more negative bias values was observed, indicating that the electronic process was dominant at low temperatures. Figures 4 and 5 show the dependence of the capacitance of the Al-SiO,-InAs structure upon bias voltage at 295°K and 77°K for the (110) surface. The data of Figs. 4 and 5 were taken on the same sample. Similar results were obtained on the (100) surfaces. Theoretical curves for the case where there is no oxide charge and no surface states are also shown for comparison (Curve B). At both 77°K and room temperature the experi-
118
R. J. SCHWARTZ,
R. C. DOCKERTY
and
H. W. THOMPSON.
JR
N , ss x2.46 X 10’2states/ev/cme Ofix=2.5X 10’Oel. charge/cm* 0 slow=o~*75
Nss=2A6X10’t Oiix = 0
states/ev/crn OE
%lOW =0
0 Measured Valuer f=20 MHz T= 295” K Cox= 120.7 pF
InAs
0.E
Surface
0.7
Nss= I
QSIOW =0
________________________Q~ 8 0.E
--+-AFig. 4. Experimental and theoretical values of the capacitance function of the bias voltage at 295°K.
as a
mental C-V curves are displaced from the theoretical in the direction of negative bias. In addition, the transition from maximum capacitance to minimum capacitance is spread over an extremely wide voltage range. At room temperature the capacitance is constant for large negative voltages while at 77°K the capacitance was observed to continue to decrease with increasing negative voltage until the breakdown voltage of the oxide was reached. Room temperature capacitance measurements are independent of frequency between
Iexp c,ni where trinsic
(K-P~,)
(1)
c,, is the capture probability. IQ is the incarrier concentration and (P*..~-pcLH) is the
MEASUREMENTS
ON N-TYPE
119
InAs MOS DIODES
0 Measured Values
< IlO>
ve
InAs
Surface
(Volts)
Fig. 5. Experimental and theoretical values of the capacitance as a function of bias voltage, for the same diode as shown in Fig. 4, at 77°K. difference between the mid-gap energy and the Fermi level at the surface in units of kT. If the capture probabilities are comparable for SiO,-Si and InAs-SiO, interfaces, then the time constant r will be approximately 10e4 that of silicon for a comparable ( ps - pB) because of the fact that the intrinsic carrier concentration of InAs is IO4 as large as that of silicon. There is of course no assurance that the capture probabilities will be similar for SiO,-Si and SiO,-InAs interfaces. In each case, as the bias voltage was changed, 2-10 set were required before the capacitance reached a constant value. The observed drift in the measured capacitance was toward increasing values of capacitance after the bias was changed from one value to a more negative value.
The effects of annealing in nitrogen and oxygen are shown in Figs. 7 and 8. In each case the primary effect of the anneal was to cause a decrease in the oxide capacitance, as long as the annealing temperature was held below 600°C. A similar decrease in the oxide capacitance was observed by Goldsmith and Kern[6] when SiO,, deposited at 325°C on silicon, was heat treated in argon at 770°C for I2 min. The change appears to be attributable to a decrease in the SiO, dielectric constant. At an annealing temperature of 600°C in an oxygen ambient, the surface state density increases to the point where C became independent of gate bias. A typical conductance curve for G-V measurements, measured at 10 MHz, is shown in Fig. 9. AS can be seen in Fig. 9, a well defined peak
120
R. J. SCHWARTZ,
I -40
,
I
Fig.
6. Capacitance
and
H. W. THOMPSON,
JR.
,
0
-20
“Q
R. C. DOCKERTY
~“Olll,
dispersion
curves
for SiO,
on the
(110) surface of InAs at 77°K. Fig. 9. MOS conductance
for the diode of Fig. 4.
occurred in the conductance measurements at 77°K. No peaks were observed for conductance measurements performed at room temperature. The behavior of the (100) and the (1 IO) surfaces were found to be similar for all measurements. DISCUSSION It is not possible
Fig. 7. The effect
of a 2 hr anneal atmosphere.
at 410°C in a nitrogen
Fig. 8. The effect of a 2 hr anneal atmosphere.
at 400°C in an oxygen
to explain both the very large negative shift (AP’) of the C-V curves and the extremely wide C,,, to Cmin transition region shown in Figs. 4 and 5 through the usual fixed oxide charge and fast surface states model. If fast surface states were present in sufficient numbers to yield a transition region as broad as that which is observed, the capacitance associated with these states would be so large that it would effectively mask the capacitance modulation with bias. The usual procedure for determining the fast surface state density involves a measurement of the capacitance at a frequency which is sufficiently high that none of the surface states can respond. The voltage difference between the measured and calculated value is then used to compute the amount of surface charge. The use of this technique was not possible in this study as the presence of a series resistance of approximately 1.5 ohms at room temperature limited the highest frequency at which reliable capacitance measurements could be made to 20 MHz. As has been noted above, no dispersion was observed up to 20 MHz at room temperature so a true “high frequency curve” could not be obtained. At 77°K
MEASUREMENTS
ON N-TYPE
dispersion was observed but some surface states appear to be responding even at 20 MHz. Two different techniques were utilized to estimate the fast surface state density at room temperature and at 77°K. At room temperature it is observed that the capacitance reached a constant value for large negative bias voltages. Since the capacitance was independent of both bias voltage and frequency in that range, it was assumed that all surface states were responding, the number of states was constant with surface potential, and that the semiconductor capacitance was constant (i.e. the surface was inverted). Under these assumptions the value of C/C,, is given by
(2) The value of C,, was obtained from measurements of capacitance in strong accumulation (positive bias). The value of Csc(minJwas calculated using the known doping of the InAs. The resulting value of C,, was then used to calculate N,, assuming all surface states were active. N-=3. This value of N,, was then used to calculate Curve C of Fig. 4. A similar procedure was not possible for the analysis of measurements performed at 77°K since the measured capacitance continued to decrease as the bias became more negative indicating that the surface did not become inverted. The curves shown in Fig. 5 indicate that at 77°K the surface goes into a deep depletion condition as the bias approaches large negative values. Also, the dispersion which is shown in Fig. 6 shows that not all surface states are responding as the measurement frequency is increased above I MHz. The surface state density which is determined at room temperature is not valid for 77°K as can be seen for Curve C, Fig. 5, where the theoretical curves using the surface density obtained at room temperature was assumed. However, at 77°K the conductance shown in Fig. 9 can be utilized to estimate the surface state density, if we assume that the admittance of the surface states is given by [9] Y,,=~In(lt~~~~)+j~
S.S.E.Vol.
14No.2-C
+tan-r
(07).
(4)
InAs MOS DIODES
121
The conductance term will have a maximum at 07 = 2. Thus, the value of N,, can be estimated at the gate bias for which the surface state conductance peaks. The value of N,, was determined, using the peak value of the surface state conductance. Curve D, Fig. 5, is the calculated capacitance using the value for N,, determined above. In Curve D, Fig. 5, it is assumed that the surface enters a deep depletion condition for large negative bias at 77°K. The deep depletion assumption will be discussed in greater detail below. It is possible to fit experimental data, such as that of Figs. 4 and 5, to any desired degree of precision by postulating, in addition to the fast states and a fixed charge Q,,, the existance of slow states with the proper voltage dependence. These slow states have the property that the charge trapped in them can respond to the d.c. bias but not to the signal frequencies used to measure the capacitance. The slow surface state charge required to match the measured curves is given by %%A Qr,ou = C,rAV=dAV where AV is the difference between the measured gate voltage and the computed gate voltage and C,, is the oxide capacitance. This procedure will in general lead to a rather arbitrary dependence of Q SlOUon surface potential. In the case of SiO, on InAs, if QsroIL’is plotted as a function of the voltage across the oxide, V,,, it is found that Q,,, is a linear function of the voltage across the oxide. Figure IO shows such a plot for the data of Figs. 4 and 5. The experimentally measured value of C,, which was used to compute the curves of Fig. 10 decreased by 15% between room temperature and 77°K. At room temperatures C,, = 121 pF and at 77”K, C,, = 103 pF. A similar decrease was observed in the capacitance of an aluminum-SiO,aluminum capacitor which was fabricated under the same deposition conditions as the MOS structures. This decrease in C,, appears to be due to a decrease in the SiO, dielectric constant as the temperature is decreased. Figure I I shows a plot of AV at 77°K for a set of three diodes with oxide thickness of 920 A;, 1150 A, and 1460 A. The various thicknesses were obtained by adjusting the deposition time while holding all other deposition parameters constant. The value of A V is found to
122
R. J. SCHWARTZ.
R. C. DOCKERTY
I
I
,
and
H. W. THOMPSON.
I
30
I
I
20 Vox
Fig. IO. The insulator
charge
JR
’
IO (Volts)
as a function
of gate voltage.
T=770K Oxide Thickness
I, 70
I 60
Fig.
I
I
50
,
1,
40 VOX (volts)
0.0
X
1460;
A
1150 ii
I,,
30
I I. b V fw various oxide thicknesses.
20
,
60 i
,
IO
1 O0
MEASUREMENTS
ON
N-TYPE
be independent of the oxide thickness in this range. We also note that the slopes of the curves of Fig. 10 are the same even though E, decreases by 15% between 295°K and 77°K. Thus it appears that
A discussion of the possible origin of Qsloul will be deferred until the calculation of Curves A in Figs. 4 and 5 is described. In the presence of (&row the gate voltage is given by
The effect of Qslou, (Y V,, is to expand a plot of capacitance vs. voltage along the voltage axis. This then leads to the observed broad transition region from maximum to minimum capacitance. Curve A of Fig. 4 has been computed utilizing the parameter values noted in the figure. The computation of the total capacitance was performed using the equations derived by Markus [ lo]. Curve A of Fig. 5 was computed in a similar manner except that it was assumed that the diode entered a deep depletion condition for large negative biases such that no minority carriers were present at the surface, even for voltages which were sufficiently negative to cause inversion under equilibrium conditions. It has been shown by Hielscher and Preier[l 11 that the presence of conduction in the insulator can lead to a deep depletion situation in MOS structures. This appears to be the cause of the deep depletion which is observed in Fig. 5. This is in contrast to the deep depletion behavior observed by Gray and Brown[l2] for a thermally grown SO,-silicon interface where deep depletion was caused by the slow build up of minority carriers due to the very low generation rate of minority carriers at 77°K. This situation should not occur for InAs at 77°K because of the much smaller band gap and lower minority carrier lifetime. In fact, a typical response time for the inverted surface should be the order of IO set and deep depletion would not be observed with a d.c. bias applied. However, if a mechanism such as conduction through the oxide is present for the removal of minority carriers from the surface as fast as they are generated, deep depletion will be observed as reported by Hielscher
InAs
MOS
DIODES
123
and Preier. That this was, in fact, the cause of the deep depletion is substantiated by the fact that a stable capacitance value was reached at each new bias value on the order of IO set after changing the bias value. This is further supported by the fact that when strong illumination was placed on the sample, the capacitance increased slightly but returned to its original value as soon as the light was removed. If the deep depletion was due to a process similar to that in silicon at 77”K, the capacitance would not return to the original value upon removal of the illumination. Apparently the generation rate of minority carriers is sufficiently high at room temperature to allow the surface to become inverted. The presence of conduction through the oxide also offers an explanation for both the hysteresis to the voltage and the fact that QsloWis proportional across the oxide. If trapping occurs within the bulk of the oxide the charge in the traps and the distribution of the charge within the oxide will depend upon the magnitude and polarity of the bias voltage. Such trapping can lead to hysteresis effects such as were observed. Hu et al. [7] have discussed similar effects for silicon nitride on silicon. Also, the presence of simple space-chargelimited-flow will lead to a charge within the oxide which is linearly proportional to the applied voltage. Rose [ 131 has pointed out that the amount of charge within an insulator which conducts with spacecharge-limited-flow in the presence of traps is independent of temperature even though the current how is strongly temperature dependent. This is consistent with the observation that the slope of a Qslowvs. V,, curve has the same value as 77°K and room temperature. Attempts to measure the oxide conduction current at 77°K were unsuccessful due to the extremely small values involved. Hence, the presence or absence of space change limited flow must be regarded as speculation. One Puzzling aspect of the above observations is that the surface state density N,, appears to change from 2.4 x lOI state/eV/cm2 at 29S”K to 2.8 X 10” state/eV/cm2 at 77°K. This is particularly puzzling since those states which remain at 77°K do not exhibit any dispersion below I MHz. One possible explanation is that there is more than one type of surface state active at room temperature, one of which fails to respond at 77°K. However, there is no additional evidence to support such a hypothesis.
124
R. J. SCHWARTZ,
There which
are two assumptions are open to question.
that surface state density potential. ment
While
there
between
curves,
the
for a constant tance
SiO,-InAs
The
the
surface
first of these is
This
of
electrons
and
hysteresis,
experimental
state density
as the capaci-
involves
in the surface
potential,
the
normally
absence
under
of
deep
argument
minority
depletion
carriers conditions
used by Nicollian
true,
even in
region,
at the
surface
precludes
and Goetzberger
in this region.
the values of N,,,
the for a
In spite of these which were
are thought to be reasonably
accurate,
in view of the fact that the use of the values for N,,, determined in this manner, leads to a linear voltage dependence of trapped oxide charge at both room temperature and 77°K. Other values of N,Y, have been used, as a test, to calculate the curves of Fig. IO and it is found that the curves are no longer linear. CONCLUSIONS
The surface
behavior
of
conductance can
the
the
by de-
associated observed
transition
region
at 77°K. The presence of very fast surface states at room temperature has been observed. There appears to be an anomalous between
of deep
and
explain
the broad capacitance
and the presence
N,,q is
since
9 appears
problems, determined,
affected
decrease
room temperature
depletion
in the surface state density
and 77°K.
for
inversion
single time constant however,
is strongly properties
and Goetzberger
peak of Fig. be a weak
JR.
fluctuation
4 to determine
is especially
the conduction
what would
the
such as was reported
by Nicollian
[9], then the use of equation though
sensitive
in the accumu-
4. If there is a significant
This
evidence
particularly
use of equation
in question.
structure
conduction
SiO,.
in N,,, especially
system
MOS
electrical
posited
lation region. The second assumption
the SiO,-Si
H. W. THOMPSON,
trapping
of surface
not conclusive
is not
and
to be good agree-
is independent
calculated
measurement
to slow variations
in the above analysis
appears
this is probably
R. C. DOCKERTY
of a pyrolitically
deposited
REFERENCES A. S. Grove. B. E. Deal, E. H. Snow and C‘. T. Sah, Solid-St. Ekrron. 8. 14.5 ( 1965). 2. B. E. Deal, P. J. Fleming and P. L. Castro. J. Elect trocl~r,m. SOC. 115.300 (I 968). 3. A. Waxman and K. H. Zaininger, Appl. P/Z?.\. I%(/. 12, IO9 ( 1968). ‘1 R. Hall and J. P. White, Solid-St. ~Yi~~c~tron. 8. 1 I I ( 1965). 5. H. E. Kunig, Solid-St. Electron. 11, 335 (1968). Rec. 28. I53 6. N. Goldsmith and W. Kern, R.C.A. ( 1967). 7. S. M. Hu, D. R. Kerr and 1.. V. Crregor, Appl. Phys. Letr. 10,97 ( 1967). 8. S. R. Hofstein and G. Warfield. Solid-St. Electron. 8. 321 (1965). 9. E. H. Nicollian and A. C;oetzberger-, He// S~sl. 7 rch. J. 46, I055 ( 1967). IO. P. M. Markus, IBM .I. Res. Dwc~lop. 8.496 ( 1964). 1I. F. H. Hielscher and H. M. Preier. Solid-St. Elrc~tron. 12.527 (1969). 12. D. M. Brown and P. V. Gray. J. E/ec,/roc,l~c,rn.SOC,. 115.760 ( 196X). I?. A. Rose. Phys. Rec. 97. I S38 ( 1955). I.