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Carbon nanotube ferroelectric random access memory cell based on omega-shaped ferroelectric gate
Carbon 162 (2020) 195e200
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Carbon nanotube ferroelectric random access memory cell based on omega-shaped ferroelectric gate Seongchan Kim a, 1, Jia Sun c, 1, Yongsuk Choi d, Dong Un Lim d, Joohoon Kang b, Jeong Ho Cho d, * a
SKKU Advanced Institute of Nanotechnology (SAINT), Suwon, 16419, South Korea School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon, 16419, South Korea Hunan Key Laboratory for Super Microstructure and Ultrafast Process, School of Physics and Electronics, Central South University, Changsha, Hunan, 410083, PR China d Department of Chemical and Biomolecular Engineering, Yonsei University, Seoul, 03722, South Korea b c
a r t i c l e i n f o
a b s t r a c t
Article history: Received 31 December 2019 Received in revised form 16 February 2020 Accepted 17 February 2020 Available online 18 February 2020
This paper presents a flexible ferroelectric random access memory (FeRAM) cell with a one-transistorone-transistor structure. The FeRAM cell was composed of a control transistor (CT) and an omegashaped ferroelectric memory transistor (MT). An inkjet-printed single-walled carbon nanotube (SWCNT) were utilized as a semiconducting channel layers of both transistors. An omega-shaped ferroelectric gate was formed through inkjet-printing of poly(vinylidene fluoride-co-trifluoroethylene) (P(VDF-TrFE)) onto the SWCNT channel of the MT. The gate electrode of the CT was electrically connected to the drain electrode of the MT, while the gate electrode of the MT was connected to the source electrode of the CT. The 1T1T architecture enabled the separation of the writing and reading operations, which afforded nondestructive readout capability. The desired multi-level conductance states could be deterministically controlled by tuning the dipole polarization in the ferroelectric P(VDF-TrFE) layer of the MT. The resulting FeRAM cell showed excellent device performances such as five-level data storage, a high programming/erasing current ratio (>105), a retention time (>104 s), and operational stability (>1000 cycles). The 1T1T FeRAM cell fabricated by inkjet printing technique opens up new opportunities for realizing future large-area flexible memory cells. © 2020 Elsevier Ltd. All rights reserved.
Keywords: Single-walled carbon nanotube Transistor Memory One-transistor-one-transistor FeRAM Nondestructive readout
1. Introduction Because of the rapid development of flexible electronics, they are now required to include flexible devices integrated into all-inone systems [1e5]. Memory devices are the most fundamental components of modern electronic circuits and systems for longterm data storage [6e9]. Currently, there is a strong demand for the fabrication of high-performance flexible memory devices via cost-effective manufacturing processes, which have great potential for use in various applications including wearable electronics, artificial electronic skins, mobile computing devices, flexible displays, and humanemachine interfaces [10e13]. From the viewpoint of device architecture, memory devices can be classified into
* Corresponding author. E-mail address: [email protected] (J.H. Cho). 1 S. Kim and J. Sun contributed equally to this work as the first author. https://doi.org/10.1016/j.carbon.2020.02.044 0008-6223/© 2020 Elsevier Ltd. All rights reserved.
resistor-type, capacitor-type, and transistor-type memories [12,14]. Among the existing memory technologies, ferroelectric field-effect transistor (FeFET)-based memories, in which the gate dielectric is substituted with a ferroelectric layer, have attracted tremendous attention for use in next-generation memory chips [15e19]. Such a device is operated via a change in the ferroelectric polarization state induced through application of a sufficient external gate electric field and consequent generation of a surface charge on the ferroelectric film and accumulation of opposite-sign carriers in the channel layer; such devices offer exceptional advantages of low power consumption, nonvolatility, high speed, and multi-level data storage [15e19]. In particular, organic poly(vinylidene fluoride-cotrifluoroethylene) (P(VDF-TrFE)) is a promising candidate for flexible memory devices because of its solution processability and ease of deposition at low temperatures [20e23]. Use of conventional ferroelectric random access memory (FeRAM) technology with one-transistor-one-capacitor architecture is considered an adequate approach for the realization of high-performance
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memory units [24e26]. However, the conventional FeRAM usually suffers from unavoidable device-to-device interference during memory access operation when the devices are integrated on a large scale [24e27]. As a result of this fatal drawback, the writing operation of a target device results in programming of its neighboring device. Thus, the writing and reading processes should be completely separated in order to ensure nondestructive readout operation. A highly efficient and low-cost fabrication procedure that does not involve complicated lithography processes is strongly required for realizing a high-performance flexible memory cell with a ferroelectric P(VDF-TrFE) gate. Printed electronics have attracted much attention because they offer advantages such as direct patterning of electronic components, cost-effectiveness, and largearea fabrication [28e31]. The main challenge in the use of printed electronics is to develop high-performance inks for semiconducting channel materials, since the semiconductor is the core of electronic devices. Because single-walled carbon nanotube (SWCNT) offer advantages of ease of use as printable inks, high mobility, excellent physical and chemical properties, and environmental stability, they have emerged as favorable channel layer materials for transistortype memory devices [32e37]. Importantly, the network structure of one-dimensional SWCNT as the channel layer permits the fabrication of an omega-shaped ferroelectric gate through incorporation of an organic P(VDF-TrFE) layer [38,39]. Such a creative device structure can greatly simplify the manufacturing process of ferroelectric memory devices. In this study, we developed a flexible one-transistor-onetransistor (1T1T) FeRAM cell with nondestructive readout capability. The FeRAM cell was integrated onto a plastic substrate by connecting a ferroelectric memory transistor (MT) with a control transistor (CT). The SWCNT was inkjet-printed to serve the semiconducting channel layers of both the CT and the MT, and P(VDFTrFE) was inkjet-printed on top of the SWCNT layer to form an omega-shaped ferroelectric gate of the MT. The resulting flexible FeRAM cell provided exceptional advantages of simple fabrication through inkjet printing and separation of the writing and reading processes for nondestructive readout. The device exhibited excellent memory performances, such as a high programming/erasing current ratio, long retention time, and multi-bit information storage capability. This work paves the way toward the realization of high-performance nonvolatile FeRAM cells for application to flexible printed electronics. 2. Methods The flexible 1T1T FeRAM cell was fabricated on a polyethylene naphthalate (PEN) substrate. The substrates was cleaned sequentially with deionized water, acetone, and isopropanol and then dried with N2 gas. First, 40-nm-thick indium tin oxide (ITO) bottom-gate electrode patterns were deposited onto the substrate by RF sputtering through a metallic shadow mask. The Al2O3 layer with thickness of 50 nm was then deposited onto the PEN substrate with predefined gate electrodes via ALD. As mentioned above, Au patterns with a thickness of 40 nm were deposited by thermal evaporation via a shadow mask, which were used as the source and drain electrodes of both the CT and the MT. Highly purified semiconducting SWCNT (purity > 98%) was purchased from SigmaAldrich, which were used as printable ink. The SWCNT was printed onto the channel region by using an inkjet printer (DMP2850, Dimatix-Fujifilm, Inc.). The water-based SWCNT ink was printed onto the predefined channel area at a printing speed of 3 mm/s. The printing times were controlled for achieving the desired density of SWCNT. The channel length (L) and width (W) were 1000 and 100 mm, respectively. Finally, 2 wt% solution of P(VDF-TrFE)
dissolved in acetone was inkjet-printed on top of the SWCNT channel layer, and the resultant layer served as an omega-shaped ferroelectric gate of the MT. All the device performances were measured using Keithley 2400 and 236 source/measure units at room temperature under dark conditions. 3. Results and discussion In the 1T1T FeRAM cell, the MT was utilized as a data storage unit and the CT was utilized to control the access of the MT. Fig. 1a shows a schematic of the flexible 1T1T FeRAM cell based on the inkjet-printed SWCNT and P(VDF-TrFE). First, a flexible polyethylene naphthalate (PEN) was used as a substrate for the memory cell and 40-nm-thick indium tin oxide (ITO) bottom-gate electrode patterns were deposited onto the substrate by radio-frequency (RF) sputtering through a metallic shadow mask. A 50-nm-thick Al2O3 gate dielectric was deposited onto the PEN substrate with predefined gate electrodes via the atomic layer deposition (ALD) technique. The specific capacitance of the Al2O3 layer was around 132 nFcm2. As mentioned above, Au patterns with a thickness of 40 nm were deposited by thermal evaporation through a shadow mask, which were used as the source and drain electrodes of both the CT and the MT. Highly purified SWCNT was used as printable semiconductor ink [40]. Printing of the SWCNT onto the channel region was performed using a commercial inkjet printer (Fig. 1b). Finally, the solution of P(VDF-TrFE) dissolved in acetone was inkjetprinted on top of the SWCNT channel layer, and the resultant layer served as an omega-shaped ferroelectric gate of the MT (Fig. 1c). Fig. 1d shows the optical top-view image of the flexible 1T1T FeRAM cell fabricated onto the plastic substrate. The operation of the omega-shaped ferroelectric MT proposed in this study is different from that of the conventional ferroelectric MT with the ferroelectric layer serving as a gate dielectric layer. The operation mechanism of the proposed MT is explained schematically in Fig. 1e. When a positive gate pulse was applied to the back gate, the electrostatic field gradient created by the gate terminal resulted in an upward polarization of HeF dipoles in the ferroelectric layer. In this case, the positive H dipoles (dþ) were aligned in the upward direction, whereas the negative F dipoles (d) were aligned in the downward direction; the latter consequently came into direct contact with the SWCNT surface, which resulted in the accumulation of holes in the SWCNT channel and induced the “programming state” of the p-type SWCNT transistors. The nonvolatility of the HeF dipole polarization resulted in the accumulation of an equal number of holes within the SWCNT channel, which enabled the current to remain unchanged even after the removal of the gate pulse [38,39]. The persistent dipole polarization afforded a long-term nonvolatile memory property. In contrast, a negative gate pulse induced the opposite polarization of the HeF dipoles in the ferroelectric layer, which resulted in the depletion of holes in the SWCNT channel and consequently induced the “erasing state” of the p-type SWCNT transistors. Flexible 1T1T FeRAM cells were fabricated on the basis of the operation mechanism of the omega-shaped ferroelectric MT. Fig. 1f shows a circuit diagram of the FeRAM cell. The memory cell consisted of a bottom-gate CT and an omega-shaped ferroelectric MT, in which, the gate electrode of the CT was electrically connected to the drain electrode of the MT, while the gate electrode of the MT was connected to the source electrode of the CT. The 1T1T architecture was beneficial for controlling the writing and reading processes of the MT using the CT, and thus, these two distinct processes were completely separated. Fig. 1g shows the writing (programming and erasing) and reading voltages of the flexible 1T1T FeRAM cell. When a negative voltage (10 V) was applied at the word line (VWL), the CT of the cell turned on. As a consequence, the voltage
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Fig. 1. (a) Schematic device structure of SWCNT-based FeRAM cell consisting of CT and ferroelectric MT. (b, c) AFM image of inkjet-printed SWCNT (b) and PVDF-TrFE (c) layers. (d) Optical top-view image of SWCNT-based FeRAM cell. (e) Operation mechanism of omega-shaped ferroelectric MT. (f) Circuit diagram of SWCNT-based FeRAM cell. (g) Table describing writing (programming and erasing) and reading processes. (A colour version of this figure can be viewed online.)
applied at the bit line (VBL) was transferred to the gate of the MT and the conductance of the MT changed correspondingly. In the writing process, VBL of þ18 V and 18 V were applied for programming and erasing, respectively, of the MT. These input values of VBL were stored in the MT. In the reading process, however, a positive voltage (þ10 V) was applied at the word line, which caused the CT to turn off. The channel conductance of the MT was not affected by the input voltage VBL. Resultingly, the 1T1T FeRAM cell architecture enabled the separation of the writing and reading operations, which, in turn, afforded nondestructive readout capability. First, the electrical properties of the SWCNT-based CT and MT were investigated. Fig. 2a displays the representative transfer characteristics of the CT when the gate voltage (VG) was swept in a closed loop: from þ10 V to 10 V back to þ10 V. The drain voltage (VD) was fixed to 10 V. The SWCNT transistors exhibited p-type conduction with an on-off current ratio exceeding 105, which provided sufficient current modulation to control the access of the MT. According to the standard transistor equation, the hole mobility in the saturation region was calculated to be as high as 6.4 cm2 V1s1. No significant hysteresis between the forward and reverse sweeps was observed, but a slight hysteresis may have originated from the shallow charge traps inside the SWCNT or at the SWCNTeAl2O3 interface. In contrast, a large hysteresis window was observed in the transfer curves of the SWCNT-based MT (Fig. 2b). Because of the electric-field-induced dipole orientation in the omega-shaped ferroelectric P(VDF-TrFE) layer, the transfer curves showed counterclockwise hysteresis. Upon sweeping of VG from the positive to the negative voltage direction, the dipoles in the omega-shaped ferroelectric P(VDF-TrFE) layer were aligned in
the upward direction. Such an alignment caused the negative dipoles to point to the SWCNT layer, which resulted in the accumulation of holes in the SWCNT channel layer and thus caused an increased drain current (ID). Sweeping of VG back from the negative to the positive voltage direction caused the polarized dipole in the ferroelectric P(VDF-TrFE) layer to gradually switch with the positive dipoles pointing to the SWCNT layer. During this process, the applied VG was partially screened by the electric field generated by the dipole formed in the ferroelectric P(VDF-TrFE) layer. The lowered effective VG resulted in the threshold voltage (VTH) shift to negative voltage direction during the reverse sweep. The electricfield-induced dipole orientation in the omega-shaped ferroelectric P(VDF-TrFE) layer during VG sweep was summarized in Fig. 2c. Note that simple inkjet printing of a single P(VDF-TrFE) droplet onto the SWCNT channel provided memory functionality to the SWCNT transistor, which simplified the steps of the separate fabrications of the CT and MT and the subsequent electrical connection between them. It was obviously observed that the hysteresis loop became enlarged with an increase in the sweep range of VG (Fig. 2d), while the off-current level remained as low as 109 A. The difference in VTH between the forward and reverse sweeps is defined as a memory window. To evaluate the data storage capability of the MT, the memory window was extracted; the corresponding data are plotted in Fig. 2e. The memory window was measured to be around 9.5 V for the VG sweep range of ±10 V. The memory window increased to 13.8 V with increasing the VG sweep range to ±18 V because of the stronger dipole polarization in the P(VDF-TrFE) layer. Consequently, the dipole polarization in the omega-shaped ferroelectric P(VDF-TrFE) layer and the resulting memory properties
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Fig. 2. (a) Semi-log scale plot of transfer curves of CT of SWCNT-based FeRAM cell. (b) Hysteresis behavior of MT of 1T1T memory cell as a function of VG sweep ranges of ±10 V and ±18 V. (c) Electric-field-induced dipole orientation in the omega-shaped ferroelectric P(VDF-TrFE) layer during VG sweep. (d) Linear scale plot of transfer curves of MT of 1T1T memory cell as a function of VG sweep ranges of ±10 V and ±18 V. (e) Memory window of transfer curves as a function of VG sweep range. (f) Shift in transfer curves after application of various erasing VG pulses for 1 s. (g) Shift in transfer curves after application of programming VG of 20 V for various time durations. (h) Drain current at VG ¼ 0 V as a function of erasing voltage. (i) Comparison of the memory window according to tensile strains (0% and 1%).
could be precisely controlled by selecting a proper input VG pulse for programming and erasing. It should be noted that the large conductance difference between the programming state and the erasing state was beneficial for multi-level data storage, which holds significant promise for the development of high-performance memory devices. In order to further evaluate the memory performance of the omega-shaped ferroelectric MT, the evolution of its transfer curves was systematically investigated by varying both the time duration and the amplitude of the input VG pulse for erasing. Fig. 2f shows the transfer curves measured after application of an erasing VG pulse of 18 V for a time duration ranging from 0.1 s to 5 s. The amplitude and time duration of the programming VG pulse were fixed to þ18 V and 1 s, respectively. As the time duration for erasing increased from 0.1 s to 5 s, VTH in the erasing state shifted negatively. This result was explained by improved dipole alignment through domain sideway growth [41]. The memory window was controlled by varying the time duration of the erasing VG pulse. However, the current levels at VG ¼ 0 V were not distinguishable, even though the time duration was increased by a factor of 50. Next, the evolution of the transfer curves was also measured by varying the amplitude of the erasing VG pulse while keeping the time duration constant at 1 s (Fig. 2g). When a more negative VG pulse was applied to the gate electrode for erasing, the transfer curve shifted negatively. When a positive VG pulse of þ18 V was applied for programming, the transfer curve shifted to the positive VG direction. Fig. 2h shows ID at VG ¼ 0 V for the MT as a function of the erasing voltage (10, 13, 15, and 18 V). With increasing the erasing voltage from 10 V to 18 V, ID at VG ¼ 0 V changed from 1.1 109 A to 5.2 106 A. A large on-off current ratio exceeding 105 at VG ¼ 0 V was obtained between the programming (þ18 V) and erasing (18 V) states, which enabled a current reading margin exceeding one order of magnitude between each level in five
different states. Both the memory window and the current levels in the erasing state (VG ¼ 0 V) could be controlled by varying the amplitude of the erasing VG pulse (Fig. 2f). These results indicated that multi-level data storage was possible if precise input VG pulses for programming or erasing were applied to the gate electrode. In addition, the mechanical flexibility of our device was confirmed by measuring the memory window under application of the tensile strain of 1% as shown in Fig. 2i. Fig. 3 shows the different operation regimes of the flexible 1T1T FeRAM cell and the corresponding sequences of VBL and VWL. As indicated in Fig. 1d, VWLs of 10 V and þ10 V applied to the word line were used to select the writing and reading operations, respectively. Fig. 3b shows the sequence of the VBL pulse for multiple programming and erasing operations. The VBL pulse duration for writing was 1 s. When the VWL pulse (10 V) was applied, the CT turned on. At the same time, the VBL pulse was applied to the bit line, and it was transferred to the MT. In this case, both the programming and the erasing processes were conducted. In contrast, the readout process of the data written by VBL was conducted when VWL was switched to þ10 V; thus, the CT turned off. Fig. 3c shows the dynamic response of the FeRAM cell. Five different VBL pulses (i.e., 18, 15, 13, and 10 V for erasing and þ18 V for programming) were applied to the bit line with a VWL pulse of 10 V. The stored data were then read out at VWL ¼ þ10 V. The readout current of the FeRAM cell showed five distinct levels. The readout current increased stepwise as VBL increased from 18 V to þ18 V. As seen from the yellow shaded area in Fig. 3, the readout current of the memory cell was not affected by the VBL pulse, because the CT was turned off (VWL ¼ þ10 V); this indicates that the writing and reading processes were separated through the 1T1T architecture, in which the CT was integrated with the MT. After one measurement cycle, the readout current was recorded again by repeating the same sequences of VBL and VWL. The five levels of current retention
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Fig. 3. Dynamic response of SWCNT-based FeRAM cell. (a) VWL, (b) VBL, and (c) drain current as functions of time. (A colour version of this figure can be viewed online.)
were reliable and repeatable. Finally, the retention and cyclic endurance properties of the multi-level 1T1T FeRAM cell were investigated [42e46]. To evaluate the retention time in different conductance states, the memory cell was triggered through application of four different erasing voltages of 18, 15, 13, and 10 V and one programming voltage of þ18 V at the bit line with a time duration of 1 s. At the same time, VWL of 10 V was applied. As shown in Fig. 4a, the readout current was monitored as a function of time under VWL ¼ þ10 V. The readout current levels could be maintained for 104 s and no obvious current degradation was observed, indicating highly stable and multi-level data retention capability. Importantly, the large conductance difference between the erasing (18 V) and programming (þ18 V) states (greater than 105) yielded a current reading margin exceeding one order of magnitude between the two states. To measure the dynamic switching stability of the FeRAM cell, the readout currents in five different states were recorded during repeated programming and erasing cycles, as shown in Fig. 4b. Reliable and rewritable operation was observed over 1000 cycles. Consequently, the separation between the writing and reading processes of our FeRAM cell afforded highly reliable data retention with good repeatability and cyclic endurance. 4. Conclusion In summary, we developed a flexible 1T1T FeRAM cell in which the CT was integrated with the MT. An inkjet-printed SWCNT semiconductor was utilized as the active channel layer of both the transistors. The MT was fabricated through inkjet printing of a P(VDF-TrFE) droplet on top of the SWCNT channel layer. The 1T1T architecture facilitated complete separation of the writing (programming and erasing) and reading processes of the memory cell, which afforded nondestructive readout capability. The high programming/erasing current ratio, in excess of 105, enabled five-level data storage. Our FeRAM cell with nondestructive readout capability showed a retention time longer than 104 s and operational stability over 1000 cycles. This work opens up potential avenues for the development of next-generation flexible and printable memory cells.
Fig. 4. (a) Retention time and (b) cyclic endurance properties of SWCNT-based FeRAM cell. (A colour version of this figure can be viewed online.)
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Declaration of competing interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. CRediT authorship contribution statement Seongchan Kim: Investigation, Writing - original draft. Jia Sun: Investigation, Writing - original draft. Yongsuk Choi: Investigation. Dong Un Lim: Investigation. Joohoon Kang: Formal analysis. Jeong Ho Cho: Supervision. Acknowledgments This work was supported by a grant from the Creative Materials Discovery Program (NRF-2019M3D1A1078296) through the National Research Foundation (NRF) of Korea funded by the Ministry of Science and ICT, and the Materials & Components Technology Development Program (20006537, Development of High Performance Insulation Materials for Flexible OLED Display TFT) funded by the Ministry of Trade, Industry & Energy (MOTIE), Korea. References [1] C. Wang, D. Hwang, Z. Yu, K. Takei, J. Park, T. Chen, et al., User-interactive electronic skin for instantaneous pressure visualization, Nat. Mater. 12 (2013) 899e904. [2] R.C. Webb, A.P. Bonifas, A. Behnaz, Y. Zhang, K.J. Yu, H. Cheng, et al., Ultrathin conformal devices for precise and continuous thermal characterization of human skin, Nat. Mater. 12 (2013) 938e944. [3] R. Cheng, S. Jiang, Y. Chen, Y. Liu, N. Weiss, H.C. Cheng, et al., Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics, Nat. Commun. 5 (2014) 5143. [4] D. Akinwande, N. Petrone, J. Hone, Two-dimensional flexible nanoelectronics, Nat. Commun. 5 (2014) 5678. [5] S.C. Mannsfeld, B.C. Tee, R.M. Stoltenberg, C.V. Chen, S. Barman, B.V. Muir, et al., Highly sensitive flexible pressure sensors with microstructured rubber dielectric layers, Nat. Mater. 9 (2010) 859e864. [6] S.T. Han, Y. Zhou, B. Chen, C. Wang, L. Zhou, Y. Yan, et al., Hybrid flexible resistive random access memory-gated transistor for novel nonvolatile data storage, Small 12 (2016) 390e396. [7] Q.A. Vu, H. Kim, V.L. Nguyen, U.Y. Won, S. Adhikari, K. Kim, et al., A high-on/ off-ratio floating-gate memristor array on a flexible substrate via CVD-grown large-area 2D layer stacking, Adv. Mater. 29 (2017), 1703363. [8] D. Son, J.H. Koo, J.K. Song, J. Kim, M. Lee, H.J. Shim, Stretchable carbon nanotube charge-trap floating-gate memory, ACS Nano 9 (2015) 5585e5593. [9] S.W. Hung, T.T.J. Wang, L.W. Chu, L.J. Chen, Orientation-dependent roomtemperature ferromagnetism of FeSi nanowires and applications in nonvolatile memory devices, J. Phys. Chem. C 115 (2011) 15592e15597. [10] T. Sekitani, T. Yokota, U. Zschieschang, H. Klauk, S. Bauer, K. Takeuchi, et al., Organic nonvolatile memory transistors for flexible sensor arrays, Science 326 (2009) 1516e1519. [11] S.K. Hwang, I. Bae, R.H. Kim, C. Park, Flexible non-volatile ferroelectric polymer memory with gate-controlled multilevel operation, Adv. Mater. 24 (2012) 5910e5914. [12] S.T. Han, Y. Zhou, V.A. Roy, Towards the development of flexible non-volatile memories, Adv. Mater. 25 (2013) 5425e5449. [13] Y. Li, W. Sui, J.C. Li, Interfacial effects on resistive switching of flexible polymer thin films embedded with TiO2 nanoparticles, J. Phys. Chem. C 121 (2017) 7944e7950. [14] K.C. Kwon, M.J. Song, K.H. Kwon, H.V. Jeoung, D.W. Kim, G.S. Lee, et al., Nanoscale CuO solid-electrolyte-based conductive-bridging-random-accessmemory cell operating multi-level-cell and 1selector1resistor, J. Mater. Chem. C 3 (2015) 9540e9550. [15] K.H. Lee, G. Lee, K. Lee, M.S. Oh, S. Im, S.-M. Yoon, High-mobility nonvolatile memory thin-film transistors with a ferroelectric polymer interfacing ZnO and pentacene channels, Adv. Mater. 21 (2009) 4287e4291. [16] Y. Zheng, G.X. Ni, C.T. Toh, C.Y. Tan, K. Yao, B. Ozyilmaz, Graphene field-effect transistors with ferroelectric gating, Phys. Rev. Lett. 105 (2010), 166602. [17] C. Ko, Y. Lee, Y. Chen, J. Suh, D. Fu, A. Suslu, et al., Ferroelectrically gated atomically thin transition-metal dichalcogenides as nonvolatile memory, Adv. Mater. 28 (2016) 2923e2930. [18] J.H. Lee, B. Jeong, S.H. Cho, E.H. Kim, C. Park, Non-volatile polymer electroluminescence programmable with ferroelectric field-induced charge injection gate, Adv. Funct. Mater. 26 (2016) 5391e5399.
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Carbon journal homepage: www.elsevier.com/locate/carbon
Carbon nanotube ferroelectric random access memory cell based on omega-shaped ferroelectric gate Seongchan Kim a, 1, Jia Sun c, 1, Yongsuk Choi d, Dong Un Lim d, Joohoon Kang b, Jeong Ho Cho d, * a
SKKU Advanced Institute of Nanotechnology (SAINT), Suwon, 16419, South Korea School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon, 16419, South Korea Hunan Key Laboratory for Super Microstructure and Ultrafast Process, School of Physics and Electronics, Central South University, Changsha, Hunan, 410083, PR China d Department of Chemical and Biomolecular Engineering, Yonsei University, Seoul, 03722, South Korea b c
a r t i c l e i n f o
a b s t r a c t
Article history: Received 31 December 2019 Received in revised form 16 February 2020 Accepted 17 February 2020 Available online 18 February 2020
This paper presents a flexible ferroelectric random access memory (FeRAM) cell with a one-transistorone-transistor structure. The FeRAM cell was composed of a control transistor (CT) and an omegashaped ferroelectric memory transistor (MT). An inkjet-printed single-walled carbon nanotube (SWCNT) were utilized as a semiconducting channel layers of both transistors. An omega-shaped ferroelectric gate was formed through inkjet-printing of poly(vinylidene fluoride-co-trifluoroethylene) (P(VDF-TrFE)) onto the SWCNT channel of the MT. The gate electrode of the CT was electrically connected to the drain electrode of the MT, while the gate electrode of the MT was connected to the source electrode of the CT. The 1T1T architecture enabled the separation of the writing and reading operations, which afforded nondestructive readout capability. The desired multi-level conductance states could be deterministically controlled by tuning the dipole polarization in the ferroelectric P(VDF-TrFE) layer of the MT. The resulting FeRAM cell showed excellent device performances such as five-level data storage, a high programming/erasing current ratio (>105), a retention time (>104 s), and operational stability (>1000 cycles). The 1T1T FeRAM cell fabricated by inkjet printing technique opens up new opportunities for realizing future large-area flexible memory cells. © 2020 Elsevier Ltd. All rights reserved.
Keywords: Single-walled carbon nanotube Transistor Memory One-transistor-one-transistor FeRAM Nondestructive readout
1. Introduction Because of the rapid development of flexible electronics, they are now required to include flexible devices integrated into all-inone systems [1e5]. Memory devices are the most fundamental components of modern electronic circuits and systems for longterm data storage [6e9]. Currently, there is a strong demand for the fabrication of high-performance flexible memory devices via cost-effective manufacturing processes, which have great potential for use in various applications including wearable electronics, artificial electronic skins, mobile computing devices, flexible displays, and humanemachine interfaces [10e13]. From the viewpoint of device architecture, memory devices can be classified into
* Corresponding author. E-mail address: [email protected] (J.H. Cho). 1 S. Kim and J. Sun contributed equally to this work as the first author. https://doi.org/10.1016/j.carbon.2020.02.044 0008-6223/© 2020 Elsevier Ltd. All rights reserved.
resistor-type, capacitor-type, and transistor-type memories [12,14]. Among the existing memory technologies, ferroelectric field-effect transistor (FeFET)-based memories, in which the gate dielectric is substituted with a ferroelectric layer, have attracted tremendous attention for use in next-generation memory chips [15e19]. Such a device is operated via a change in the ferroelectric polarization state induced through application of a sufficient external gate electric field and consequent generation of a surface charge on the ferroelectric film and accumulation of opposite-sign carriers in the channel layer; such devices offer exceptional advantages of low power consumption, nonvolatility, high speed, and multi-level data storage [15e19]. In particular, organic poly(vinylidene fluoride-cotrifluoroethylene) (P(VDF-TrFE)) is a promising candidate for flexible memory devices because of its solution processability and ease of deposition at low temperatures [20e23]. Use of conventional ferroelectric random access memory (FeRAM) technology with one-transistor-one-capacitor architecture is considered an adequate approach for the realization of high-performance
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memory units [24e26]. However, the conventional FeRAM usually suffers from unavoidable device-to-device interference during memory access operation when the devices are integrated on a large scale [24e27]. As a result of this fatal drawback, the writing operation of a target device results in programming of its neighboring device. Thus, the writing and reading processes should be completely separated in order to ensure nondestructive readout operation. A highly efficient and low-cost fabrication procedure that does not involve complicated lithography processes is strongly required for realizing a high-performance flexible memory cell with a ferroelectric P(VDF-TrFE) gate. Printed electronics have attracted much attention because they offer advantages such as direct patterning of electronic components, cost-effectiveness, and largearea fabrication [28e31]. The main challenge in the use of printed electronics is to develop high-performance inks for semiconducting channel materials, since the semiconductor is the core of electronic devices. Because single-walled carbon nanotube (SWCNT) offer advantages of ease of use as printable inks, high mobility, excellent physical and chemical properties, and environmental stability, they have emerged as favorable channel layer materials for transistortype memory devices [32e37]. Importantly, the network structure of one-dimensional SWCNT as the channel layer permits the fabrication of an omega-shaped ferroelectric gate through incorporation of an organic P(VDF-TrFE) layer [38,39]. Such a creative device structure can greatly simplify the manufacturing process of ferroelectric memory devices. In this study, we developed a flexible one-transistor-onetransistor (1T1T) FeRAM cell with nondestructive readout capability. The FeRAM cell was integrated onto a plastic substrate by connecting a ferroelectric memory transistor (MT) with a control transistor (CT). The SWCNT was inkjet-printed to serve the semiconducting channel layers of both the CT and the MT, and P(VDFTrFE) was inkjet-printed on top of the SWCNT layer to form an omega-shaped ferroelectric gate of the MT. The resulting flexible FeRAM cell provided exceptional advantages of simple fabrication through inkjet printing and separation of the writing and reading processes for nondestructive readout. The device exhibited excellent memory performances, such as a high programming/erasing current ratio, long retention time, and multi-bit information storage capability. This work paves the way toward the realization of high-performance nonvolatile FeRAM cells for application to flexible printed electronics. 2. Methods The flexible 1T1T FeRAM cell was fabricated on a polyethylene naphthalate (PEN) substrate. The substrates was cleaned sequentially with deionized water, acetone, and isopropanol and then dried with N2 gas. First, 40-nm-thick indium tin oxide (ITO) bottom-gate electrode patterns were deposited onto the substrate by RF sputtering through a metallic shadow mask. The Al2O3 layer with thickness of 50 nm was then deposited onto the PEN substrate with predefined gate electrodes via ALD. As mentioned above, Au patterns with a thickness of 40 nm were deposited by thermal evaporation via a shadow mask, which were used as the source and drain electrodes of both the CT and the MT. Highly purified semiconducting SWCNT (purity > 98%) was purchased from SigmaAldrich, which were used as printable ink. The SWCNT was printed onto the channel region by using an inkjet printer (DMP2850, Dimatix-Fujifilm, Inc.). The water-based SWCNT ink was printed onto the predefined channel area at a printing speed of 3 mm/s. The printing times were controlled for achieving the desired density of SWCNT. The channel length (L) and width (W) were 1000 and 100 mm, respectively. Finally, 2 wt% solution of P(VDF-TrFE)
dissolved in acetone was inkjet-printed on top of the SWCNT channel layer, and the resultant layer served as an omega-shaped ferroelectric gate of the MT. All the device performances were measured using Keithley 2400 and 236 source/measure units at room temperature under dark conditions. 3. Results and discussion In the 1T1T FeRAM cell, the MT was utilized as a data storage unit and the CT was utilized to control the access of the MT. Fig. 1a shows a schematic of the flexible 1T1T FeRAM cell based on the inkjet-printed SWCNT and P(VDF-TrFE). First, a flexible polyethylene naphthalate (PEN) was used as a substrate for the memory cell and 40-nm-thick indium tin oxide (ITO) bottom-gate electrode patterns were deposited onto the substrate by radio-frequency (RF) sputtering through a metallic shadow mask. A 50-nm-thick Al2O3 gate dielectric was deposited onto the PEN substrate with predefined gate electrodes via the atomic layer deposition (ALD) technique. The specific capacitance of the Al2O3 layer was around 132 nFcm2. As mentioned above, Au patterns with a thickness of 40 nm were deposited by thermal evaporation through a shadow mask, which were used as the source and drain electrodes of both the CT and the MT. Highly purified SWCNT was used as printable semiconductor ink [40]. Printing of the SWCNT onto the channel region was performed using a commercial inkjet printer (Fig. 1b). Finally, the solution of P(VDF-TrFE) dissolved in acetone was inkjetprinted on top of the SWCNT channel layer, and the resultant layer served as an omega-shaped ferroelectric gate of the MT (Fig. 1c). Fig. 1d shows the optical top-view image of the flexible 1T1T FeRAM cell fabricated onto the plastic substrate. The operation of the omega-shaped ferroelectric MT proposed in this study is different from that of the conventional ferroelectric MT with the ferroelectric layer serving as a gate dielectric layer. The operation mechanism of the proposed MT is explained schematically in Fig. 1e. When a positive gate pulse was applied to the back gate, the electrostatic field gradient created by the gate terminal resulted in an upward polarization of HeF dipoles in the ferroelectric layer. In this case, the positive H dipoles (dþ) were aligned in the upward direction, whereas the negative F dipoles (d) were aligned in the downward direction; the latter consequently came into direct contact with the SWCNT surface, which resulted in the accumulation of holes in the SWCNT channel and induced the “programming state” of the p-type SWCNT transistors. The nonvolatility of the HeF dipole polarization resulted in the accumulation of an equal number of holes within the SWCNT channel, which enabled the current to remain unchanged even after the removal of the gate pulse [38,39]. The persistent dipole polarization afforded a long-term nonvolatile memory property. In contrast, a negative gate pulse induced the opposite polarization of the HeF dipoles in the ferroelectric layer, which resulted in the depletion of holes in the SWCNT channel and consequently induced the “erasing state” of the p-type SWCNT transistors. Flexible 1T1T FeRAM cells were fabricated on the basis of the operation mechanism of the omega-shaped ferroelectric MT. Fig. 1f shows a circuit diagram of the FeRAM cell. The memory cell consisted of a bottom-gate CT and an omega-shaped ferroelectric MT, in which, the gate electrode of the CT was electrically connected to the drain electrode of the MT, while the gate electrode of the MT was connected to the source electrode of the CT. The 1T1T architecture was beneficial for controlling the writing and reading processes of the MT using the CT, and thus, these two distinct processes were completely separated. Fig. 1g shows the writing (programming and erasing) and reading voltages of the flexible 1T1T FeRAM cell. When a negative voltage (10 V) was applied at the word line (VWL), the CT of the cell turned on. As a consequence, the voltage
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Fig. 1. (a) Schematic device structure of SWCNT-based FeRAM cell consisting of CT and ferroelectric MT. (b, c) AFM image of inkjet-printed SWCNT (b) and PVDF-TrFE (c) layers. (d) Optical top-view image of SWCNT-based FeRAM cell. (e) Operation mechanism of omega-shaped ferroelectric MT. (f) Circuit diagram of SWCNT-based FeRAM cell. (g) Table describing writing (programming and erasing) and reading processes. (A colour version of this figure can be viewed online.)
applied at the bit line (VBL) was transferred to the gate of the MT and the conductance of the MT changed correspondingly. In the writing process, VBL of þ18 V and 18 V were applied for programming and erasing, respectively, of the MT. These input values of VBL were stored in the MT. In the reading process, however, a positive voltage (þ10 V) was applied at the word line, which caused the CT to turn off. The channel conductance of the MT was not affected by the input voltage VBL. Resultingly, the 1T1T FeRAM cell architecture enabled the separation of the writing and reading operations, which, in turn, afforded nondestructive readout capability. First, the electrical properties of the SWCNT-based CT and MT were investigated. Fig. 2a displays the representative transfer characteristics of the CT when the gate voltage (VG) was swept in a closed loop: from þ10 V to 10 V back to þ10 V. The drain voltage (VD) was fixed to 10 V. The SWCNT transistors exhibited p-type conduction with an on-off current ratio exceeding 105, which provided sufficient current modulation to control the access of the MT. According to the standard transistor equation, the hole mobility in the saturation region was calculated to be as high as 6.4 cm2 V1s1. No significant hysteresis between the forward and reverse sweeps was observed, but a slight hysteresis may have originated from the shallow charge traps inside the SWCNT or at the SWCNTeAl2O3 interface. In contrast, a large hysteresis window was observed in the transfer curves of the SWCNT-based MT (Fig. 2b). Because of the electric-field-induced dipole orientation in the omega-shaped ferroelectric P(VDF-TrFE) layer, the transfer curves showed counterclockwise hysteresis. Upon sweeping of VG from the positive to the negative voltage direction, the dipoles in the omega-shaped ferroelectric P(VDF-TrFE) layer were aligned in
the upward direction. Such an alignment caused the negative dipoles to point to the SWCNT layer, which resulted in the accumulation of holes in the SWCNT channel layer and thus caused an increased drain current (ID). Sweeping of VG back from the negative to the positive voltage direction caused the polarized dipole in the ferroelectric P(VDF-TrFE) layer to gradually switch with the positive dipoles pointing to the SWCNT layer. During this process, the applied VG was partially screened by the electric field generated by the dipole formed in the ferroelectric P(VDF-TrFE) layer. The lowered effective VG resulted in the threshold voltage (VTH) shift to negative voltage direction during the reverse sweep. The electricfield-induced dipole orientation in the omega-shaped ferroelectric P(VDF-TrFE) layer during VG sweep was summarized in Fig. 2c. Note that simple inkjet printing of a single P(VDF-TrFE) droplet onto the SWCNT channel provided memory functionality to the SWCNT transistor, which simplified the steps of the separate fabrications of the CT and MT and the subsequent electrical connection between them. It was obviously observed that the hysteresis loop became enlarged with an increase in the sweep range of VG (Fig. 2d), while the off-current level remained as low as 109 A. The difference in VTH between the forward and reverse sweeps is defined as a memory window. To evaluate the data storage capability of the MT, the memory window was extracted; the corresponding data are plotted in Fig. 2e. The memory window was measured to be around 9.5 V for the VG sweep range of ±10 V. The memory window increased to 13.8 V with increasing the VG sweep range to ±18 V because of the stronger dipole polarization in the P(VDF-TrFE) layer. Consequently, the dipole polarization in the omega-shaped ferroelectric P(VDF-TrFE) layer and the resulting memory properties
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Fig. 2. (a) Semi-log scale plot of transfer curves of CT of SWCNT-based FeRAM cell. (b) Hysteresis behavior of MT of 1T1T memory cell as a function of VG sweep ranges of ±10 V and ±18 V. (c) Electric-field-induced dipole orientation in the omega-shaped ferroelectric P(VDF-TrFE) layer during VG sweep. (d) Linear scale plot of transfer curves of MT of 1T1T memory cell as a function of VG sweep ranges of ±10 V and ±18 V. (e) Memory window of transfer curves as a function of VG sweep range. (f) Shift in transfer curves after application of various erasing VG pulses for 1 s. (g) Shift in transfer curves after application of programming VG of 20 V for various time durations. (h) Drain current at VG ¼ 0 V as a function of erasing voltage. (i) Comparison of the memory window according to tensile strains (0% and 1%).
could be precisely controlled by selecting a proper input VG pulse for programming and erasing. It should be noted that the large conductance difference between the programming state and the erasing state was beneficial for multi-level data storage, which holds significant promise for the development of high-performance memory devices. In order to further evaluate the memory performance of the omega-shaped ferroelectric MT, the evolution of its transfer curves was systematically investigated by varying both the time duration and the amplitude of the input VG pulse for erasing. Fig. 2f shows the transfer curves measured after application of an erasing VG pulse of 18 V for a time duration ranging from 0.1 s to 5 s. The amplitude and time duration of the programming VG pulse were fixed to þ18 V and 1 s, respectively. As the time duration for erasing increased from 0.1 s to 5 s, VTH in the erasing state shifted negatively. This result was explained by improved dipole alignment through domain sideway growth [41]. The memory window was controlled by varying the time duration of the erasing VG pulse. However, the current levels at VG ¼ 0 V were not distinguishable, even though the time duration was increased by a factor of 50. Next, the evolution of the transfer curves was also measured by varying the amplitude of the erasing VG pulse while keeping the time duration constant at 1 s (Fig. 2g). When a more negative VG pulse was applied to the gate electrode for erasing, the transfer curve shifted negatively. When a positive VG pulse of þ18 V was applied for programming, the transfer curve shifted to the positive VG direction. Fig. 2h shows ID at VG ¼ 0 V for the MT as a function of the erasing voltage (10, 13, 15, and 18 V). With increasing the erasing voltage from 10 V to 18 V, ID at VG ¼ 0 V changed from 1.1 109 A to 5.2 106 A. A large on-off current ratio exceeding 105 at VG ¼ 0 V was obtained between the programming (þ18 V) and erasing (18 V) states, which enabled a current reading margin exceeding one order of magnitude between each level in five
different states. Both the memory window and the current levels in the erasing state (VG ¼ 0 V) could be controlled by varying the amplitude of the erasing VG pulse (Fig. 2f). These results indicated that multi-level data storage was possible if precise input VG pulses for programming or erasing were applied to the gate electrode. In addition, the mechanical flexibility of our device was confirmed by measuring the memory window under application of the tensile strain of 1% as shown in Fig. 2i. Fig. 3 shows the different operation regimes of the flexible 1T1T FeRAM cell and the corresponding sequences of VBL and VWL. As indicated in Fig. 1d, VWLs of 10 V and þ10 V applied to the word line were used to select the writing and reading operations, respectively. Fig. 3b shows the sequence of the VBL pulse for multiple programming and erasing operations. The VBL pulse duration for writing was 1 s. When the VWL pulse (10 V) was applied, the CT turned on. At the same time, the VBL pulse was applied to the bit line, and it was transferred to the MT. In this case, both the programming and the erasing processes were conducted. In contrast, the readout process of the data written by VBL was conducted when VWL was switched to þ10 V; thus, the CT turned off. Fig. 3c shows the dynamic response of the FeRAM cell. Five different VBL pulses (i.e., 18, 15, 13, and 10 V for erasing and þ18 V for programming) were applied to the bit line with a VWL pulse of 10 V. The stored data were then read out at VWL ¼ þ10 V. The readout current of the FeRAM cell showed five distinct levels. The readout current increased stepwise as VBL increased from 18 V to þ18 V. As seen from the yellow shaded area in Fig. 3, the readout current of the memory cell was not affected by the VBL pulse, because the CT was turned off (VWL ¼ þ10 V); this indicates that the writing and reading processes were separated through the 1T1T architecture, in which the CT was integrated with the MT. After one measurement cycle, the readout current was recorded again by repeating the same sequences of VBL and VWL. The five levels of current retention
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Fig. 3. Dynamic response of SWCNT-based FeRAM cell. (a) VWL, (b) VBL, and (c) drain current as functions of time. (A colour version of this figure can be viewed online.)
were reliable and repeatable. Finally, the retention and cyclic endurance properties of the multi-level 1T1T FeRAM cell were investigated [42e46]. To evaluate the retention time in different conductance states, the memory cell was triggered through application of four different erasing voltages of 18, 15, 13, and 10 V and one programming voltage of þ18 V at the bit line with a time duration of 1 s. At the same time, VWL of 10 V was applied. As shown in Fig. 4a, the readout current was monitored as a function of time under VWL ¼ þ10 V. The readout current levels could be maintained for 104 s and no obvious current degradation was observed, indicating highly stable and multi-level data retention capability. Importantly, the large conductance difference between the erasing (18 V) and programming (þ18 V) states (greater than 105) yielded a current reading margin exceeding one order of magnitude between the two states. To measure the dynamic switching stability of the FeRAM cell, the readout currents in five different states were recorded during repeated programming and erasing cycles, as shown in Fig. 4b. Reliable and rewritable operation was observed over 1000 cycles. Consequently, the separation between the writing and reading processes of our FeRAM cell afforded highly reliable data retention with good repeatability and cyclic endurance. 4. Conclusion In summary, we developed a flexible 1T1T FeRAM cell in which the CT was integrated with the MT. An inkjet-printed SWCNT semiconductor was utilized as the active channel layer of both the transistors. The MT was fabricated through inkjet printing of a P(VDF-TrFE) droplet on top of the SWCNT channel layer. The 1T1T architecture facilitated complete separation of the writing (programming and erasing) and reading processes of the memory cell, which afforded nondestructive readout capability. The high programming/erasing current ratio, in excess of 105, enabled five-level data storage. Our FeRAM cell with nondestructive readout capability showed a retention time longer than 104 s and operational stability over 1000 cycles. This work opens up potential avenues for the development of next-generation flexible and printable memory cells.
Fig. 4. (a) Retention time and (b) cyclic endurance properties of SWCNT-based FeRAM cell. (A colour version of this figure can be viewed online.)
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Declaration of competing interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. CRediT authorship contribution statement Seongchan Kim: Investigation, Writing - original draft. Jia Sun: Investigation, Writing - original draft. Yongsuk Choi: Investigation. Dong Un Lim: Investigation. Joohoon Kang: Formal analysis. Jeong Ho Cho: Supervision. Acknowledgments This work was supported by a grant from the Creative Materials Discovery Program (NRF-2019M3D1A1078296) through the National Research Foundation (NRF) of Korea funded by the Ministry of Science and ICT, and the Materials & Components Technology Development Program (20006537, Development of High Performance Insulation Materials for Flexible OLED Display TFT) funded by the Ministry of Trade, Industry & Energy (MOTIE), Korea. References [1] C. Wang, D. Hwang, Z. Yu, K. Takei, J. Park, T. Chen, et al., User-interactive electronic skin for instantaneous pressure visualization, Nat. Mater. 12 (2013) 899e904. [2] R.C. Webb, A.P. Bonifas, A. Behnaz, Y. Zhang, K.J. Yu, H. Cheng, et al., Ultrathin conformal devices for precise and continuous thermal characterization of human skin, Nat. Mater. 12 (2013) 938e944. [3] R. Cheng, S. Jiang, Y. Chen, Y. Liu, N. Weiss, H.C. Cheng, et al., Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics, Nat. Commun. 5 (2014) 5143. [4] D. Akinwande, N. Petrone, J. Hone, Two-dimensional flexible nanoelectronics, Nat. Commun. 5 (2014) 5678. [5] S.C. Mannsfeld, B.C. Tee, R.M. Stoltenberg, C.V. Chen, S. Barman, B.V. Muir, et al., Highly sensitive flexible pressure sensors with microstructured rubber dielectric layers, Nat. Mater. 9 (2010) 859e864. [6] S.T. Han, Y. Zhou, B. Chen, C. Wang, L. Zhou, Y. Yan, et al., Hybrid flexible resistive random access memory-gated transistor for novel nonvolatile data storage, Small 12 (2016) 390e396. [7] Q.A. Vu, H. Kim, V.L. Nguyen, U.Y. Won, S. Adhikari, K. Kim, et al., A high-on/ off-ratio floating-gate memristor array on a flexible substrate via CVD-grown large-area 2D layer stacking, Adv. Mater. 29 (2017), 1703363. [8] D. Son, J.H. Koo, J.K. Song, J. Kim, M. Lee, H.J. Shim, Stretchable carbon nanotube charge-trap floating-gate memory, ACS Nano 9 (2015) 5585e5593. [9] S.W. Hung, T.T.J. Wang, L.W. Chu, L.J. Chen, Orientation-dependent roomtemperature ferromagnetism of FeSi nanowires and applications in nonvolatile memory devices, J. Phys. Chem. C 115 (2011) 15592e15597. [10] T. Sekitani, T. Yokota, U. Zschieschang, H. Klauk, S. Bauer, K. Takeuchi, et al., Organic nonvolatile memory transistors for flexible sensor arrays, Science 326 (2009) 1516e1519. [11] S.K. Hwang, I. Bae, R.H. Kim, C. Park, Flexible non-volatile ferroelectric polymer memory with gate-controlled multilevel operation, Adv. Mater. 24 (2012) 5910e5914. [12] S.T. Han, Y. Zhou, V.A. Roy, Towards the development of flexible non-volatile memories, Adv. Mater. 25 (2013) 5425e5449. [13] Y. Li, W. Sui, J.C. Li, Interfacial effects on resistive switching of flexible polymer thin films embedded with TiO2 nanoparticles, J. Phys. Chem. C 121 (2017) 7944e7950. [14] K.C. Kwon, M.J. Song, K.H. Kwon, H.V. Jeoung, D.W. Kim, G.S. Lee, et al., Nanoscale CuO solid-electrolyte-based conductive-bridging-random-accessmemory cell operating multi-level-cell and 1selector1resistor, J. Mater. Chem. C 3 (2015) 9540e9550. [15] K.H. Lee, G. Lee, K. Lee, M.S. Oh, S. Im, S.-M. Yoon, High-mobility nonvolatile memory thin-film transistors with a ferroelectric polymer interfacing ZnO and pentacene channels, Adv. Mater. 21 (2009) 4287e4291. [16] Y. Zheng, G.X. Ni, C.T. Toh, C.Y. Tan, K. Yao, B. Ozyilmaz, Graphene field-effect transistors with ferroelectric gating, Phys. Rev. Lett. 105 (2010), 166602. [17] C. Ko, Y. Lee, Y. Chen, J. Suh, D. Fu, A. Suslu, et al., Ferroelectrically gated atomically thin transition-metal dichalcogenides as nonvolatile memory, Adv. Mater. 28 (2016) 2923e2930. [18] J.H. Lee, B. Jeong, S.H. Cho, E.H. Kim, C. Park, Non-volatile polymer electroluminescence programmable with ferroelectric field-induced charge injection gate, Adv. Funct. Mater. 26 (2016) 5391e5399.
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