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Card connectors adopt to wide variety of IC memory cards
1970
World abstracts of microelectronics and reliability
technology is undergoing remarkable changes. In the future, ASICs will continue gaining importance as the cores of electronic systems.
Throughput optimized architectural synthesis. CATHERINE H. GEBOTYS. IEEE Transactions on Very Large Scale Inteqration (VLSI) Systems, !(3), 254 (September 1993). This paper presents for the first time an optimization approach to synthesizing DSP-specific architectures which maximize throughput. A new integer programming (IP) model is presented that supports simultaneous scheduling, allocation, and retiming or loop winding. The IP model is used to map a DSP application to a high speed applicationspecific architecture which maximizes throughput given constraints on area and latency. Results show this approach optimally synthesizes architectures that have up to 127/~ihigher throughputs than previously published architectures. This research provides Industry with a DA tool for mapping DSP applications to high performance architectures optimized for throughput. ASIC device technology holds key to rapid progress of LSI technology. TAKEO MAEDA. dEE (Japan), 58 (August 1993). Design rules virtually determine the performance and integration of a VLSI circuit. These rules define the minimum processing dimension in a silicon chip, and they are becoming smaller every year as LSI processing technology progresses. Accordingly, the integration level of the VLSI circuit increases and the switching speed becomes faster than ever before. With these transitions among design rules, DRAM integration levels have improved fourfold during the past three years. Logic LSIs have made the same progress. VLSI architectures for discrete wavelet transforms. KESHAB K. PARHI and TAKAO NISHITANI. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1(2), 19l (June 1993). This paper presents two classes of novel VLSI architectures, referred to as the .folded architecture and the digit-serial architecture, for implementation of one- and twodimensional discrete wavelet transforms. In the one-dimensional folded architecture, the computations of all wavelet levels are folded to the same low-pass and high-pass filters. The number of registers in the folded architecture is minimized by the use of a generalized life time analysis. The converter units are synthesized with minimum number of registers using forward-backward allocation. The advantage of the folded architecture is low latency and its drawbacks are increased hardware area, less than 100~o hardware utilization, and complex routing and interconnection required by the converters used in this architecture. These drawbacks are eliminated in the alternate digit-serial architecture which requires simpler control
circuits, routing, and interconnection, achieves complete hardware utilization, and requires lower power, at the expense of an increase in the system latency and some constraints on the wordlength. In latency-critical applications, we propose the use of the folded architecture. If latency is not so critical, we propose the use of the digit-serial architecture. The use of a combined folded and digit-serial architecture is proposed for implementation of two-dimensional discrete wavelet transforms.
A high-level VLSI design for ultra-dense instruction set computer architectures. OLAF S. SCH()EPK|C Microeleetronics Journal, 24, 497 (1993). At present, typical yon Neumann architectures lose more and more of their performance to the memory system. The main reason for this behaviour is the slow main memory. Even if caches alleviate this problem, an advanced architecture has to be developed to provide instructions to the execution unit very much faster than current architectures are able to. This paper describes an advanced system architecture based on ultra-dense instruction sets to overcome the increasing gap between processor and memory speed. Entropy measurements show great redundancy in RISC instruction streams, and therefore a coding technique which can bet as close as desired to the entropy is required to encode and decode the instruction stream. Encoding has to be done on static code, the code prior to execution, and decoding on dynamic code, the code during execution. A high-level VLSI design to build the system is suggested. Card connectors adopt to wide variety of 1C memory cards. TAKASHI SA1TO. JEE (Japan), 33 (September 1993). IC memory cards are going to grow in applications and demand with the advance of information-oriented home electronics appliances arising from the integration of information, communications and home electric appliances. As their chief characteristics, the cards perform memory functions and exhibit excellent reliability suitable for portable equipment. They do not require drive systems in applied equipment, such as floppy or hard disk drives, making them resistant to mechanical vibrations and easy to reduce in size and weight. An extensible fault-tolerant network architecture. SURANJAN GHOSE et al. Computers Elect Engineering, 19(5), 365 (1993). A simple network architecture, obtained by augmenting a modified binary tree with a few additional edges has been proposed in this paper. The network with N nodes has less than 1.67 N edges and O (log N) diameter. The structure is incrementally extensible and fault-tolerant. A simple self-routing algorithm for message communication under faultfree conditions has been presented. A method for routing under faulty condition has also been discussed.
World abstracts of microelectronics and reliability
technology is undergoing remarkable changes. In the future, ASICs will continue gaining importance as the cores of electronic systems.
Throughput optimized architectural synthesis. CATHERINE H. GEBOTYS. IEEE Transactions on Very Large Scale Inteqration (VLSI) Systems, !(3), 254 (September 1993). This paper presents for the first time an optimization approach to synthesizing DSP-specific architectures which maximize throughput. A new integer programming (IP) model is presented that supports simultaneous scheduling, allocation, and retiming or loop winding. The IP model is used to map a DSP application to a high speed applicationspecific architecture which maximizes throughput given constraints on area and latency. Results show this approach optimally synthesizes architectures that have up to 127/~ihigher throughputs than previously published architectures. This research provides Industry with a DA tool for mapping DSP applications to high performance architectures optimized for throughput. ASIC device technology holds key to rapid progress of LSI technology. TAKEO MAEDA. dEE (Japan), 58 (August 1993). Design rules virtually determine the performance and integration of a VLSI circuit. These rules define the minimum processing dimension in a silicon chip, and they are becoming smaller every year as LSI processing technology progresses. Accordingly, the integration level of the VLSI circuit increases and the switching speed becomes faster than ever before. With these transitions among design rules, DRAM integration levels have improved fourfold during the past three years. Logic LSIs have made the same progress. VLSI architectures for discrete wavelet transforms. KESHAB K. PARHI and TAKAO NISHITANI. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1(2), 19l (June 1993). This paper presents two classes of novel VLSI architectures, referred to as the .folded architecture and the digit-serial architecture, for implementation of one- and twodimensional discrete wavelet transforms. In the one-dimensional folded architecture, the computations of all wavelet levels are folded to the same low-pass and high-pass filters. The number of registers in the folded architecture is minimized by the use of a generalized life time analysis. The converter units are synthesized with minimum number of registers using forward-backward allocation. The advantage of the folded architecture is low latency and its drawbacks are increased hardware area, less than 100~o hardware utilization, and complex routing and interconnection required by the converters used in this architecture. These drawbacks are eliminated in the alternate digit-serial architecture which requires simpler control
circuits, routing, and interconnection, achieves complete hardware utilization, and requires lower power, at the expense of an increase in the system latency and some constraints on the wordlength. In latency-critical applications, we propose the use of the folded architecture. If latency is not so critical, we propose the use of the digit-serial architecture. The use of a combined folded and digit-serial architecture is proposed for implementation of two-dimensional discrete wavelet transforms.
A high-level VLSI design for ultra-dense instruction set computer architectures. OLAF S. SCH()EPK|C Microeleetronics Journal, 24, 497 (1993). At present, typical yon Neumann architectures lose more and more of their performance to the memory system. The main reason for this behaviour is the slow main memory. Even if caches alleviate this problem, an advanced architecture has to be developed to provide instructions to the execution unit very much faster than current architectures are able to. This paper describes an advanced system architecture based on ultra-dense instruction sets to overcome the increasing gap between processor and memory speed. Entropy measurements show great redundancy in RISC instruction streams, and therefore a coding technique which can bet as close as desired to the entropy is required to encode and decode the instruction stream. Encoding has to be done on static code, the code prior to execution, and decoding on dynamic code, the code during execution. A high-level VLSI design to build the system is suggested. Card connectors adopt to wide variety of 1C memory cards. TAKASHI SA1TO. JEE (Japan), 33 (September 1993). IC memory cards are going to grow in applications and demand with the advance of information-oriented home electronics appliances arising from the integration of information, communications and home electric appliances. As their chief characteristics, the cards perform memory functions and exhibit excellent reliability suitable for portable equipment. They do not require drive systems in applied equipment, such as floppy or hard disk drives, making them resistant to mechanical vibrations and easy to reduce in size and weight. An extensible fault-tolerant network architecture. SURANJAN GHOSE et al. Computers Elect Engineering, 19(5), 365 (1993). A simple network architecture, obtained by augmenting a modified binary tree with a few additional edges has been proposed in this paper. The network with N nodes has less than 1.67 N edges and O (log N) diameter. The structure is incrementally extensible and fault-tolerant. A simple self-routing algorithm for message communication under faultfree conditions has been presented. A method for routing under faulty condition has also been discussed.