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Catalyst-free growth of InP nanowires on patterned Si (001) substrate by using GaAs buffer layer
Journal of Crystal Growth 440 (2016) 81–85
Contents lists available at ScienceDirect
Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Catalyst-free growth of InP nanowires on patterned Si (001) substrate by using GaAs buffer layer Shiyan Li, Xuliang Zhou, Xiangting Kong, Mengke Li, Junping Mi, Jiaoqing Pan n Key Laboratory of Semiconductor Materials Science, Institute of Semiconductors, Chinese Academy of Sciences, P.O. Box 912, Beijing 100083, PR China
art ic l e i nf o
a b s t r a c t
Article history: Received 27 August 2015 Received in revised form 18 December 2015 Accepted 22 January 2016 Available online 30 January 2016
The catalyst-free metal organic vapor phase epitaxial growth of InP nanowires on silicon (001) substrate is investigated using selectively grown GaAs buffer layers in V-shaped trenches. A yield up to 70% of nanowires is self-aligned in uncommon 〈112〉 directions under the optimized growth conditions. The evolution mechanism of self-aligned 〈112〉 directions for nanowires is discussed and demonstrated. Using this growth method, we can achieve branched and direction switched InP nanowires by varying the V/III ratio in situ. The structure of the nanowires is characterized by scanning electron microscope and transmission electron microscopy measurements. The crystal structure of the InP nanowires is stackingfaults-free wurtzite with its c axis perpendicular to the nanowire axis. & 2016 Published by Elsevier B.V.
Keywords: A1. Growth models A3. Metal-organic chemical vapor deposition B1. Nanomaterials B1. Semiconducting III–V materials
1. Introduction Integrated III–V nanowires on Si have been praised for combining all of the advantages of III–V semiconductors, such as direct band-gap, high carrier mobility, and advanced band-structure engineering with silicon microelectronics technology [1–3]. Furthermore, Indium Phosphide (InP) is a key building block in III–V heterojunction devices which is widely used in optical communications and high speed integrated circuits. In most cases, heteroepitaxial growth of InP nanowires on Si has been performed by using gold particles as a catalyst in the so-called vapor liquid–solid (VLS) mechanism [4–6]. However, gold is a forbidden element in CMOS processing, as it forms mid-gap electronic states in Si [7], which has a very high solid diffusivity, and it is extremely hard to be removed from the exposed fabrication equipment. Recently, catalyst-free (or self-catalyzed) growth of InP nanowires using in situ deposited In droplets as seeds on Si substrate was reported [8,9]. Nevertheless, there is a need for a more controllable growth scheme for Si (001) substrate. The use of Si (001) oriented substrates is preferable, considering its potential compatibility with processing in standard microelectronics fabrication. In addition, III–V semiconductors when grown in the 〈111〉 B direction often exhibit a high density of stacking faults that can degrade device optical and electrical characteristics. Therefore, the growth of nanowires in other directions (which generally result in defectfree nanowires) is of great interest. n
Corresponding author. E-mail address: [email protected] (J. Pan).
http://dx.doi.org/10.1016/j.jcrysgro.2016.01.020 0022-0248/& 2016 Published by Elsevier B.V.
In this work, we introduce a novel means to nucleate and grow Au-catalyst-free InP nanowires on Si (001) substrate without predeposited In droplets. In this manner, the use of a separate step to apply the nano-catalyst to the surface is avoided. A high quality GaAs buffer layer with two convex {111} B facets was selectively grown in V-shaped trenches to promote the growth of highly uniform, direction control, single-crystal InP nanowires on Si (001) substrates. In addition, by varying the V/III mole ratio in nanowires growth process, we achieved branched and direction switched InP nanowires. This method can also be used in GaAs and InAs nanowires growth but is not in the scope of this letter.
2. Experiment The epitaxy was performed by MOCVD (AIXTRON 200) at a pressure 50 mbar. Triethylgallium (TEGa), trimethylgallium (TMGa) and arsine (AsH3) were used as precursors of GaAs buffer layers. InP nanowires precursors were trimethylindium (TMIn) and phosphorane (PH3). Substrates used for InP nanowires growth were Si (001) substrates patterned with high aspect ratio Vshaped trenches along 〈110〉 direction and fabrication processes for substrates were reported elsewhere [10]. Growth of the InP nanowires on Si substrate was carried out as the following steps. (1) Prior to growth, thermal cleaning in an H2 ambient was carried out at 720 °C to remove the native oxide. While wafers were being cooled from the H2 baking temperature, AsH3 is introduced into the reactor to form one monolayer of As-terminated Si {111} surfaces. (2) GaAs buffer layers were grown by a two-step growth
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method: the low-temperature (400 °C) nucleation layer and hightemperature (630 °C) top layer. (3) After ramped down to the desired temperature, the InP nanowires were deposited by feeding PH3 and TMIn simultaneously. InP nanowires growth was terminated by switching off In supply while maintaining PH3 supply until the substrate was cooled down below 250 °C. The gas-flow and temperature sequence was shown in Fig. 1. Different growth conditions were used in step 3, including growth temperature (range from 380 °C to 450 °C) and V/III ratio (range from 250 to 668). The morphologies of InP nanowires were investigated by a scanning electron microscopy (SEM). The crystal structure of the nanowires was characterized by FEI Tecnai F20 transmission electron microscopes (TEM) operated at 200 kV. For highresolution TEM (HR-TEM) analysis, nanowires were removed from the growth substrate via sonication in ethanol and then drop-cast onto holey carbon grids.
3. Results and discussion
{111} B surfaces [11]. In this inset, InP nanowire started from the bottom consists by GaAs and SiO2 sidewall, and grew along the GaAs {111} facets and extends to few micrometers length. From the sample shown in Fig. 2(a), about 73% nanowires are aligned in 〈1 12〉 directions. As for the growth direction, InP nanowires preferentially grow in the 〈111〉 direction by MOVPE, thus many reported about nanowires growth on Si (111) substrates [12]. When the InP nanowires growth on Si (001) substrate, the angles between the nanowires and the Si substrate are diverse [13]. In this study, we report that the InP nanowires growth direction can be controlled and favor to grow in 〈1 12〉 directions. We explained growth mechanism of 〈1 12〉 favor growth directions by two growth mechanisms: misfit dislocations and mass surface diffusion, as shown schematically in Fig. 3. In the part (a), since there exists a 4.2% difference in the lattice parameters between GaAs (aGaAs¼0.565 nm) and InP (aInP ¼0.587 nm), there will be many {111} type microtwins and stacking faults parallel to the InP/GaAs interface when InP nucleate on GaAs buffer layers (labeled by a dot line in InP nanowires) [14]. These twins/stacking faults can relieve
A top-view SEM image of InP nanowires deposited on patterned Si (001) is shown in Fig. 2(a). The process conditions were 450 °C and a V/III ratio of 250. In this SEM image, most of the nanowires appear as white lines parallel with each other and perpendicular with trenches direction. Fig. 2(b) is a side-view SEM image obtained from [1 10] direction, the nanowires appear vertical to the substrate. Comparing Fig. 2(a) with (b) shows that InP nanowires lie in (1 10) plane. In Fig. 2(c) which is obtained in [110] direction, we can see InP nanowires with two preferential growth directions, both angled 55° from the (001) plane and angled 70° from each other. As mentioned before, the nanowires lie in (1 10) plane, we can conclude that the nanowires elongate along the 〈1 12〉 directions. The lower-left inset shows a magnified detail of Fig. 2(c). As we previously reported, the GaAs buffer layer grown in V-shaped trenches of Si substrates has two convex
Fig. 1. Schematic illustrations of gas-flow and temperature sequence for InP nanowires growth on Si.
Fig. 3. Schematic diagram of the MOCVD growth mechanisms for InP nanowires on Si substrate patterned with V-shaped trenches by using GaAs buffer layer.
Fig. 2. SEM images of InP nanowires growth on patterned Si (001) substrates using GaAs buffer layers. (a) The top view SEM images of InP nanowires (b) A side view SEM image taken on [1 10] direction. (c) A typical SEM image (side view) taken on [110] direction.
S. Li et al. / Journal of Crystal Growth 440 (2016) 81–85
misfit strain between InP and GaAs, which is caused by the formation of a/6 〈112〉 type partial dislocations. Dislocations were considered as “active sites” for growth of nanowires [15]. In our results, those dislocations can effectively reduce the strain energy of InP crystal, therefore the nanowires will be self-aligned in 〈1 12〉 directions parallel with the GaAs {111} surface. Secondly, precursors diffusion effect may play an important role in nanowires growth direction. Precursors transport to the GaAs and SiO2 mask surface, adsorbed on to these surfaces. Once absorbed, the TMIn diffuse across the surfaces until they find an active site for decomposition. The arrows in part (a) labeled the diffusion of the precursors along the SiO2, GaAs and InP surfaces. The diffusion effect of the precursors will be enhanced in [1 10] and [1 12] directions, since the longitudinal size of V-shaped trenches is significantly larger than the width. These diffusion of In species may enhance the nanowires growth aligned in 〈1 12〉 directions along the GaAs {111} surfaces by changing the In droplet shape. Fig. 3(b–d) shows the process of InP nanowires grown in a GaAs {111} surface. Before the InP nanowires growth, the InP nucleation occurs in the GaAs {111} surface with the catalytic effect of In droplet. Since there exists a large lattice mismatch between GaAs and InP, there will be many misfit dislocations in InP nucleation region. Then InP nanowires grow in the [1 12] direction on the GaAs {111} plane under the action of dislocation and precursors diffusion. Due to the finite size of GaAs {111} planes in the trenches, finally, InP nanowires will grow beyond the trench along the initial 〈1 12〉 growth directions. In order to testify the growth mechanism of 〈1 12〉 directions InP nanowires we proposed, we investigated two samples growth in different conditions. Fig. 4(a) shows an InP sample grown at 650 °C with a V/III ratio 668. From the previous study, in this growth parameter, no InP nanowires can be grown via the VLS mechanism. However in this sample, a [1 12] direction InP nanowire was observed. There will be many {111} type microtwins and stacking faults parallel to the InP/GaAs interface when InP nucleate on GaAs buffer layers [14]. Those dislocations can effectively reduce the strain energy of InP crystal and make it easier growth aligned in 〈1 12〉 directions. This observed nanowire may be driven by 〈1 12〉 dislocations in InP films. Fig. 4(b) shows an InP nanowires sample growth in a Si substrate patterned with much larger area ratio of SiO2 mask. The active area of V-shaped trenches for selective growth only occupied a ratio 2.5%. The growth temperature and V/III ratio for InP nanowires are 400 °C and 250, respectively. From the SEM image, a comb-like nanowires array was observed along the [110] direction (the trenches along direction). This improvement of direction controlling ability correspond to the enhancement of the process that in species diffuse along the SiO2 surface due to larger SiO2 mask area. Based on the above discussion, the strain forms stacking faults and dislocations at the GaAs/InP interface and precursors diffusion effect may be the reasons resulting in InP nanowires preferentially grow in the 〈1 12〉 directions. Interestingly, by varying the V/III mole ratio in situ, we can achieve the branched and direction switched nanostructures. The sample was grown at a V/III ratio 334 for 10 min, then, the V/III ratio reduced to 250 by decreased PH3 flow (with a constant TMIn flow) and maintained for 3.3 min. Fig. 5(a) shows a side-view of the nanowires from [1 10] direction. In this view, the backbone nanowires are vertical to the substrate as the previous discussion. We labeled three kinds of nanowires in this graph with dotted lines: straight line, branched and direction switched nanowires. In order to see more detail of those nanowires, we removed the nanowires from the growth substrate via sonication in ethanol and then drop-cast onto a Si substrate. We observed from this sample and a 20% yield kinking nanowires are obtained. In Fig. 5(b), we observed the nanowires branch also may come up a switch in
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Fig. 4. (a) A typical SEM side view image of InP films growth at 650 °C with a GaAs buffer layer in V-shaped trenches. (b) A top view SEM image of InP nanowires growth on Si substrates only with 2.5% trench area for selective growth.
growth direction. In Fig. 5(e), an interesting phenomenon was observed: the nanowires reversible switching of the growth direction in this nanowire. From Fig. 5(b)-(e), we can observe that the angle between the backbone and branch of InP nanowires and the switch angle in nanowires growth direction both are 60°. As reported by Jia Wang etc., using Au droplet as a catalyst growth InP nanowires, they reversibly switch InP nanowires growth between a 〈100〉 and a 〈111〉 direction by varying the indium content of the droplet [16]. In this work, the change of the V/III ratio may influence the shape of the In droplet and this may be the reasons of the nanowires kinking. In addition, with the V/III ratio reduced, there may be In droplet on nanowire backbone and this may lead to a branch nanowire growth. Fig. 6(a) is a SEM image of nanowires backbones which shows the InP nanowire presents a triangular cross-section morphology. To determine the branched nanowires crystal structure, a TEM image was taken with 〈111〉 direction of the electron beam incidence. In the Fig. 6(b), the TEM image shows one single branched InP nanowire with a diameter of 100 nm. As shown in the lower-left inset, the TEM electron diffraction pattern indicated the InP nanowire with pure WZ structure and that the nanowire axis is perpendicular to the c axis of the lattice. This is common for GaN nanowire [17], but very infrequently for InP nanowires. To determine more detail about crystal structure and the mechanism about the formation of branched morphology, high-resolution TEM investigations were conducted for the region of backbone, branched section and crotch edge, of this nanowire. The HRTEM
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Fig. 5. Scanning electron micrographs of branched and direction switched InP nanowires. (a) A cross-section view of the nanowires on [1 10] direction. (b–e) are the SEM images of nanowires removed from the growth substrate via sonication in ethanol and then drop-cast onto a Si substrate. The angle of branched section and direction switch are both 60°.
Fig. 6. TEM and SEM images of single branched InP nanowire (a) A cross-section of InP nanowires backbone (b) A TEM images and diffraction pattern in the [0001] projection. (c–e) are high-resolution TEM images of this nanowire with fast fourier transform.
results are shown in Fig. 6(c)-(e). From these HRTEM images, we find that the crotch edge, backbone and branched section of this nanowire with a single crystalline nature. The insets of Fig. 6(c)– (e) are fast Fourier transform (FFT) of the TEM images, which confirmed the pure WZ crystal structure of the nanowires. Now
we use the [hkil] notation for InP nanowires crystal structure. According to FFT pattern in Fig. 6(c), the interplanar spacing of this nanowire is approximately 2.15 Å for {11 20} planes, corresponding to the expected value of a typical InP WZ structure. The TEM diffraction pattern indicates the nanowire growth in [11 20]
S. Li et al. / Journal of Crystal Growth 440 (2016) 81–85
direction which is equivalent with the 〈1 12〉 orientation in cubic coordinate system. This result is consistent with our discussion in the previous part. By comparing the FFT patterns of Fig. 6(d) and (e) with the pattern in part (b), it shows an epitaxial crystalline relations between the backbone and branch segments of the nanowire. Furthermore, the FFT patterns indicates that the backbone and branch segments aligned in [11 20] and [ 12 10] directions, respectively. These direction of [11 20] and [ 12 10] are equivalent in the hexagonal coordinate system. In addition, no defects and stacking faults were observed at the crotch of this nanowire. More work is needed to be done to well understand this branched nanowire growth mechanism.
4. Conclusion In conclusion, catalyst-free InP nanowires grown by low pressure MOCVD on Si (001) substrate patterned with V-shaped trenches have been reported. Stacking-faults-free pure wurtzite phase nanowires were realized by using selective grown GaAs buffer layers. For growing under the optimized conditions, about 70% of the nanowires self-aligned on 〈1 12〉 directions which were perpendicular with its c axis. This preferable growth direction gave a new understanding about the nanowires growth mechanisms. In addition, our approach shows the possibility of making branched and switching of growth directions in single InP nanowire with proper adjusted V/III ratio in growth process.
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Acknowledgment This work was financially supported by National Science and Technology Major Project (Grant no. 2011ZX02708) in China.
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Contents lists available at ScienceDirect
Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Catalyst-free growth of InP nanowires on patterned Si (001) substrate by using GaAs buffer layer Shiyan Li, Xuliang Zhou, Xiangting Kong, Mengke Li, Junping Mi, Jiaoqing Pan n Key Laboratory of Semiconductor Materials Science, Institute of Semiconductors, Chinese Academy of Sciences, P.O. Box 912, Beijing 100083, PR China
art ic l e i nf o
a b s t r a c t
Article history: Received 27 August 2015 Received in revised form 18 December 2015 Accepted 22 January 2016 Available online 30 January 2016
The catalyst-free metal organic vapor phase epitaxial growth of InP nanowires on silicon (001) substrate is investigated using selectively grown GaAs buffer layers in V-shaped trenches. A yield up to 70% of nanowires is self-aligned in uncommon 〈112〉 directions under the optimized growth conditions. The evolution mechanism of self-aligned 〈112〉 directions for nanowires is discussed and demonstrated. Using this growth method, we can achieve branched and direction switched InP nanowires by varying the V/III ratio in situ. The structure of the nanowires is characterized by scanning electron microscope and transmission electron microscopy measurements. The crystal structure of the InP nanowires is stackingfaults-free wurtzite with its c axis perpendicular to the nanowire axis. & 2016 Published by Elsevier B.V.
Keywords: A1. Growth models A3. Metal-organic chemical vapor deposition B1. Nanomaterials B1. Semiconducting III–V materials
1. Introduction Integrated III–V nanowires on Si have been praised for combining all of the advantages of III–V semiconductors, such as direct band-gap, high carrier mobility, and advanced band-structure engineering with silicon microelectronics technology [1–3]. Furthermore, Indium Phosphide (InP) is a key building block in III–V heterojunction devices which is widely used in optical communications and high speed integrated circuits. In most cases, heteroepitaxial growth of InP nanowires on Si has been performed by using gold particles as a catalyst in the so-called vapor liquid–solid (VLS) mechanism [4–6]. However, gold is a forbidden element in CMOS processing, as it forms mid-gap electronic states in Si [7], which has a very high solid diffusivity, and it is extremely hard to be removed from the exposed fabrication equipment. Recently, catalyst-free (or self-catalyzed) growth of InP nanowires using in situ deposited In droplets as seeds on Si substrate was reported [8,9]. Nevertheless, there is a need for a more controllable growth scheme for Si (001) substrate. The use of Si (001) oriented substrates is preferable, considering its potential compatibility with processing in standard microelectronics fabrication. In addition, III–V semiconductors when grown in the 〈111〉 B direction often exhibit a high density of stacking faults that can degrade device optical and electrical characteristics. Therefore, the growth of nanowires in other directions (which generally result in defectfree nanowires) is of great interest. n
Corresponding author. E-mail address: [email protected] (J. Pan).
http://dx.doi.org/10.1016/j.jcrysgro.2016.01.020 0022-0248/& 2016 Published by Elsevier B.V.
In this work, we introduce a novel means to nucleate and grow Au-catalyst-free InP nanowires on Si (001) substrate without predeposited In droplets. In this manner, the use of a separate step to apply the nano-catalyst to the surface is avoided. A high quality GaAs buffer layer with two convex {111} B facets was selectively grown in V-shaped trenches to promote the growth of highly uniform, direction control, single-crystal InP nanowires on Si (001) substrates. In addition, by varying the V/III mole ratio in nanowires growth process, we achieved branched and direction switched InP nanowires. This method can also be used in GaAs and InAs nanowires growth but is not in the scope of this letter.
2. Experiment The epitaxy was performed by MOCVD (AIXTRON 200) at a pressure 50 mbar. Triethylgallium (TEGa), trimethylgallium (TMGa) and arsine (AsH3) were used as precursors of GaAs buffer layers. InP nanowires precursors were trimethylindium (TMIn) and phosphorane (PH3). Substrates used for InP nanowires growth were Si (001) substrates patterned with high aspect ratio Vshaped trenches along 〈110〉 direction and fabrication processes for substrates were reported elsewhere [10]. Growth of the InP nanowires on Si substrate was carried out as the following steps. (1) Prior to growth, thermal cleaning in an H2 ambient was carried out at 720 °C to remove the native oxide. While wafers were being cooled from the H2 baking temperature, AsH3 is introduced into the reactor to form one monolayer of As-terminated Si {111} surfaces. (2) GaAs buffer layers were grown by a two-step growth
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method: the low-temperature (400 °C) nucleation layer and hightemperature (630 °C) top layer. (3) After ramped down to the desired temperature, the InP nanowires were deposited by feeding PH3 and TMIn simultaneously. InP nanowires growth was terminated by switching off In supply while maintaining PH3 supply until the substrate was cooled down below 250 °C. The gas-flow and temperature sequence was shown in Fig. 1. Different growth conditions were used in step 3, including growth temperature (range from 380 °C to 450 °C) and V/III ratio (range from 250 to 668). The morphologies of InP nanowires were investigated by a scanning electron microscopy (SEM). The crystal structure of the nanowires was characterized by FEI Tecnai F20 transmission electron microscopes (TEM) operated at 200 kV. For highresolution TEM (HR-TEM) analysis, nanowires were removed from the growth substrate via sonication in ethanol and then drop-cast onto holey carbon grids.
3. Results and discussion
{111} B surfaces [11]. In this inset, InP nanowire started from the bottom consists by GaAs and SiO2 sidewall, and grew along the GaAs {111} facets and extends to few micrometers length. From the sample shown in Fig. 2(a), about 73% nanowires are aligned in 〈1 12〉 directions. As for the growth direction, InP nanowires preferentially grow in the 〈111〉 direction by MOVPE, thus many reported about nanowires growth on Si (111) substrates [12]. When the InP nanowires growth on Si (001) substrate, the angles between the nanowires and the Si substrate are diverse [13]. In this study, we report that the InP nanowires growth direction can be controlled and favor to grow in 〈1 12〉 directions. We explained growth mechanism of 〈1 12〉 favor growth directions by two growth mechanisms: misfit dislocations and mass surface diffusion, as shown schematically in Fig. 3. In the part (a), since there exists a 4.2% difference in the lattice parameters between GaAs (aGaAs¼0.565 nm) and InP (aInP ¼0.587 nm), there will be many {111} type microtwins and stacking faults parallel to the InP/GaAs interface when InP nucleate on GaAs buffer layers (labeled by a dot line in InP nanowires) [14]. These twins/stacking faults can relieve
A top-view SEM image of InP nanowires deposited on patterned Si (001) is shown in Fig. 2(a). The process conditions were 450 °C and a V/III ratio of 250. In this SEM image, most of the nanowires appear as white lines parallel with each other and perpendicular with trenches direction. Fig. 2(b) is a side-view SEM image obtained from [1 10] direction, the nanowires appear vertical to the substrate. Comparing Fig. 2(a) with (b) shows that InP nanowires lie in (1 10) plane. In Fig. 2(c) which is obtained in [110] direction, we can see InP nanowires with two preferential growth directions, both angled 55° from the (001) plane and angled 70° from each other. As mentioned before, the nanowires lie in (1 10) plane, we can conclude that the nanowires elongate along the 〈1 12〉 directions. The lower-left inset shows a magnified detail of Fig. 2(c). As we previously reported, the GaAs buffer layer grown in V-shaped trenches of Si substrates has two convex
Fig. 1. Schematic illustrations of gas-flow and temperature sequence for InP nanowires growth on Si.
Fig. 3. Schematic diagram of the MOCVD growth mechanisms for InP nanowires on Si substrate patterned with V-shaped trenches by using GaAs buffer layer.
Fig. 2. SEM images of InP nanowires growth on patterned Si (001) substrates using GaAs buffer layers. (a) The top view SEM images of InP nanowires (b) A side view SEM image taken on [1 10] direction. (c) A typical SEM image (side view) taken on [110] direction.
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misfit strain between InP and GaAs, which is caused by the formation of a/6 〈112〉 type partial dislocations. Dislocations were considered as “active sites” for growth of nanowires [15]. In our results, those dislocations can effectively reduce the strain energy of InP crystal, therefore the nanowires will be self-aligned in 〈1 12〉 directions parallel with the GaAs {111} surface. Secondly, precursors diffusion effect may play an important role in nanowires growth direction. Precursors transport to the GaAs and SiO2 mask surface, adsorbed on to these surfaces. Once absorbed, the TMIn diffuse across the surfaces until they find an active site for decomposition. The arrows in part (a) labeled the diffusion of the precursors along the SiO2, GaAs and InP surfaces. The diffusion effect of the precursors will be enhanced in [1 10] and [1 12] directions, since the longitudinal size of V-shaped trenches is significantly larger than the width. These diffusion of In species may enhance the nanowires growth aligned in 〈1 12〉 directions along the GaAs {111} surfaces by changing the In droplet shape. Fig. 3(b–d) shows the process of InP nanowires grown in a GaAs {111} surface. Before the InP nanowires growth, the InP nucleation occurs in the GaAs {111} surface with the catalytic effect of In droplet. Since there exists a large lattice mismatch between GaAs and InP, there will be many misfit dislocations in InP nucleation region. Then InP nanowires grow in the [1 12] direction on the GaAs {111} plane under the action of dislocation and precursors diffusion. Due to the finite size of GaAs {111} planes in the trenches, finally, InP nanowires will grow beyond the trench along the initial 〈1 12〉 growth directions. In order to testify the growth mechanism of 〈1 12〉 directions InP nanowires we proposed, we investigated two samples growth in different conditions. Fig. 4(a) shows an InP sample grown at 650 °C with a V/III ratio 668. From the previous study, in this growth parameter, no InP nanowires can be grown via the VLS mechanism. However in this sample, a [1 12] direction InP nanowire was observed. There will be many {111} type microtwins and stacking faults parallel to the InP/GaAs interface when InP nucleate on GaAs buffer layers [14]. Those dislocations can effectively reduce the strain energy of InP crystal and make it easier growth aligned in 〈1 12〉 directions. This observed nanowire may be driven by 〈1 12〉 dislocations in InP films. Fig. 4(b) shows an InP nanowires sample growth in a Si substrate patterned with much larger area ratio of SiO2 mask. The active area of V-shaped trenches for selective growth only occupied a ratio 2.5%. The growth temperature and V/III ratio for InP nanowires are 400 °C and 250, respectively. From the SEM image, a comb-like nanowires array was observed along the [110] direction (the trenches along direction). This improvement of direction controlling ability correspond to the enhancement of the process that in species diffuse along the SiO2 surface due to larger SiO2 mask area. Based on the above discussion, the strain forms stacking faults and dislocations at the GaAs/InP interface and precursors diffusion effect may be the reasons resulting in InP nanowires preferentially grow in the 〈1 12〉 directions. Interestingly, by varying the V/III mole ratio in situ, we can achieve the branched and direction switched nanostructures. The sample was grown at a V/III ratio 334 for 10 min, then, the V/III ratio reduced to 250 by decreased PH3 flow (with a constant TMIn flow) and maintained for 3.3 min. Fig. 5(a) shows a side-view of the nanowires from [1 10] direction. In this view, the backbone nanowires are vertical to the substrate as the previous discussion. We labeled three kinds of nanowires in this graph with dotted lines: straight line, branched and direction switched nanowires. In order to see more detail of those nanowires, we removed the nanowires from the growth substrate via sonication in ethanol and then drop-cast onto a Si substrate. We observed from this sample and a 20% yield kinking nanowires are obtained. In Fig. 5(b), we observed the nanowires branch also may come up a switch in
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Fig. 4. (a) A typical SEM side view image of InP films growth at 650 °C with a GaAs buffer layer in V-shaped trenches. (b) A top view SEM image of InP nanowires growth on Si substrates only with 2.5% trench area for selective growth.
growth direction. In Fig. 5(e), an interesting phenomenon was observed: the nanowires reversible switching of the growth direction in this nanowire. From Fig. 5(b)-(e), we can observe that the angle between the backbone and branch of InP nanowires and the switch angle in nanowires growth direction both are 60°. As reported by Jia Wang etc., using Au droplet as a catalyst growth InP nanowires, they reversibly switch InP nanowires growth between a 〈100〉 and a 〈111〉 direction by varying the indium content of the droplet [16]. In this work, the change of the V/III ratio may influence the shape of the In droplet and this may be the reasons of the nanowires kinking. In addition, with the V/III ratio reduced, there may be In droplet on nanowire backbone and this may lead to a branch nanowire growth. Fig. 6(a) is a SEM image of nanowires backbones which shows the InP nanowire presents a triangular cross-section morphology. To determine the branched nanowires crystal structure, a TEM image was taken with 〈111〉 direction of the electron beam incidence. In the Fig. 6(b), the TEM image shows one single branched InP nanowire with a diameter of 100 nm. As shown in the lower-left inset, the TEM electron diffraction pattern indicated the InP nanowire with pure WZ structure and that the nanowire axis is perpendicular to the c axis of the lattice. This is common for GaN nanowire [17], but very infrequently for InP nanowires. To determine more detail about crystal structure and the mechanism about the formation of branched morphology, high-resolution TEM investigations were conducted for the region of backbone, branched section and crotch edge, of this nanowire. The HRTEM
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Fig. 5. Scanning electron micrographs of branched and direction switched InP nanowires. (a) A cross-section view of the nanowires on [1 10] direction. (b–e) are the SEM images of nanowires removed from the growth substrate via sonication in ethanol and then drop-cast onto a Si substrate. The angle of branched section and direction switch are both 60°.
Fig. 6. TEM and SEM images of single branched InP nanowire (a) A cross-section of InP nanowires backbone (b) A TEM images and diffraction pattern in the [0001] projection. (c–e) are high-resolution TEM images of this nanowire with fast fourier transform.
results are shown in Fig. 6(c)-(e). From these HRTEM images, we find that the crotch edge, backbone and branched section of this nanowire with a single crystalline nature. The insets of Fig. 6(c)– (e) are fast Fourier transform (FFT) of the TEM images, which confirmed the pure WZ crystal structure of the nanowires. Now
we use the [hkil] notation for InP nanowires crystal structure. According to FFT pattern in Fig. 6(c), the interplanar spacing of this nanowire is approximately 2.15 Å for {11 20} planes, corresponding to the expected value of a typical InP WZ structure. The TEM diffraction pattern indicates the nanowire growth in [11 20]
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direction which is equivalent with the 〈1 12〉 orientation in cubic coordinate system. This result is consistent with our discussion in the previous part. By comparing the FFT patterns of Fig. 6(d) and (e) with the pattern in part (b), it shows an epitaxial crystalline relations between the backbone and branch segments of the nanowire. Furthermore, the FFT patterns indicates that the backbone and branch segments aligned in [11 20] and [ 12 10] directions, respectively. These direction of [11 20] and [ 12 10] are equivalent in the hexagonal coordinate system. In addition, no defects and stacking faults were observed at the crotch of this nanowire. More work is needed to be done to well understand this branched nanowire growth mechanism.
4. Conclusion In conclusion, catalyst-free InP nanowires grown by low pressure MOCVD on Si (001) substrate patterned with V-shaped trenches have been reported. Stacking-faults-free pure wurtzite phase nanowires were realized by using selective grown GaAs buffer layers. For growing under the optimized conditions, about 70% of the nanowires self-aligned on 〈1 12〉 directions which were perpendicular with its c axis. This preferable growth direction gave a new understanding about the nanowires growth mechanisms. In addition, our approach shows the possibility of making branched and switching of growth directions in single InP nanowire with proper adjusted V/III ratio in growth process.
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Acknowledgment This work was financially supported by National Science and Technology Major Project (Grant no. 2011ZX02708) in China.
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