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Cathedral-II: a silicon compiler for digital signal processing
R& D reports Applications Capehart, B L 'Emerging microcomputer technology for electrical energy management' ]. Microcomput. Appl. Vol 9 No 4 (October 1986) pp 253-260
Carinalli, C and Blair, l 'National's advanced graphics chip set for high performance graphics' pp 40-48
Shires, G 'A new VLSI graphics coprocessor -the Intel 82786' pp 49-55
Perkins, W J, Sowden, J, Cheng, C W J and Stenning, B F
IC design
'A microcomputer system to help the severely handicapped' JIERE Vol 56 No 10-12 (October/December 1986) pp 311-316
De Man, H, Rabaey, J, Six, P and Claesen, L
Methods for using standard microcomputers for operation by physically disabled persons are considered, and the development of suitable programs for control from limited input devices is explained.
Control Parish, D J and Lucas, J 'Advanced automotive multiplexed wiring system' lEE Proc. E Vo1133 No 6 (November 1986) pp 312-313 Despite the widespread installation of functioning systems, such as electronic ignition, in production vehicles, multiplexed wiring harnesses are not yet installed. The experimental harness described in the paper uses 4-bit custom CMOS microcontrollers to achieve low cost, say the authors. A central master unit with a microcontroller and software programming controls up to eight switching and monitoring units distributed throughout the vehicle, which in turn control up to 64 automotive devices.
'Cathedral-II: a silicon compiler for digital signal processing' IEEE Des. Test. Comput. Vol 3 No 6 (December 1986) pp 13-25
IEEE Comput. Graph. and Appl. Vol 6 No 10 (October 1986)
Asal, M, Short, G, Preston, T, Simpson, R, Roskell, D and Guttag, K 'The Texas Instruments 34010 graphics system processor' pp 24-39
"/66
RAPAC, a reconfigurable attached processor architecture for convolution, was designed to perform online industrial inspection tasks. The system contains independent acquisition, display, framestore and processor units. The framestore/ processor are controlled by a host microcomputer, which is also used for algorithm development.
Memories
Cathedral II is an 'applicationspecific' silicon compiler developed to synthesize multiprocessor system chips for DSP. Processors are synthesized in terms of modules called from automated, reusable module generators. An expert subsystem verifies correctness during silicon design and generates functional and timing modules for verification at the module and chip levels.
Vinals, V, Rodriguez, C and OlivE, A 'Cache memories' Mundo Electronico
Gajski, D D, Dutt, N D and Pangrle, BM
Discusses how the 68020 can be used to configure a multiple-CPU computer.
'Silicon compilation: a tutorial' J. Semicustom ICs Vol 4 No 2 (December 1986) pp 5-21 This overview surveys three levels of approach to silicon compilation: structural, functional and intelligent silicon compilation. Some commercial and research silicon compilers are examined, and a design process model that can be used in designing intelligent silicon compilers is described.
Roger, J D Graphics processors
'RAPAC: a high-speed imageprocessing system' lEE Proc. E Vol 134 No 1 (January 1987) pp 39-46
'The development cycle of a typical semicustom IC' J. Semicustom ICs Vol 4 No 1 (September 1986) pp 32-39
Image processing Elphinstone, A C, Heron, A P, Hobson, G S, Houghton, A, Lau, M K, Powell, A R, Seed, L and Tozer, R C
No 167 (November 1986) pp 72-82
Multiprocessors Eastwood, D 'Multiple 32-bit design' Systems Int. (November 1986) pp 65-66
Gaudiot, J-L, Dubois, M, Lee, L-T and Tohme, N G 'The TX16: a highly programmable multi-microprocessor architecture' IEEEMicro Vol 6 No 5 (October 1986) pp 18-31 Conventional methods of programming multiprocessor systems could rapidly become unworkable, say the authors, as it is impossible for a programmer to 'juggle' a large number of active tasks. The paper presents a bus-oriented multiprocessor structure in which memory is distributed among the processors but each processor can access the memory of any other processor. Called the TX16, the system is built around 16 transputers and is based on the functional language model, whereby instructions are scheduled directly by the availability of their operands.
Microprocessors and Microsystems
Carinalli, C and Blair, l 'National's advanced graphics chip set for high performance graphics' pp 40-48
Shires, G 'A new VLSI graphics coprocessor -the Intel 82786' pp 49-55
Perkins, W J, Sowden, J, Cheng, C W J and Stenning, B F
IC design
'A microcomputer system to help the severely handicapped' JIERE Vol 56 No 10-12 (October/December 1986) pp 311-316
De Man, H, Rabaey, J, Six, P and Claesen, L
Methods for using standard microcomputers for operation by physically disabled persons are considered, and the development of suitable programs for control from limited input devices is explained.
Control Parish, D J and Lucas, J 'Advanced automotive multiplexed wiring system' lEE Proc. E Vo1133 No 6 (November 1986) pp 312-313 Despite the widespread installation of functioning systems, such as electronic ignition, in production vehicles, multiplexed wiring harnesses are not yet installed. The experimental harness described in the paper uses 4-bit custom CMOS microcontrollers to achieve low cost, say the authors. A central master unit with a microcontroller and software programming controls up to eight switching and monitoring units distributed throughout the vehicle, which in turn control up to 64 automotive devices.
'Cathedral-II: a silicon compiler for digital signal processing' IEEE Des. Test. Comput. Vol 3 No 6 (December 1986) pp 13-25
IEEE Comput. Graph. and Appl. Vol 6 No 10 (October 1986)
Asal, M, Short, G, Preston, T, Simpson, R, Roskell, D and Guttag, K 'The Texas Instruments 34010 graphics system processor' pp 24-39
"/66
RAPAC, a reconfigurable attached processor architecture for convolution, was designed to perform online industrial inspection tasks. The system contains independent acquisition, display, framestore and processor units. The framestore/ processor are controlled by a host microcomputer, which is also used for algorithm development.
Memories
Cathedral II is an 'applicationspecific' silicon compiler developed to synthesize multiprocessor system chips for DSP. Processors are synthesized in terms of modules called from automated, reusable module generators. An expert subsystem verifies correctness during silicon design and generates functional and timing modules for verification at the module and chip levels.
Vinals, V, Rodriguez, C and OlivE, A 'Cache memories' Mundo Electronico
Gajski, D D, Dutt, N D and Pangrle, BM
Discusses how the 68020 can be used to configure a multiple-CPU computer.
'Silicon compilation: a tutorial' J. Semicustom ICs Vol 4 No 2 (December 1986) pp 5-21 This overview surveys three levels of approach to silicon compilation: structural, functional and intelligent silicon compilation. Some commercial and research silicon compilers are examined, and a design process model that can be used in designing intelligent silicon compilers is described.
Roger, J D Graphics processors
'RAPAC: a high-speed imageprocessing system' lEE Proc. E Vol 134 No 1 (January 1987) pp 39-46
'The development cycle of a typical semicustom IC' J. Semicustom ICs Vol 4 No 1 (September 1986) pp 32-39
Image processing Elphinstone, A C, Heron, A P, Hobson, G S, Houghton, A, Lau, M K, Powell, A R, Seed, L and Tozer, R C
No 167 (November 1986) pp 72-82
Multiprocessors Eastwood, D 'Multiple 32-bit design' Systems Int. (November 1986) pp 65-66
Gaudiot, J-L, Dubois, M, Lee, L-T and Tohme, N G 'The TX16: a highly programmable multi-microprocessor architecture' IEEEMicro Vol 6 No 5 (October 1986) pp 18-31 Conventional methods of programming multiprocessor systems could rapidly become unworkable, say the authors, as it is impossible for a programmer to 'juggle' a large number of active tasks. The paper presents a bus-oriented multiprocessor structure in which memory is distributed among the processors but each processor can access the memory of any other processor. Called the TX16, the system is built around 16 transputers and is based on the functional language model, whereby instructions are scheduled directly by the availability of their operands.
Microprocessors and Microsystems