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Causes of cracks in SMD and type specific remedies
1338
World Abstracts on Microelectromcs and Reliability
sections of the solder joints are inspected using scanning electron microscopy Individual grains (colonies of iamellae or globulae) are found to slide relative to one another d u n n g thermal cychng. Cracks initiate at sites where the b o u n d a n e s between colonies intersect the outer surface of the solder fillet In the case of the LLCC solder joints, cracks also initiate beneath the chip carrier These cracks rapidly reach the bulk portion of the fillet, where they are observed to prefer travel along interfaces between phases
Optimization of GaAs-on-silicon M E S F E T structures. G HALKIAS, etal Sohd-St Electron 34(10), 1157 (1991) The optimization of GaAs-on-Sl M E S F E T structures has been investigated both experimentally and theoretically The GaAs-on-Si samples were grown by conventional molecular beam epitaxy (MBE) and laser assisted M B E (LAMBE), on victual (100) S1 wafers The n - GaAs/p - on-S1 heterojunctlons show a linear C 2-V dependence with intercept voltages of 0 5-0 6 V and straight line logarithmic I - V relationships with ideahty factors between 1_4 and 2 Ideahty factors approaching 1 have been obtained for the L A M B E samples which are attributed to the presence of abrupt heterojunctlons A transistor slmulatmn model was developed which includes the influence of the heterojunctlon potential barner on the charge concentration into the entire device structure The tradeoff of the effects of the heterojunction barrier with the structural properties of GaAs-onSI indicates that a 1 5 m m think buffer layer is optimum This optimized structure has been expenmentally verified by fabncatmg MESFETs, resulting in a transconductance higher than 200 mS m m ~ for 1 × 250 m m 2 gates
Computer vision for quality control in automated manufacturing systems. EHSAN ASOUDEG1 and ZHIBING PAN Comput md Engng 21(1-4), 141 (1991) On-line automated inspection for quality a_nd process control is becoming an important element of automated m a n u f a c t u n n g systems Enabling non-contact, thus non-destructive inspection, optical techniques are especially well suited to industrial inspection needs In this paper, an image processing system for respectIng round parts is proposed and described Several measures of out-of-roundness are discussed. Different sampling plans are investigated and the proper sampling plan is suggested
Exhaust gas detoxifying systems used hi microeleetronies. N PROUST, C FR£SNAIS and F BOURDON Revue Techmque Thomson-CSF 23(3), 619 (September 1991) As mlcroelectromcs requ,res a large variety of hazardous gases which can be toxic, combustible, pyrophonc or corrosive, decontamination of exhaust gases to avoid pollution has to be performed in a safe manner Various methods based on dilution, adsorption, solid phase destruction, combustion in a flame, thermal decomposition and wet scrubbing are presented and compared Some examples of available equipments are reported
Interconnection techniques for GaAs packaging. T J BUCK Circuit Wld 18(1), 22 (1991) In the never-ending quest for speed, designers are now turning to digital G a A s rotegrated circuits both to extend the bandwidth of current designs and in some cases to generate a whole new class of products never before possible. The engineer well versed in high speed ECL design techniques generally understands the problems assocmted with this transfer to G a A s logic However, even with the design task well defined, the exact solution for interconnecting devices is often difficult and stresses the capabilities of exastmg multilayer pnnted circmt techniques using conventional dielectric materials and processing This paper examines the design task in detail, and will present recent developments in shielded &screte wrong techniques as a possible solution for G a A s packaging
New applications of low temperature PECVD silicon nitride films for microelectronic device fabrication. M, D DANGE, J Y LEE and K SOOmAKUMAR Mwroelectron J. 22(7-8), 19 (1991) Sdmon nltnde has been widely used in microelectronic device f a b n c a u o n processes for encapsulation, surface passwation and isolation In this paper we report new applications of plasma-enhanced chemical vapor deposition (PECVD) silicon m t n d e films that can be deposited at a temperature lower than the soft bake temperature of normal photoreslsts Lift-off of the silicon nltride film was carried out using standard poSltlve photoresist GaAs M E S F E T s and InP MISFETs with self-ahgned gates were successfully fabricated using this hft-off process of low temperature PECVD slhcon mtrlde
Electroplated solder joints for flip-chip applications. EDWARD K YUNG and IWONA TURKLIK IEEE Trans Compon Hybrids mfg Technol 14(3), 549 (1991) A step-by-step description of M C N C s solder electroplating process for flip-chip apphcatmns is provided The necessity of phasing Cr and Cu in the under-bump metallurgy (UBM), which also functions as the current path during plating, ,s verified by SEM study of the lntermetalhcs in the reflowed solder joints Characteristics of the SnPb solder plating bath are presented, and key issues on designing and operating manufacture scale cells are identified Mathematical modellng of the plating process confirms the capability of the plating process to produce solder bumps of uniform volume and solder composltmn Feasibility of the eleetroplated solder bumping process is demonstrated on dice with an area array of pads of a ~ 0 005 inch diameter on a 0 010 inch pitch Data of preliminary mechanical testing conducted to evaluate the integrity of the solder joints are presented On the development of chip-net. PARAG DIWAN and RAKESH KuM/d~t Microelectron_ J 22(7/8), 105 (1991) As IS wellknown, semiconductor m a n u f a c t u n n g is a technologyintensive operation carried out in an ultraclean dust-free environment Such an environment can be best maintained by m l m m m n g h u m a n intervention Thus, the key for high yields and defect-free reliable mlcrochips seems to be automatron Behind any automation project Is an efficient and reliable computer network In this paper, an overview of semiconductor manufacturing environment is presented so as to provide an insight into dataflow direction and requirements Details of C I M / C A D / C A M reqmrements of semiconductor operations in terms of software and hardware are then elaborated upon Next, a blueprint for a proposed company-wide network is detailed m terms of network topology transmission media, network access methods and communication protocols The paper concludes with comments on specific benefits obtained from such a network, and possible future enhancements such as satellite links
Causes of cracks in S M D and type specific remedies. SUSUMU OMI, KAZUYA FUJITA, TAKAAKI TSUDA and TAKAMICHI MAEDA IEEE Trans Compon Hybrids mfg Technol 14(4), 818 (1991) Packages used with surface-mount devices (SMDs) have the u m q u e rehabihty problems of package cracks arising due to soldenng stress Package cracks can be divided into three dlstmct types To remedy this problem of cracking, it is necessary to determme the type of cracking that may occur, and take countermeasures specific to each type. In this paper, we investtsat~l possible causes for each type of package crack, and t ~ h m q u e s for optimized crackproof package design for in&vldual crack types were developed
Hermetic sealing, process with atmospheric pressure vibration for LSI packages. YuuJI FUJITA, MXSAHIDE KOKUDA and KEN'ICHI MIZUISI-II. IEEE Trans. Comport Hybrids mfg Technol 14(4), 714 (1991) This paper presents a new
World Abstracts on Microelectromcs and Reliability
sections of the solder joints are inspected using scanning electron microscopy Individual grains (colonies of iamellae or globulae) are found to slide relative to one another d u n n g thermal cychng. Cracks initiate at sites where the b o u n d a n e s between colonies intersect the outer surface of the solder fillet In the case of the LLCC solder joints, cracks also initiate beneath the chip carrier These cracks rapidly reach the bulk portion of the fillet, where they are observed to prefer travel along interfaces between phases
Optimization of GaAs-on-silicon M E S F E T structures. G HALKIAS, etal Sohd-St Electron 34(10), 1157 (1991) The optimization of GaAs-on-Sl M E S F E T structures has been investigated both experimentally and theoretically The GaAs-on-Si samples were grown by conventional molecular beam epitaxy (MBE) and laser assisted M B E (LAMBE), on victual (100) S1 wafers The n - GaAs/p - on-S1 heterojunctlons show a linear C 2-V dependence with intercept voltages of 0 5-0 6 V and straight line logarithmic I - V relationships with ideahty factors between 1_4 and 2 Ideahty factors approaching 1 have been obtained for the L A M B E samples which are attributed to the presence of abrupt heterojunctlons A transistor slmulatmn model was developed which includes the influence of the heterojunctlon potential barner on the charge concentration into the entire device structure The tradeoff of the effects of the heterojunction barrier with the structural properties of GaAs-onSI indicates that a 1 5 m m think buffer layer is optimum This optimized structure has been expenmentally verified by fabncatmg MESFETs, resulting in a transconductance higher than 200 mS m m ~ for 1 × 250 m m 2 gates
Computer vision for quality control in automated manufacturing systems. EHSAN ASOUDEG1 and ZHIBING PAN Comput md Engng 21(1-4), 141 (1991) On-line automated inspection for quality a_nd process control is becoming an important element of automated m a n u f a c t u n n g systems Enabling non-contact, thus non-destructive inspection, optical techniques are especially well suited to industrial inspection needs In this paper, an image processing system for respectIng round parts is proposed and described Several measures of out-of-roundness are discussed. Different sampling plans are investigated and the proper sampling plan is suggested
Exhaust gas detoxifying systems used hi microeleetronies. N PROUST, C FR£SNAIS and F BOURDON Revue Techmque Thomson-CSF 23(3), 619 (September 1991) As mlcroelectromcs requ,res a large variety of hazardous gases which can be toxic, combustible, pyrophonc or corrosive, decontamination of exhaust gases to avoid pollution has to be performed in a safe manner Various methods based on dilution, adsorption, solid phase destruction, combustion in a flame, thermal decomposition and wet scrubbing are presented and compared Some examples of available equipments are reported
Interconnection techniques for GaAs packaging. T J BUCK Circuit Wld 18(1), 22 (1991) In the never-ending quest for speed, designers are now turning to digital G a A s rotegrated circuits both to extend the bandwidth of current designs and in some cases to generate a whole new class of products never before possible. The engineer well versed in high speed ECL design techniques generally understands the problems assocmted with this transfer to G a A s logic However, even with the design task well defined, the exact solution for interconnecting devices is often difficult and stresses the capabilities of exastmg multilayer pnnted circmt techniques using conventional dielectric materials and processing This paper examines the design task in detail, and will present recent developments in shielded &screte wrong techniques as a possible solution for G a A s packaging
New applications of low temperature PECVD silicon nitride films for microelectronic device fabrication. M, D DANGE, J Y LEE and K SOOmAKUMAR Mwroelectron J. 22(7-8), 19 (1991) Sdmon nltnde has been widely used in microelectronic device f a b n c a u o n processes for encapsulation, surface passwation and isolation In this paper we report new applications of plasma-enhanced chemical vapor deposition (PECVD) silicon m t n d e films that can be deposited at a temperature lower than the soft bake temperature of normal photoreslsts Lift-off of the silicon nltride film was carried out using standard poSltlve photoresist GaAs M E S F E T s and InP MISFETs with self-ahgned gates were successfully fabricated using this hft-off process of low temperature PECVD slhcon mtrlde
Electroplated solder joints for flip-chip applications. EDWARD K YUNG and IWONA TURKLIK IEEE Trans Compon Hybrids mfg Technol 14(3), 549 (1991) A step-by-step description of M C N C s solder electroplating process for flip-chip apphcatmns is provided The necessity of phasing Cr and Cu in the under-bump metallurgy (UBM), which also functions as the current path during plating, ,s verified by SEM study of the lntermetalhcs in the reflowed solder joints Characteristics of the SnPb solder plating bath are presented, and key issues on designing and operating manufacture scale cells are identified Mathematical modellng of the plating process confirms the capability of the plating process to produce solder bumps of uniform volume and solder composltmn Feasibility of the eleetroplated solder bumping process is demonstrated on dice with an area array of pads of a ~ 0 005 inch diameter on a 0 010 inch pitch Data of preliminary mechanical testing conducted to evaluate the integrity of the solder joints are presented On the development of chip-net. PARAG DIWAN and RAKESH KuM/d~t Microelectron_ J 22(7/8), 105 (1991) As IS wellknown, semiconductor m a n u f a c t u n n g is a technologyintensive operation carried out in an ultraclean dust-free environment Such an environment can be best maintained by m l m m m n g h u m a n intervention Thus, the key for high yields and defect-free reliable mlcrochips seems to be automatron Behind any automation project Is an efficient and reliable computer network In this paper, an overview of semiconductor manufacturing environment is presented so as to provide an insight into dataflow direction and requirements Details of C I M / C A D / C A M reqmrements of semiconductor operations in terms of software and hardware are then elaborated upon Next, a blueprint for a proposed company-wide network is detailed m terms of network topology transmission media, network access methods and communication protocols The paper concludes with comments on specific benefits obtained from such a network, and possible future enhancements such as satellite links
Causes of cracks in S M D and type specific remedies. SUSUMU OMI, KAZUYA FUJITA, TAKAAKI TSUDA and TAKAMICHI MAEDA IEEE Trans Compon Hybrids mfg Technol 14(4), 818 (1991) Packages used with surface-mount devices (SMDs) have the u m q u e rehabihty problems of package cracks arising due to soldenng stress Package cracks can be divided into three dlstmct types To remedy this problem of cracking, it is necessary to determme the type of cracking that may occur, and take countermeasures specific to each type. In this paper, we investtsat~l possible causes for each type of package crack, and t ~ h m q u e s for optimized crackproof package design for in&vldual crack types were developed
Hermetic sealing, process with atmospheric pressure vibration for LSI packages. YuuJI FUJITA, MXSAHIDE KOKUDA and KEN'ICHI MIZUISI-II. IEEE Trans. Comport Hybrids mfg Technol 14(4), 714 (1991) This paper presents a new