- Email: [email protected]
Challenges for giga-scale integration
Microelectron. Reliab., Vol, 37, No. 7, pp. 985-1001, 1997
Pergamon
PII: S0026-2714(96)00261-2
© 1997 ElsevierScienceLtd All rights reserved.Printed in Great Britain oo26-2714/97 $17.0o+ o.o0
CHALLENGES FOR GIGA-SCALE INTEGRATION EIJI T A K E D A Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan (Received 1 September 1995)
Abstract--The "giga-chip era" has begun, A new challenging approach to ULSI reliability is now greatly needed in response to the "paradigm shift" now being brought about by simple scaling limitations, increased process complexity, and diversified ULSI application to advanced multimedia and personal digital assistant (PDA) systems. A good example of this shift is the new movement from simple failure analysis by sampling the output of a manufacturing line to the "building-in-reliability" approach. To pursue this technique, greater importance will be attached to a deeper physical understanding of the significant relationships between the input variables and product reliability (including frequent use of Computer Aided Design, CAD and Design Automation, DA), and to total concurrent engineering from research labs to production sites. Furthermore, fast, new ULSI testing methods and new yield-enhancing redundancy techniques that reduce costs will be increasingly needed to achieve high reliability for ULSIs with 109devices on a single chip. Only with these approaches can we pave the way for giga-scale integration (GSI) in the 21st century. © 1997 Elsevier Science Ltd.
1. INTRODUCTION The "ULSI revolution" that is opening a new epoch in the electronics industry has made remarkable progress to such an extent that 109-10 I° transistors can now be fabricated on a single chip. E.g. current ULSI micro-fabrication technologies are being pushed to new extremes by the D R A M community, thereby expediting research on 1 Gbit D R A M s [1] using a 0.16/lm design rule. Also, sophisticated micro-processors using 0.15 #m MOSFETs could possibly appear at the beginning of the 21st century. From the manufacturing standpoint, process and device technologies in the deep-submicron region (0.1--0.3/~m) are, however, approaching practical limits and thus coincident achievement of high performance, high packing density, and high reliability is expected to become increasingly difficult. Furthermore, due to the large initial investment required by the fabrication process complexity, the ultimate profitability of a large investment has recently become a significant issue in the semiconductor industry. Thus, there is an urgent need to reduce fabrication process costs by developing new approaches such as single wafer processing [2] and tool clustering, and increasing automation of process and factory control. Additionally, new approaches to ULSI systems and architectures have been proposed to enhance the total performance of systems and to reduce system cost. Examples include the RAMBUS interface [3] and synchronous DRAMs that overcome bandwidth bottlenecks. Judging from the present trend ("paradigm shift") in ULSIs, it is now more important
to make ULSI chips and systems more profitable by adding value--market breakthroughs, and simplify fabrication processes for higher reliability and standardization--production breakthroughs, as well as ultra-scaling breakthroughs. For scaled MOSFETs, hot-carrier effects are still important even under low supply voltages (less than 3 V), and the Vth-scaling required for power supply voltage reduction and associated shortchannel effect (e.g. punch-through), is now demanding much attention. Moreover, it is not too much to say that ULSIs have been developed mainly with continued reliability in mind. For each generation, device and memory structures, fabrication processes, and materials have so far been determined by the need to overcome reliability problems, such as soft-error phenomena in ULSI memories, dielectric breakdown in insulators, and electro- and stress-migration in the interconnection. This tendency will continue. However, according to the current technology paradigm shift and ULSI business changes, a new strategy for ULSI technology must be introduced to realize giga-scale and nanometer LSIs. In this paper, state-of-the-art ULSI technology is reviewed and the new reliability challenges for giga-scale integration (GSI) are considered. 2. DRAM TECHNOLOGY--FERROELECTRIC MATERIALS
Japanese ULSI technology and business have made great progress by using D R A M s as a technology driver and business strategy in the past 20 years. A key word was down-scaling of device dimensions,
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between CPUs and memories. The former strongly requires use of ferroelectric materials such as PZTs in the memory capacitor; the latter requires D R A M s to shift to more system-oriented applications. The trend in device parameters for each D R A M generation is shown in Fig. 2. It should be noted that
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the down-scaling of capacitor size and capacitor dielectric thickness is leveling off because of physical limits, in spite of the still monotonic decrease in cell size. This trend demands complicated threedimensional cell structures, at least up to 256 Mbit DRAMs, resulting in increased bit-cost. The increase in process steps due to device complexity is demonstrated in Fig. 3. The key technology used for each generation is also shown in Fig. 3. These approaches have aimed at high performance and high packing density rather than low process cost. Thus, the number of process steps has been increasing with every D R A M generation. The solution to this problem is the use of ferroelectric materials such as PZT as a capacitor insulator. The process step advantage gained from the use of PZT materials is shown in Fig. 4. A drastic
decrease in process steps is seen in ferroelectric DRAMs. However, it is very difficult, although urgent, to enhance the quality of ferroelectric films up to production level. At the moment, a dielectric constant of 1000 at 0.1/~m thickness has been achieved, which corresponds to I Gbit DRAMs. Leakage current is also an important factor. What is even more significant is the dependence of dielectric constant on film thickness (Fig. 5). It should be noted that the dielectric constant decreases as film thickness decreases. The physical mechanism for this phenomenon is not yet clear. Discovering this important mechanism will lead to ideal ferroelectric DRAMs that make good use of PZT polarization. The ferroelectric RAM is a non-volatile DRAM. Figure 6 shows trends in D R A M cell structures.
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Flash non-volatile memories are making good progress with higher speeds than DRAMs (Fig. 7), aiming at application to personal digital assistants (PDA). A key for flash memories is high quality oxide/insulator technology, the same as for DRAMs. In particular, demand for 105-106 write/ erase cycles is very severe for gate oxides and seems to be close to intrinsic oxide breakdown. Therefore, new robust oxides such as N20-oxynitrided oxides are needed. Furthermore, as shown in Fig. 8, in terms of cell size miniaturization, flash memory cells can be more
easily scaled down than D R A M cells. This fact will be important for future PDA applications• Flash memories, rather than DRAMs, may provide a key to the multimedia and PDA systems of the 21st century. The characteristics of an A N D cell [4] are compared with those of NOR cells and N A N D cells [5] in Fig. 9. A N D and N A N D cells use tunneling injection for the write/erase operation, while the NOR cell is operated by hot-carrier injection. Tunneling and hot-carrier injections have different oxide degradation mechanisms. Thus, a different approach is needed to obtain reliable oxides•
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4. SCALED MOS DEVICES FOR HIGH PERFORMANCE PROCESSORS
4.1. Hot-carrier effects Hot-carrier effects have determined MOS device structures for many VLSI generations and so have been thoroughly studied. To reduce hot-carrier degradation in scaled MOS devices, two approaches have been taken: (1) hot-carrier resistant device structures such as D D D (double diffused drain), L D D (lightly doped drain) and G O L D (gate-drain overlapped device)--drain/gate engineering--and (2) reduction of power supply voltage (1.5-3 V). The former 5 V power supply suffers from power
consumption and process complexity. The lowvoltage approach must overcome the current drivability issue and low speed (which is caused by non-down-scaling of V,h). A third approach is to make good use of AC (alternating current) effects, including the duty ratio. That calls for a deeper physical understanding of AC hot-carrier phenomena, followed by use of this understanding in the actual device/circuit design and supply voltage selection. Hot-carrier effects are still important,
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particularly in logic circuits in 3 V power supply systems, in the trade-off of hot-carrier effects vs performance. In terms of AC hot-carrier effects, inductancenoise-induced-degradation and enhanced degradation specific to AC hot-carrier effects have been reported. Figure 10 shows the source noise (AVs) as a function of the wiring inductance (Z) with channel width (W) as a parameter. It is found that AVs is a logarithmic function of Z and is negligible when Z is smaller than 250 mQ (80 #H). That fact is important for circuit design as well [6]. Figure 11 also shows the ratio of calculated lifetime to measured lifetime as a function of drain voltage. The lifetime measured by the e-beam tester obviously becomes shorter
than the calculated one at voltages above 7 V. This is an enhanced degradation phenomenon. Of course, below 6V, there is obviously good agreement between calculation and experiments. Such an enhanced degradation can be explained in the following way. Neutral traps are generated by hothole injection and subsequently, many hot-electrons are trapped in the neutral traps, leading to the enhanced degradation. That is an intrinsic AC hot-carrier effect. Figure 12 shows hot-carrier breakdown voltage. As can be seen, the 3.3 V supply voltage is a critical point for 0.3/~m MOS devices. Therefore, more attention should be paid to G O L D structures (gate-drain overlapped structure), which has a higher
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hot-carrier breakdown voltage than the LDD structure and higher channel current without severe gate length down-scaling. 4.2. Short-channel effects When MOS devices are scaled down to less than 0.3 #m, short-channel effects are more significant than hot-carrier effects, because the width of the depletion layers surrounding the source/drain is close to the gate length value. In addition, due to the strong demand for lower power consumption, the supply voltage is reduced to 3.3-1.5 V, resulting in the reduction of hot-carrier effects. Thus, more attention must be paid to "substrate engineering" of device structures, such as the punch-through stopper, to suppress the short-channel effects. Under reduced supply voltage, it is important to simultaneously suppress Vth lowering and keep V,, low. Figure 13 shows V,h-lowering characteristics for three types of substrate engineering structures. Type A is the conventional one. Type B has a punch-through stopper within the substrate. Type C is the so-called pocket structure. It should be noted that the pocket structure provides low V,h and highly suppressed V,h lowering. As the ultimate device structure of the substrate engineering method, much attention has recently been paid to thin film SO1 device structures. Although crystal quality problems remain, thin film SOI technology may be able to provide new low cost fabrication processes, as well as higher performance and low power consumption. It will drastically change the isolation process and the memory cell process. Figure 14 shows a new bulk thin film SOl device, DELTA [7]. The reason why the DELTA provides a large channel current is due to the effectively wide channel width and the thin film SOl effect (enhanced mobility).
Besides the conventional device miniaturization approaches, single electron transistors and memories are interesting [8]. Such devices make good use of the Coulomb blockade phenomenon as a device operating principle, because the Coulomb blockade is a more robust physical phenomenon than interference effects such as the AB effect. In addition, the single electron devices provide very low power electronics and very reliable memory devices, which may lead to the ultimate flash memories. The noise issue in the single electron devices is not clear, but at least for the single electron memories, the low-noise might be achieved as an extension of flash non-volatile memories. Thus, device structures from 0.3-0.1/~m should be re-examined from the viewpoints of reliability vs performance and memory vs logic circuits. 4.3. Isolation In order to enhance device performance, drastic approaches such as silicidation of source and drain have been used to a great extent in logic circuits, but not memory circuits. From now on, because of the
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need to reduce the parasitic effects, not only active devices, but also isolation will be more significant, particularly in the 0.3/~m regime, or to a lesser extent, logic circuits. To this end, as the LOCOS isolation is approaching its limits, trench isolation [9] will be more important in regions of 0.2/~m or less. However, the trench isolation has several problems such as side-wall leakage and mechanical stress. Therefore, new device designs that include isolation structures are strongly required.
5. LOW POWER ELECTRONICS--POST CMOS CIRCUITS The advent of personal data processing and communication, coupled with device miniaturization, is strongly calling for low voltage operation. However, various constraints associated with lowering voltage, such as drivability degradation and the controllability of low threshold voltage, have not been solved, thus implying the need for new challenges to "low power electronics". Here, new low voltage devices and circuits are discussed from the viewpoints of CMOS and BiCMOS logic circuits, D R A M , and post-CMOS circuits (pass transistor logics). So far, BiCMOS provides the benefits of the low power dissipation of CMOS and the high output drive capability of bipolar devices. However, under low-supply voltages, the gate delay time significantly increases due to the inherent built-in voltage of the bipolar devices. To overcome this problem, new circuit concepts suitable for low voltage operation have been proposed. Among them, the transiently saturated full-swing BiCMOS (TS-Fs-BiCMOS), which makes good use of the transient saturation technique of the bipolar junction transistors, enables
high-speed operation in the sub 2-V regime. Figure 15 shows simulated dependence of gate delay time on supply voltage. It can be seen that Ts-Fs BiCMOS provides the highest speed [11]. For standard DRAMs, the international operating voltage is expected to decrease to approximately 1.5 V for the 256 Mb to 1 Gbit D R A M generation. Although changing the external supply voltage is effective in reducing power dissipation, it is inconvenient for many users. Therefore, D R A M s that cover the wide operating voltage range from 1.5 to 3.3 or 5 V are increasingly important. Figure 16 shows the universal-lice concept, which covers a wide operating voltage range from 1.5 to 3.6 V. A dual voltage limiter ensures the reliability of the MOS devices in the I/O buffers. A two way power supply unit provides a constant internal operating voltage Fin, of c a . 1.5 V to ensure the reliability of the scaled MOS devices. Thus, the D R A M core always operates at around 1.5V, independently of the Switching En_erclyof Electron Devices and Brain Cell lo z ~
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Challenges for giga-scale integration external I~2c, as shown here. This universal-Vet concept will be an essential technique for future high density memories. To gain competitive advantages in performance, and cost of microprocessor and other logic LSIs, we are developing a new circuit technology named LEAP (lean integration with pass transistors) [13]. Pass-transistor circuits have an inherent advantage, that is, both charging and discharging can be done by a single transistor. Therefore, complex functions are achieved with a small number of transistors. In contrast, both pMOS and nMOS are needed to charge and discharge this capacitance in conventional CMOS. In actual ULSIs, however, pass-transistor logic has been used in a small portion of arithmetic macros. The major reason for this is that there is no established design methodology or tools for forming general logic functions. We cleared this hurdle by establishing the first top-down pass transistor logic design scheme called LEAP. The goal is to replace all CMOS circuits with pass transistors and achieve a major leap in value and cost of LSIs. The function of a logic block is given in a hardware description language such as VHDL. Pass-transistor
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logic circuits are then synthesized by the new tool, Circuit Inventor. Here, a binary decision diagram, BDD, is intensively used instead of conventional Boolean minimization, because the function of pass-transistor logic, selecting one of two data according to the control signal, is a "binary decision" itself and suits the BDD. The Circuit Inventor refers to this pass-transistor cell library, which consists of multiplexers. The unique feature of this library is that it does not include the more familiar cell functions, like N A N D or NOR. Those functions are replaced by the multiplexers. The netlist generated using the pass-transistor cells is used in automatic placement and router to produce mask layout patterns. One important issue to be clarified before using pass transistors is whether they work under the lower supply voltages. The nMOS pass transistors are believed to have poorer low-voltage performance than CMOS circuits, which might raise doubt about future applicability. Although the delay becomes larger than that of the CMOS when we reduce the supply voltage without reducing the threshold voltage, as shown in Fig. 17, in realistic situations LEAP is always faster than CMOS. LEAP has been
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shown to be faster than CMOS if the supply voltage is 2.7 times larger than the threshold voltage, which has always been satisfied in real LSIs. Benchmark tests of a 4b Adder/Subtracter show that delay and power are improved by roughly 30-40% (Fig. 18). The total performance-cost ratio, which is defined as the product of these three figures, is three times as high as that of the conventional CMOS circuits. Reducing power supply voltage will be regarded as reducing the switching energy. Figure 19 compares the switching energies of various electron devices with that of a human brain cell. It should be noted that the value for the deep-submicron CMOS technology is very close to the estimated value for the brain cell. This implies that, in addition to the conventional scaling, we may have to use new architectures such as the massively parallel processing architecture of the brain, in order to further increase processing capability without increasing the switching energy per function, as long as room temperature operation is required for PDA and multimedia uses.
6. METALLIZATION--Cu, LOW e AND CMP Interconnection technology is becoming increasingly important, particularly in logic circuits. Figure 20 shows the trend of metallization, with sheet resistance as the criterion. An A1 monolayer is limited in the region of 1/~m, due to stress migration. After that, Al-rare metal multilayers have been used, but electromigration is a limiting factor near 0.2#m. In that case, there is a mixed use of multilayers and W. After that, Cu and grain-controlled AI will be important [14]. This figure also shows the effect of AI grain size on electromigration. Larger grains provide higher resistance against electromigration. Also, grain size is strongly dependent on barrier metals. Figure 21 shows stress-migration lifetime as a function of feature size. It is clear that in the submicron region, monolayer AISi and AICuSi can not be used. Even Cu has poor stress-migration reliability in the region less than 0.2/~m. Thus, layered AI and Cu are important. In terms of AI
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Challenges for giga-scale integration mono-layer stress-migration lifetime as a function of mechanical stress, a thinner passivation layer and a lower passivation growth temperature provide higher lifetime. This implies that low temperature processes are important. Metallization technology, including CMP (Chemical Mechanical Polishing), should be developed with application to logic circuits, as well as to memories, in mind. Furthermore, interlevel dielectric reliability and a lower dielectric constant e ( < 3) will be needed to achieve higher performance microprocessors.
7. LITHOGRAPHY--PATTERN SIZE
FLUCTUATION Among the fine-line patterning technologies, the lithography system is so important that its selection for each VLSI generation is a key factor in business success. Lithography systems, consisting of exposure tools, masks, resist materials and etching processes, require a large initial investment and have a large impact on factory operating cost. Thus, lithography has dominated fabrication technology. Given its importance, new concepts in lithography might also pave the way to future, low-cost submicron processes. The debatable issue is which technologies are most promising for lithography systems in the regions of 0.3~0.1/~m--optical, e-beam, proximity X-ray or projection X-ray lithography. Also, below 0.2/~m, resist pattern size fluctuation reflecting the
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So far, optical lithography has always been pushed to its limit not only by using shorter wavelengths [1] (from g-line and i-line to excimer lasers: KrF and ArF, etc.), but also by controlling the wave phase, e.g. phase shift methods and spatial filtering methods. Such super high resolution techniques are still preventing e-beam and X-ray lithographies from entering production lines. Due to such great advances, it can be said that the resolution limit of optical lithography will be extended down to about 0.15/~m (corresponding to l Gbit DRAMs). Some have argued that 0.125/~m may be possible using an excimer laser and reflection optics. Depth of focus (DOF) is also very important for lithography, because the sum of VLSI topography, wafer variation and focus-plane positioning control often exceeds 1 #m. At the moment, new technologies are being used to overcome planarization problems. One is grooving Si substrates, resulting in recessed high-aspect-ratio features. Another approach is to use chemical mechanical polishing. Figure 22 shows a recessed stacked capacitor cell technology used to reduce the high aspect ratio features of 256 Mbit DRAMs. To reduce the difference in D O F between the memory array and peripheral circuits, the Si substrate at the memory area was grooved using an oxidation process at the beginning of the fabrication process.
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Challenges for giga-scale integration Among several approaches to realize planarization, the CMP method can provide almost perfect planarization in a whole wafer region. Such perfect planarization results in an improvement of resolution. Thus, the resolution limit of optical lithography will also be extended. The superiority of optical lithography will therefore continue for a while. In this case, it is important to develop phase-shift masks and to implement modified illumination in a total system with mass-production reliability in mind. However, it may be impossible for optical lithography (even A r F and F2 excimer lasers) to invade regions less than 0.1/~m. Therefore, other lithography systems will inevitably be introduced for use in the nanometer regions. 7.2. Electron-beam lithography Electron-beam lithography is now being used mainly for making reticles, the direct writing of wire fabrication for ASICs (application specific ICs) and the feasibility checking of small sized devices, i.e. not for mass-production. Each purpose has different requirements: reticle making requires a high positioning/overlay accuracy in a large area, direct writing of VLSIs needs a high throughput, and feasibility checking of scaled MOS devices and mesoscopic (quantum) devices requires ultra-fine patterning. There is still a severe trade-off between throughput and accuracy/fine-line patterning. This fact strongly calls for a new breakthrough that simultaneously satisfies high throughput and high accuracy. Figure 23 shows the figures of merit for each lithography system. The definition of figure of merit is throughput per resolution times registration. In terms of electron beam lithography, the present cell projection approach [15] is limited by cell pattern distortion due to aberrations in the objective lens. This strongly demands low-distortion optics. However, even using such a low-distortion lens, the cell projection method will be limited by the fabrication limit of cell aperture with a higher aspect ratio as device dimensions are scaled down. Even if the cell aperture material is changed from Si to W, such a fabrication limit will occur. Therefore, a new concept aiming at high throughput is strongly required. Recently, such new concepts as multicolumns have been proposed, but do not seem to be sufficient. On the other hand, in regard to the reticles for optical and projection X-ray lithographies, the chip size becomes increasingly large with the down-scaling of device dimensions, and as a matter of course, a larger reticle will be required, leading to a further increase in exposure field in the stepper optics. This requires a decrease in demagnification, e.g. from 1:5 to 1:4, resulting in a more severe positioning/overlay accuracy. E.g. with a 0.15 k~m design rule, the total error budget on the wafer is 0.05/~m, which is one third of the design rule, that includes the error
999
budget for the reticle (0.007/~m), resulting in a 0.035/~m overlay accuracy in the case of 1-5 demagnification. In the case of 1-4 demagnification, the required overlay accuracy is more severe. This is a significant point for future reticle making electronbeam systems. With regard to resist pattern edge roughness [16], caused by the resist molecular size, Fig. 24 demonstrates the significant impact of molecular size induced pattern fluctuation on resolution limits. This implies that smaller molecular size without sacrificing resolution will be important. 7.3. Proximity X-ray lithography Although it is commonly said that proximity X-ray lithography is the most promising technique in the replication of patterns as small as 100 nm or less, there will be a new physical phenomenon different from diffraction, which will determine the resolution limitation. These are the waveguide effect and the secondary electron effect. The waveguide effect is due to the interaction of many waves reflected from mask patterns, which leads to the degradation of
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resolution. The secondary electrons include those excited in the resist polymer and those from the substrates. These electrons cause proximity effects in the same way as e-beam lithography. In addition, a more severe constraint on proximity X-ray lithography is mask accuracy, as shown in Fig. 25. It should be noted that the required accuracy for a 0.1 pm design rule is much more severe than for the present status and the technical limit of the electron beam system. Furthermore, the pattern displacement due to absorber stress reduces mask accuracy. Thus, the practical limit of proximity X-ray lithography is approximately 0.1/~m. 7.4. Projection X-ray lithography Projection X-ray lithography is known to have severe constraints, such as a l-nm-figure-accuracy of aspherical mirrors with multilayers (e.g. Mo/Si) in the 0.1 pm design rule and a reflectivity greater than 60%. However, in principle, the resolution limit of the projection X-ray lithography system can be extended to ca. 30 nm. Of course, in the same way as for optical lithography, the phase-shift method can be used. A final constraint on the resolution is a deteriorated reflectivity determined by a degraded figure accuracy of mirrors. E.g. the accuracy of a spherical mirror for 4 Gbit D R A M s is, surprisingly, ! nm. To achieve such an accuracy, sophisticated
metroiogy is needed. Furthermore, from the viewpoint of throughput, e.g. 20 wafers/h, the requirements for multilayer reflectivity depend on the X-ray wavelength. A 60% reflectivity for the Mo/Si multilayer has been achieved. Using this Schwarzschild imaging system, we have succeeded in fabricating a 0.07/~m resist pattern (Fig. 26). Another problem for future lithography is alignment accuracy. With down-scaling of device dimensions, the alignment accuracy demanded is more severe. The limitation of conventional alignment is approximately 0.05/~m, which corresponds to, at most 256 Mbit DRAMs. Wafer rear surface alignment is strongly needed because there is less influence on the fabrication process. The limitation of rear surface alignment can be less than 0.02 pm. In terms of device damages caused by each lithography, the details have not yet been made clear, but in the regions below 0.1 #m, much attention should be paid to oxide damage (e.g. neutral trap formation). 8. CONCLUSIONS At the beginning of the 21st century, gigascale memories and GIPS processors with device
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dimensions as small as 0.1/zm or less, could appear in the production level. Consequently, the attitude toward U L S I development should be changed along with the inevitable technology and social paradigm shifts. An overview of new challenges to the coming GSI technology was discussed in this paper. The key words are high performance, high reliability, and highly diversified U L S I applications under low cost and low power with customer satisfaction in mind. H o w can we manage these inconsistent trade-offs? We will have to cope with the new wave and a new paradigm that are quite different from the down-scaling approaches. A new challenge to G S I reliability such as building-in reliability will be strongly required. Fortunately, such new user-oriented systems as game softwares and chips, and such multimedia systems as " K a r a o k e " have already been developed. These experiences encourage us to open the new GSI era. Also with new approaches to D A / C A D systems including virtual factories, as well as U L S I technology, we can pave the way for intelligent GSls in the 21st century.
REFERENCES
1. Horiguchi, M. et al., An experimental 220-MHz 1 Gb DRAM. IEEE ISSCC, 1995, 252-253. 2. Doering, R. R., Trends in single-wafer processing, 1992 Syrup. on VLSI Techn. Dig. o f Technical Papers, 1992, pp. 2-5. 3. Kushiyama, N., Ohshima, S., Stark, D., Sakurai, K., Takase, K., Furuyama, T., Barth, R., Dillon, J., Gasbarro, J., Griffin, M., Horowitz, M., Lee, V., Lee, W. and Leung, W., Symposium on V L S I Circuits, 1992, pp. 66-67. 4. Kume, H. et al., 1EEE IEDM, 1992, 991-993. 5. Masuoka, F. et al., 1EEE I E D M 1984, 464-467. 6. Takeda, E. et al., IRPS, 1991, 118-122. 7. Hisamoto, D. et al., IEEE IEDM, 1991, 959-961. 8. Yano, K. et al., IEEE IEDM, 1993, 541-544. 9. Ishimaru, K. et al., IEEE IEDM, 1995, pp. 673-676. 10. Hiraki, N. et al., 1SSCC, 1992, pp. 48-49. 11. Shimohigashi, K. and Seki, K., Symposium on VLS1 Circuits, 1992, pp. 54-58. 12. Nakagome, Y. et al., ESSCIRC, 1990, pp. 118 121. 13. Yano, K. et al., IEEE 1994 Custom Integrated Circuit Conf., pp. 603-606. 14. Miyazaki, H. et al., 1994 Fall Meeting o f the Material Research Society El.6, pp. 175-176. 15. Sakitani, Y. et al., J. Vac. Science Technol. B, 1992, 10(6), 2759-2763. 16. Scheckler, E. W. et al., 1993 Symposium on VLSI Technology, pp. 149-150.
Pergamon
PII: S0026-2714(96)00261-2
© 1997 ElsevierScienceLtd All rights reserved.Printed in Great Britain oo26-2714/97 $17.0o+ o.o0
CHALLENGES FOR GIGA-SCALE INTEGRATION EIJI T A K E D A Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan (Received 1 September 1995)
Abstract--The "giga-chip era" has begun, A new challenging approach to ULSI reliability is now greatly needed in response to the "paradigm shift" now being brought about by simple scaling limitations, increased process complexity, and diversified ULSI application to advanced multimedia and personal digital assistant (PDA) systems. A good example of this shift is the new movement from simple failure analysis by sampling the output of a manufacturing line to the "building-in-reliability" approach. To pursue this technique, greater importance will be attached to a deeper physical understanding of the significant relationships between the input variables and product reliability (including frequent use of Computer Aided Design, CAD and Design Automation, DA), and to total concurrent engineering from research labs to production sites. Furthermore, fast, new ULSI testing methods and new yield-enhancing redundancy techniques that reduce costs will be increasingly needed to achieve high reliability for ULSIs with 109devices on a single chip. Only with these approaches can we pave the way for giga-scale integration (GSI) in the 21st century. © 1997 Elsevier Science Ltd.
1. INTRODUCTION The "ULSI revolution" that is opening a new epoch in the electronics industry has made remarkable progress to such an extent that 109-10 I° transistors can now be fabricated on a single chip. E.g. current ULSI micro-fabrication technologies are being pushed to new extremes by the D R A M community, thereby expediting research on 1 Gbit D R A M s [1] using a 0.16/lm design rule. Also, sophisticated micro-processors using 0.15 #m MOSFETs could possibly appear at the beginning of the 21st century. From the manufacturing standpoint, process and device technologies in the deep-submicron region (0.1--0.3/~m) are, however, approaching practical limits and thus coincident achievement of high performance, high packing density, and high reliability is expected to become increasingly difficult. Furthermore, due to the large initial investment required by the fabrication process complexity, the ultimate profitability of a large investment has recently become a significant issue in the semiconductor industry. Thus, there is an urgent need to reduce fabrication process costs by developing new approaches such as single wafer processing [2] and tool clustering, and increasing automation of process and factory control. Additionally, new approaches to ULSI systems and architectures have been proposed to enhance the total performance of systems and to reduce system cost. Examples include the RAMBUS interface [3] and synchronous DRAMs that overcome bandwidth bottlenecks. Judging from the present trend ("paradigm shift") in ULSIs, it is now more important
to make ULSI chips and systems more profitable by adding value--market breakthroughs, and simplify fabrication processes for higher reliability and standardization--production breakthroughs, as well as ultra-scaling breakthroughs. For scaled MOSFETs, hot-carrier effects are still important even under low supply voltages (less than 3 V), and the Vth-scaling required for power supply voltage reduction and associated shortchannel effect (e.g. punch-through), is now demanding much attention. Moreover, it is not too much to say that ULSIs have been developed mainly with continued reliability in mind. For each generation, device and memory structures, fabrication processes, and materials have so far been determined by the need to overcome reliability problems, such as soft-error phenomena in ULSI memories, dielectric breakdown in insulators, and electro- and stress-migration in the interconnection. This tendency will continue. However, according to the current technology paradigm shift and ULSI business changes, a new strategy for ULSI technology must be introduced to realize giga-scale and nanometer LSIs. In this paper, state-of-the-art ULSI technology is reviewed and the new reliability challenges for giga-scale integration (GSI) are considered. 2. DRAM TECHNOLOGY--FERROELECTRIC MATERIALS
Japanese ULSI technology and business have made great progress by using D R A M s as a technology driver and business strategy in the past 20 years. A key word was down-scaling of device dimensions,
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between CPUs and memories. The former strongly requires use of ferroelectric materials such as PZTs in the memory capacitor; the latter requires D R A M s to shift to more system-oriented applications. The trend in device parameters for each D R A M generation is shown in Fig. 2. It should be noted that
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the down-scaling of capacitor size and capacitor dielectric thickness is leveling off because of physical limits, in spite of the still monotonic decrease in cell size. This trend demands complicated threedimensional cell structures, at least up to 256 Mbit DRAMs, resulting in increased bit-cost. The increase in process steps due to device complexity is demonstrated in Fig. 3. The key technology used for each generation is also shown in Fig. 3. These approaches have aimed at high performance and high packing density rather than low process cost. Thus, the number of process steps has been increasing with every D R A M generation. The solution to this problem is the use of ferroelectric materials such as PZT as a capacitor insulator. The process step advantage gained from the use of PZT materials is shown in Fig. 4. A drastic
decrease in process steps is seen in ferroelectric DRAMs. However, it is very difficult, although urgent, to enhance the quality of ferroelectric films up to production level. At the moment, a dielectric constant of 1000 at 0.1/~m thickness has been achieved, which corresponds to I Gbit DRAMs. Leakage current is also an important factor. What is even more significant is the dependence of dielectric constant on film thickness (Fig. 5). It should be noted that the dielectric constant decreases as film thickness decreases. The physical mechanism for this phenomenon is not yet clear. Discovering this important mechanism will lead to ideal ferroelectric DRAMs that make good use of PZT polarization. The ferroelectric RAM is a non-volatile DRAM. Figure 6 shows trends in D R A M cell structures.
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Flash non-volatile memories are making good progress with higher speeds than DRAMs (Fig. 7), aiming at application to personal digital assistants (PDA). A key for flash memories is high quality oxide/insulator technology, the same as for DRAMs. In particular, demand for 105-106 write/ erase cycles is very severe for gate oxides and seems to be close to intrinsic oxide breakdown. Therefore, new robust oxides such as N20-oxynitrided oxides are needed. Furthermore, as shown in Fig. 8, in terms of cell size miniaturization, flash memory cells can be more
easily scaled down than D R A M cells. This fact will be important for future PDA applications• Flash memories, rather than DRAMs, may provide a key to the multimedia and PDA systems of the 21st century. The characteristics of an A N D cell [4] are compared with those of NOR cells and N A N D cells [5] in Fig. 9. A N D and N A N D cells use tunneling injection for the write/erase operation, while the NOR cell is operated by hot-carrier injection. Tunneling and hot-carrier injections have different oxide degradation mechanisms. Thus, a different approach is needed to obtain reliable oxides•
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4.1. Hot-carrier effects Hot-carrier effects have determined MOS device structures for many VLSI generations and so have been thoroughly studied. To reduce hot-carrier degradation in scaled MOS devices, two approaches have been taken: (1) hot-carrier resistant device structures such as D D D (double diffused drain), L D D (lightly doped drain) and G O L D (gate-drain overlapped device)--drain/gate engineering--and (2) reduction of power supply voltage (1.5-3 V). The former 5 V power supply suffers from power
consumption and process complexity. The lowvoltage approach must overcome the current drivability issue and low speed (which is caused by non-down-scaling of V,h). A third approach is to make good use of AC (alternating current) effects, including the duty ratio. That calls for a deeper physical understanding of AC hot-carrier phenomena, followed by use of this understanding in the actual device/circuit design and supply voltage selection. Hot-carrier effects are still important,
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Fig. 15. Simulated gate delay time for several Bi-CMOS circuits and CMOS circuit [10].
particularly in logic circuits in 3 V power supply systems, in the trade-off of hot-carrier effects vs performance. In terms of AC hot-carrier effects, inductancenoise-induced-degradation and enhanced degradation specific to AC hot-carrier effects have been reported. Figure 10 shows the source noise (AVs) as a function of the wiring inductance (Z) with channel width (W) as a parameter. It is found that AVs is a logarithmic function of Z and is negligible when Z is smaller than 250 mQ (80 #H). That fact is important for circuit design as well [6]. Figure 11 also shows the ratio of calculated lifetime to measured lifetime as a function of drain voltage. The lifetime measured by the e-beam tester obviously becomes shorter
than the calculated one at voltages above 7 V. This is an enhanced degradation phenomenon. Of course, below 6V, there is obviously good agreement between calculation and experiments. Such an enhanced degradation can be explained in the following way. Neutral traps are generated by hothole injection and subsequently, many hot-electrons are trapped in the neutral traps, leading to the enhanced degradation. That is an intrinsic AC hot-carrier effect. Figure 12 shows hot-carrier breakdown voltage. As can be seen, the 3.3 V supply voltage is a critical point for 0.3/~m MOS devices. Therefore, more attention should be paid to G O L D structures (gate-drain overlapped structure), which has a higher
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hot-carrier breakdown voltage than the LDD structure and higher channel current without severe gate length down-scaling. 4.2. Short-channel effects When MOS devices are scaled down to less than 0.3 #m, short-channel effects are more significant than hot-carrier effects, because the width of the depletion layers surrounding the source/drain is close to the gate length value. In addition, due to the strong demand for lower power consumption, the supply voltage is reduced to 3.3-1.5 V, resulting in the reduction of hot-carrier effects. Thus, more attention must be paid to "substrate engineering" of device structures, such as the punch-through stopper, to suppress the short-channel effects. Under reduced supply voltage, it is important to simultaneously suppress Vth lowering and keep V,, low. Figure 13 shows V,h-lowering characteristics for three types of substrate engineering structures. Type A is the conventional one. Type B has a punch-through stopper within the substrate. Type C is the so-called pocket structure. It should be noted that the pocket structure provides low V,h and highly suppressed V,h lowering. As the ultimate device structure of the substrate engineering method, much attention has recently been paid to thin film SO1 device structures. Although crystal quality problems remain, thin film SOI technology may be able to provide new low cost fabrication processes, as well as higher performance and low power consumption. It will drastically change the isolation process and the memory cell process. Figure 14 shows a new bulk thin film SOl device, DELTA [7]. The reason why the DELTA provides a large channel current is due to the effectively wide channel width and the thin film SOl effect (enhanced mobility).
Besides the conventional device miniaturization approaches, single electron transistors and memories are interesting [8]. Such devices make good use of the Coulomb blockade phenomenon as a device operating principle, because the Coulomb blockade is a more robust physical phenomenon than interference effects such as the AB effect. In addition, the single electron devices provide very low power electronics and very reliable memory devices, which may lead to the ultimate flash memories. The noise issue in the single electron devices is not clear, but at least for the single electron memories, the low-noise might be achieved as an extension of flash non-volatile memories. Thus, device structures from 0.3-0.1/~m should be re-examined from the viewpoints of reliability vs performance and memory vs logic circuits. 4.3. Isolation In order to enhance device performance, drastic approaches such as silicidation of source and drain have been used to a great extent in logic circuits, but not memory circuits. From now on, because of the
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need to reduce the parasitic effects, not only active devices, but also isolation will be more significant, particularly in the 0.3/~m regime, or to a lesser extent, logic circuits. To this end, as the LOCOS isolation is approaching its limits, trench isolation [9] will be more important in regions of 0.2/~m or less. However, the trench isolation has several problems such as side-wall leakage and mechanical stress. Therefore, new device designs that include isolation structures are strongly required.
5. LOW POWER ELECTRONICS--POST CMOS CIRCUITS The advent of personal data processing and communication, coupled with device miniaturization, is strongly calling for low voltage operation. However, various constraints associated with lowering voltage, such as drivability degradation and the controllability of low threshold voltage, have not been solved, thus implying the need for new challenges to "low power electronics". Here, new low voltage devices and circuits are discussed from the viewpoints of CMOS and BiCMOS logic circuits, D R A M , and post-CMOS circuits (pass transistor logics). So far, BiCMOS provides the benefits of the low power dissipation of CMOS and the high output drive capability of bipolar devices. However, under low-supply voltages, the gate delay time significantly increases due to the inherent built-in voltage of the bipolar devices. To overcome this problem, new circuit concepts suitable for low voltage operation have been proposed. Among them, the transiently saturated full-swing BiCMOS (TS-Fs-BiCMOS), which makes good use of the transient saturation technique of the bipolar junction transistors, enables
high-speed operation in the sub 2-V regime. Figure 15 shows simulated dependence of gate delay time on supply voltage. It can be seen that Ts-Fs BiCMOS provides the highest speed [11]. For standard DRAMs, the international operating voltage is expected to decrease to approximately 1.5 V for the 256 Mb to 1 Gbit D R A M generation. Although changing the external supply voltage is effective in reducing power dissipation, it is inconvenient for many users. Therefore, D R A M s that cover the wide operating voltage range from 1.5 to 3.3 or 5 V are increasingly important. Figure 16 shows the universal-lice concept, which covers a wide operating voltage range from 1.5 to 3.6 V. A dual voltage limiter ensures the reliability of the MOS devices in the I/O buffers. A two way power supply unit provides a constant internal operating voltage Fin, of c a . 1.5 V to ensure the reliability of the scaled MOS devices. Thus, the D R A M core always operates at around 1.5V, independently of the Switching En_erclyof Electron Devices and Brain Cell lo z ~
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Challenges for giga-scale integration external I~2c, as shown here. This universal-Vet concept will be an essential technique for future high density memories. To gain competitive advantages in performance, and cost of microprocessor and other logic LSIs, we are developing a new circuit technology named LEAP (lean integration with pass transistors) [13]. Pass-transistor circuits have an inherent advantage, that is, both charging and discharging can be done by a single transistor. Therefore, complex functions are achieved with a small number of transistors. In contrast, both pMOS and nMOS are needed to charge and discharge this capacitance in conventional CMOS. In actual ULSIs, however, pass-transistor logic has been used in a small portion of arithmetic macros. The major reason for this is that there is no established design methodology or tools for forming general logic functions. We cleared this hurdle by establishing the first top-down pass transistor logic design scheme called LEAP. The goal is to replace all CMOS circuits with pass transistors and achieve a major leap in value and cost of LSIs. The function of a logic block is given in a hardware description language such as VHDL. Pass-transistor
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logic circuits are then synthesized by the new tool, Circuit Inventor. Here, a binary decision diagram, BDD, is intensively used instead of conventional Boolean minimization, because the function of pass-transistor logic, selecting one of two data according to the control signal, is a "binary decision" itself and suits the BDD. The Circuit Inventor refers to this pass-transistor cell library, which consists of multiplexers. The unique feature of this library is that it does not include the more familiar cell functions, like N A N D or NOR. Those functions are replaced by the multiplexers. The netlist generated using the pass-transistor cells is used in automatic placement and router to produce mask layout patterns. One important issue to be clarified before using pass transistors is whether they work under the lower supply voltages. The nMOS pass transistors are believed to have poorer low-voltage performance than CMOS circuits, which might raise doubt about future applicability. Although the delay becomes larger than that of the CMOS when we reduce the supply voltage without reducing the threshold voltage, as shown in Fig. 17, in realistic situations LEAP is always faster than CMOS. LEAP has been
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shown to be faster than CMOS if the supply voltage is 2.7 times larger than the threshold voltage, which has always been satisfied in real LSIs. Benchmark tests of a 4b Adder/Subtracter show that delay and power are improved by roughly 30-40% (Fig. 18). The total performance-cost ratio, which is defined as the product of these three figures, is three times as high as that of the conventional CMOS circuits. Reducing power supply voltage will be regarded as reducing the switching energy. Figure 19 compares the switching energies of various electron devices with that of a human brain cell. It should be noted that the value for the deep-submicron CMOS technology is very close to the estimated value for the brain cell. This implies that, in addition to the conventional scaling, we may have to use new architectures such as the massively parallel processing architecture of the brain, in order to further increase processing capability without increasing the switching energy per function, as long as room temperature operation is required for PDA and multimedia uses.
6. METALLIZATION--Cu, LOW e AND CMP Interconnection technology is becoming increasingly important, particularly in logic circuits. Figure 20 shows the trend of metallization, with sheet resistance as the criterion. An A1 monolayer is limited in the region of 1/~m, due to stress migration. After that, Al-rare metal multilayers have been used, but electromigration is a limiting factor near 0.2#m. In that case, there is a mixed use of multilayers and W. After that, Cu and grain-controlled AI will be important [14]. This figure also shows the effect of AI grain size on electromigration. Larger grains provide higher resistance against electromigration. Also, grain size is strongly dependent on barrier metals. Figure 21 shows stress-migration lifetime as a function of feature size. It is clear that in the submicron region, monolayer AISi and AICuSi can not be used. Even Cu has poor stress-migration reliability in the region less than 0.2/~m. Thus, layered AI and Cu are important. In terms of AI
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Challenges for giga-scale integration mono-layer stress-migration lifetime as a function of mechanical stress, a thinner passivation layer and a lower passivation growth temperature provide higher lifetime. This implies that low temperature processes are important. Metallization technology, including CMP (Chemical Mechanical Polishing), should be developed with application to logic circuits, as well as to memories, in mind. Furthermore, interlevel dielectric reliability and a lower dielectric constant e ( < 3) will be needed to achieve higher performance microprocessors.
7. LITHOGRAPHY--PATTERN SIZE
FLUCTUATION Among the fine-line patterning technologies, the lithography system is so important that its selection for each VLSI generation is a key factor in business success. Lithography systems, consisting of exposure tools, masks, resist materials and etching processes, require a large initial investment and have a large impact on factory operating cost. Thus, lithography has dominated fabrication technology. Given its importance, new concepts in lithography might also pave the way to future, low-cost submicron processes. The debatable issue is which technologies are most promising for lithography systems in the regions of 0.3~0.1/~m--optical, e-beam, proximity X-ray or projection X-ray lithography. Also, below 0.2/~m, resist pattern size fluctuation reflecting the
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So far, optical lithography has always been pushed to its limit not only by using shorter wavelengths [1] (from g-line and i-line to excimer lasers: KrF and ArF, etc.), but also by controlling the wave phase, e.g. phase shift methods and spatial filtering methods. Such super high resolution techniques are still preventing e-beam and X-ray lithographies from entering production lines. Due to such great advances, it can be said that the resolution limit of optical lithography will be extended down to about 0.15/~m (corresponding to l Gbit DRAMs). Some have argued that 0.125/~m may be possible using an excimer laser and reflection optics. Depth of focus (DOF) is also very important for lithography, because the sum of VLSI topography, wafer variation and focus-plane positioning control often exceeds 1 #m. At the moment, new technologies are being used to overcome planarization problems. One is grooving Si substrates, resulting in recessed high-aspect-ratio features. Another approach is to use chemical mechanical polishing. Figure 22 shows a recessed stacked capacitor cell technology used to reduce the high aspect ratio features of 256 Mbit DRAMs. To reduce the difference in D O F between the memory array and peripheral circuits, the Si substrate at the memory area was grooved using an oxidation process at the beginning of the fabrication process.
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resolution. The secondary electrons include those excited in the resist polymer and those from the substrates. These electrons cause proximity effects in the same way as e-beam lithography. In addition, a more severe constraint on proximity X-ray lithography is mask accuracy, as shown in Fig. 25. It should be noted that the required accuracy for a 0.1 pm design rule is much more severe than for the present status and the technical limit of the electron beam system. Furthermore, the pattern displacement due to absorber stress reduces mask accuracy. Thus, the practical limit of proximity X-ray lithography is approximately 0.1/~m. 7.4. Projection X-ray lithography Projection X-ray lithography is known to have severe constraints, such as a l-nm-figure-accuracy of aspherical mirrors with multilayers (e.g. Mo/Si) in the 0.1 pm design rule and a reflectivity greater than 60%. However, in principle, the resolution limit of the projection X-ray lithography system can be extended to ca. 30 nm. Of course, in the same way as for optical lithography, the phase-shift method can be used. A final constraint on the resolution is a deteriorated reflectivity determined by a degraded figure accuracy of mirrors. E.g. the accuracy of a spherical mirror for 4 Gbit D R A M s is, surprisingly, ! nm. To achieve such an accuracy, sophisticated
metroiogy is needed. Furthermore, from the viewpoint of throughput, e.g. 20 wafers/h, the requirements for multilayer reflectivity depend on the X-ray wavelength. A 60% reflectivity for the Mo/Si multilayer has been achieved. Using this Schwarzschild imaging system, we have succeeded in fabricating a 0.07/~m resist pattern (Fig. 26). Another problem for future lithography is alignment accuracy. With down-scaling of device dimensions, the alignment accuracy demanded is more severe. The limitation of conventional alignment is approximately 0.05/~m, which corresponds to, at most 256 Mbit DRAMs. Wafer rear surface alignment is strongly needed because there is less influence on the fabrication process. The limitation of rear surface alignment can be less than 0.02 pm. In terms of device damages caused by each lithography, the details have not yet been made clear, but in the regions below 0.1 #m, much attention should be paid to oxide damage (e.g. neutral trap formation). 8. CONCLUSIONS At the beginning of the 21st century, gigascale memories and GIPS processors with device
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dimensions as small as 0.1/zm or less, could appear in the production level. Consequently, the attitude toward U L S I development should be changed along with the inevitable technology and social paradigm shifts. An overview of new challenges to the coming GSI technology was discussed in this paper. The key words are high performance, high reliability, and highly diversified U L S I applications under low cost and low power with customer satisfaction in mind. H o w can we manage these inconsistent trade-offs? We will have to cope with the new wave and a new paradigm that are quite different from the down-scaling approaches. A new challenge to G S I reliability such as building-in reliability will be strongly required. Fortunately, such new user-oriented systems as game softwares and chips, and such multimedia systems as " K a r a o k e " have already been developed. These experiences encourage us to open the new GSI era. Also with new approaches to D A / C A D systems including virtual factories, as well as U L S I technology, we can pave the way for intelligent GSls in the 21st century.
REFERENCES
1. Horiguchi, M. et al., An experimental 220-MHz 1 Gb DRAM. IEEE ISSCC, 1995, 252-253. 2. Doering, R. R., Trends in single-wafer processing, 1992 Syrup. on VLSI Techn. Dig. o f Technical Papers, 1992, pp. 2-5. 3. Kushiyama, N., Ohshima, S., Stark, D., Sakurai, K., Takase, K., Furuyama, T., Barth, R., Dillon, J., Gasbarro, J., Griffin, M., Horowitz, M., Lee, V., Lee, W. and Leung, W., Symposium on V L S I Circuits, 1992, pp. 66-67. 4. Kume, H. et al., 1EEE IEDM, 1992, 991-993. 5. Masuoka, F. et al., 1EEE I E D M 1984, 464-467. 6. Takeda, E. et al., IRPS, 1991, 118-122. 7. Hisamoto, D. et al., IEEE IEDM, 1991, 959-961. 8. Yano, K. et al., IEEE IEDM, 1993, 541-544. 9. Ishimaru, K. et al., IEEE IEDM, 1995, pp. 673-676. 10. Hiraki, N. et al., 1SSCC, 1992, pp. 48-49. 11. Shimohigashi, K. and Seki, K., Symposium on VLS1 Circuits, 1992, pp. 54-58. 12. Nakagome, Y. et al., ESSCIRC, 1990, pp. 118 121. 13. Yano, K. et al., IEEE 1994 Custom Integrated Circuit Conf., pp. 603-606. 14. Miyazaki, H. et al., 1994 Fall Meeting o f the Material Research Society El.6, pp. 175-176. 15. Sakitani, Y. et al., J. Vac. Science Technol. B, 1992, 10(6), 2759-2763. 16. Scheckler, E. W. et al., 1993 Symposium on VLSI Technology, pp. 149-150.