Challenges of Ta2O5 as high-k dielectric for nanoscale DRAMs

Microelectronics Reliability 47 (2007) 913–923 www.elsevier.com/locate/microrel

Introductory Invited Paper

Challenges of Ta2O5 as high-k dielectric for nanoscale DRAMs

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E. Atanassova *, A. Paskaleva Institute of Solid State Physics, Bulgarian Academy of Science, 72 Tzarigradsko Chaussee, 1784 Sofia, Bulgaria Received 6 June 2006 Available online 14 September 2006

Abstract The present status, successes, challenges and future of Ta2O5, and mixed Ta2O5-based high-k layers as active component in storage capacitors of nanoscale DRAMs are discussed. The engineering of new Ta2O5-based dielectrics (doped Ta2O5 and multicomponent Ta2O5-based high-k dielectrics) as well as of metal/high-k interface in MIM capacitor configuration are identified as critical factors for further reduction of EOT value below 1 nm.  2006 Elsevier Ltd. All rights reserved.

1. Introduction ‘‘Yesterday is history Tomorrow is mystery Today is a gift. . .’’ Eleonor Roosevelt The continuous scaling of Si devices has guided the microelectronics into the era of nanoelectronics when the components are with nanoscale dimensions (the so-called top-down approach of nanotechnology which is a characteristic of microelectronics). While manufacture aspects dominated the problems of scaling in the past, one now faces the first fundamental physical limitations as structures approach atomic dimensions. The thickness of SiO2 used now is about and below 1.4 nm (the theoretical limit enough to reach the band gap of SiO2 and to show characteristics close to these of bulk oxide is about two monolayers). The most effective approach to overcome the fundamental limits for SiO2-device scaling is the use of new, alternative dielectrics with high dielectric constant k.1 With high-k q

An earlier version of this paper was published in the Proceedings of the 25th International Conference on Microelectronics, Belgrade, 14–17 May 2006. p. 47–54. * Corresponding author. Tel.: +359 2 975 36 32; fax: +359 2 714 44 48. E-mail address: [email protected] (E. Atanassova). 1 The relative permittivity is often given by e; since always k  e, k and e can be used interchangeable without loss of meaning. 0026-2714/$ - see front matter  2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2006.06.006

dielectrics the desired equivalent oxide thickness (EOT)2 can be achieved concurrently with a reduced current by increasing the physical thickness. A number of high-k dielectrics and fabrication processes are currently under investigation. There are urgent questions facing the Si industry today: when high-k? what k and what dielectric? The answer to this complex question depends on both the technology node and the device type, DRAM or MOSFET. Here we will focus only on the case of DRAMs. In fact, in DRAMs as well as in MOSFETs, the thickness of the present dielectrics is becoming sufficiently thin and leakage currents increase to intolerable level. The current densities corresponding to various thicknesses of SiO2 in the range of 1–3.5 nm as a function of applied voltage are nearly the same for DRAMs and FETs. Transistors have only more lenient leakage current requirements. For ultra-thin dielectric the leakage mechanism is quantum mechanical tunneling which ultimately cannot be mitigated by improvement of dielectric quality. This results in a real limit to the minimum useful dielectric thickness for SiO2, independently of the device type using the dielectric as an active component. For memory applications the scaling of EOT is more aggressive, and a specific problem appears for dynamic memories in nanoscale – so called minimum cell capacitance value. The reduction of capacitor area in DRAMs has made

2

Thickness of any dielectric scaled by ratio of its e to that of SiO2.

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it difficult to maintain the storage charge needed for stable operation of memory cell to prevent soft errors caused by a-particles and cosmic rays radiation. The capacitance should not be less than 25 fF/cell so that stable cell operation can be guaranteed. For nanoscale memories, however, there is not much room for achieving high capacitance by scaling down the dielectric thickness or expanding the capacitor area. In addition, the classical MOS physics is no longer valid for extremely thin SiO2 and the layers show effects of quantum behavior. It seems as if the nature says that the scaling can not go on forever. The excellent electrical properties of the magic couple Si–SiO2 clearly present significant challenges for any new alternative dielectric candidate. The concept of using high-k dielectrics to obtain the same EOT so as to reduce the tunneling current was presented more a decade ago, and the research efforts have continued ever since. The introduction of high-k materials becomes more and more urgent – one of the major issues is to find the most suitable material that can replace SiO2. The alternative insulators must meet a set of criteria. It is essential to distinguish the requirements for DRAMs and FETs. Memory capacitors require low leakage current and high capacitance density for charge storage, while the interface quality is not that critical. Memory capacitors require control of the interface primary to limit interfacial reactions to keep the total capacitance high. Since the main requirement is the capacitor stored charge, current transport along the interface is not critically important. Furthermore, no electric field penetration is required below the bottom electrode, so that it may be metal or poly-Si. Therefore, the key parameters to be optimized for dielectric in DRAMs are the leakage current and the dielectric constant, and the purpose is to obtain films with high-k and extremely low leakage current. Naturally the dielectric selection for storage capacitors began by focusing on candidates with the highest e. Consequently, in the course of this process it became clear that the relative impact of the other films’ related parameters has to be considered. Although the understanding of the high-k dielectrics is increasing at a very rapid pace, a lot of unresolved problems on material stability and electrical performance are still laying ahead. The high-k films enable reduction of currents to tolerable levels but the preparation of such dielectric with a good uniformity and composition control at an atomic level is proving to be a very challenging problem which is directly related to the major challenge with high-k layers – achieving EOT of at most 1 nm. Finding a material to replace SiO2 is a formidable challenge because SiO2 is a nearly perfect dielectric. The only notable drawback of SiO2 is its relatively low e, and it turned out to be the major issue giving rise to the end of the long successive SiO2 story at the entrance of microelectronics in the nanoscale. At present no material can fully replace SiO2 for DRAM applications. Among the metal oxides Ta2O5 is the strongest candidate and Ta2O5-based memories are already in production. Ta2O5 with high e, high breakdown fields, low leakage cur-

rent tolerable for Gigabit DRAMs and excellent step coverage characteristics can be obtained by a number of methods compatible with Si technology [1,2]. The essential parameter, however, which favors Ta2O5 in terms of memory applications is its value of stored charge, usually several times higher than other candidates. (Maximum stored charge can be represented by the permittivity and breakdown field, Qmax = eEbd.) The purpose of this paper is to illustrate the existing complex issues for the use of Ta2O5 as high-k oxide in storage capacitors; to point out its present status and potency for future applications, as well as the extent to which Ta2O5 is different to SiO2 and to other high-k insulators. 2. Factors affecting the key parameters of Ta2O5 as a dielectric in storage capacitor The major focus of Ta2O5 research is to improve e and leakage currents by appropriate technological steps. The later one has stronger impact on the memory effect because not only a layer with high-k is needed but the layer also has to keep the current within reasonable limits. e and current depend on films related parameters which reflect on one hand fundamental materials properties (band structure, barrier height at Ta2O5/Si interface, density and nature of bulk traps and slow states, thermal stability in contact with Si) and on the other hand device performance issues such as the quality of two interfaces (at gate and at Si) and longterm reliability. Since leakage is the primary reason for switching to high-k dielectric it is necessary to understand the current transport mechanisms in a given dielectric. The conduction process identified in Ta2O5 is generally attributed to Poole–Frenkel (PF) (including modified one) and Schottky emission. The current is rather bulk than electrode-limited and the component corresponding to hopping of electrons from one to another state is essential in many cases. The modified PF mechanism appears when the film contains neutral and donor traps. Space charge limited current is more probable for thick films. Since the specific intrinsic properties of Ta2O5 are completely different from those of SiO2, the nature of leakage current should be studied in close relation to the preparation conditions considering information on bulk traps and slow states. The detailed understanding of the conductivity is complicated by the presence of interfacial layer which is typically SiO2-like, lower-k layer (k values are between those of SiO2 and Si). A lack of reliable experimental data for barrier heights for electrons and holes in Ta2O5-based capacitors causes additional difficulties in data analysis. Which are the key parameters that could determine the success in improving dielectric constant and the leakage current? Several fundamental ones are considered. 2.1. Film microstructure and stoichiometry One of the advantages of Ta2O5 is its high e. (e is the static dielectric constant extracted from Hf C–V curves under

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accumulation. The optical dielectric constant is given by the refractive index squared and is typically 4–5.) There are efficient technologies giving films with a dielectric constant of bulk oxide from 20 to 40 and even higher, up to 50–55 for specially doped Ta2O5 [3–6]. Although it is possible to obtain films with high e the presence of interfacial layer compromises the benefits of Ta2O5 as a high-k material, and effectively reduces the dielectric constant of the stack (interfacial layer and bulk Ta2O5 behave as two serially connected capacitors). Usually e increases with increasing film thickness due to the microstructural properties of the films and their changes with thickness. By relevant annealing [3,4] it is possible to improve the film stoichiometry, to make more abrupt interfaces at two electrodes, to reduce structural non-perfections, and by this way to control and maximize e even for films obtained by conventional methods (bulk dielectric constant et of sputtered Ta2O5 can be increased from 25 to 37 after O2 annealing at 850  C [5]). In terms of high desirable dielectric constant of the bulk Ta2O5, the problems are generally solved. 2.2. Band gap and band offsets The higher e comes at the expense of a smaller band gap and lower conduction and valence band offsets between Si and Ta2O5. The small DEc value (calculated conduction band offset, DEc is 0.4 eV [7]) correlates with high leakage current, i.e. the trade-off between e and band offsets tend to limit the advantage of pure Ta2O5 as high-k oxide. However, the values of barrier heights are not a critical factor for dynamic memories, in contrary to FET where the transistor performance depends fundamentally on the quality of the interface that determines carrier mobility and device stability. Since Ta2O5 does not have reported reliable experimental values of DEc, the closest most readily alternative indicator for the band offsets is the band gap Eg. The value of Eg  4.5 eV (± 0.3 eV) has been obtained, i.e. relatively low. At the same time Ta2O5 capacitors typically exhibit low leakage currents, up to several orders of magnitude lower currents than electrically equivalent SiO2, indicating that Ta2O5 has fewer problems than some other materials. It is not possible to realize simultaneously high-k and wide Eg because k varies roughly inversely with the band gap [2]. The relatively small values of Eg and DEc of high-k insulators originate from their electronic structure which is qualitatively different from that of SiO2 and Si–oxynitride, (the lowest conduction band offset energy is determined by the d-state energy of metal atom). When discussing tolerable levels of leakage currents it should be noted that leakage limits are application dependent and the aim has to be by balancing e and Eg to achieve desirable low current and stable stored charge. Eg could be increased by doping of pure Ta2O5 with Hf and Zr (Fig. 1). Since many factors affect on both k and Eg the detailed relationship between permitivity and Eg is not trivial. On the other hand, there is not unique value of DEc and the band offsets to Si can be additionally influenced by the interfacial layer.

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Fig. 1. O1s energy loss spectra for 10 nm layer [6].

The local bonding at the interface could add an extra interfacial dipole, which modifies barrier heights [2,7]. Our results revealed that by preliminary nitridation of Si surface the conduction band offset in the Ta2O5/SiON/Si stack can be increased to 1.3 eV, which is significantly higher than the theoretically predicted value of 0.4 eV for Ta2O5/Si interface, and even higher than critical value for MOSFETs application. 2.3. Ta2O5/Si interface SiO2-like layer inevitably presents between Si and high-k film due to the thermodynamic instability of high-k materials in direct contact with Si (thermodynamic considerations show that Si reduces Ta2O5 forming an interfacial layer [8]). The growth of this layer is favored by the active oxidizing ambient during film deposition. This lower-k layer decreases the global dielectric constant, controls the leakage current and may have a large impact on the carrier transport through the capacitor. (Charge build-up at the interface with bulk Ta2O5 modifies the conduction mechanism in the stack and can lead to early breakdown events even at low applied fields.) Its general obstacle is compromising the minimal EOT according to the relation, EOT = ds + (es/ehigh-k)dhigh-k, i.e. EOT will never be less than the thickness ds of the interfacial layer which means that for non-optimized films the interface can even nullify the benefits of Ta2O5 as a high-k film, particularly if its thickness is comparable to the active Ta2O5 thickness. The microstructure and composition of interfacial layer depend strongly on the fabrication conditions. Very often the layer is a mixed one of SiO2 and suboxides of both Ta and Si; the later are located nearer the Si surface [4]. At the beginning of high-k film investigations a common view was that this layer has to be removed. To combat the nature, however, is awfully hopeless! Actually for memory capacitors, it is not necessary to eliminate this layer completely. The efforts to eliminate this layer did not result in better system parameters. The more successful approach is whether the stack can exhibit acceptable leakage and desirable e. The solution here is to suppress the negative

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10-2

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effect of this layer and take advantage of its presence. Thus the interfacial region could be exploited to obtain desirable properties; the actual interface will be controlled by the better Si/SiO2-like one instead of that of Ta2O5/Si. The challenge lies in finding relevant annealing steps without other non-desirable subtle effects. Another option to achieve this is to introduce nitrogen at the Si surface. The formation of SiON interface layer enhances not only the stacked capacitance but also reduces the strain at the interface, minimizes charge traps, increases immunity to hot electron degradation and improves reliability. SiON layers grown by thermal methods are lightly ‘‘doped’’ with N and thus offer only a moderate increase of k of the interface region. A higher doping is possible with ion implantation. The surface nitridation, however, strongly affects the electrical behavior of the capacitor; sometimes additional problems appear. Detailed study of these effects is necessary in order to control the electrical behavior of the capacitor in a desirable manner. Fig. 2 shows representative data of layers on N+ implanted Si. The data suggest the existence of a high density of negatively charged traps in the nitrided layer which act as slow states. This charge modifies the cathode field and hinders electron injection from Si. The temperature stimulated detrapping of electrons results in a strong increase of leakage current. The trapping/ detrapping processes in the interface layer are not reversible and cause much instability of electrical performance. The conduction process is dominated by PF emission from traps at 1 eV below the conduction band of Ta2O5. Fig. 3 illustrates the beneficial effect of N2 post-fabrication annealing at 850 C on 15 nm Ta2O5. The existence of excess Si is established in the interfacial region for the asgrown samples. The annealing improves the stoichiometry and microstructure of both the bulk oxide and the interfacial region which manifests as a reduced amount of suboxides. This is not accompanied either by any oxidation of Si or nitridation processes in the stack. A real reduction of the interfacial region width is detected, making the interface more abrupt.

2.4. Bulk defects and slow states One of the advantages of Ta2O5 is that it can be fabricated by a number of methods completely compatible with Si technology. Owing to the low temperature of deposition high leakage current is very often observed in as-fabricated films. The current originates from bulk traps and slow states. The structural nature of electrically active centers in Ta2O5 is not clarified in details because their parameters are strongly dependent on the preparation conditions. The obvious source of electrically active centers is the intrinsic defects (oxygen vacancies and interstitials, suboxides of Ta and Si, strained and broken Ta–O and Si–O bonds) because high-k oxides contain much more defects than SiO2 and exactly they are responsible for the domination of the bulk-limited conduction mechanism(s) in these oxides. The cause of oxide charge, for example, could be the intrinsic defects as well as extrinsic ones such as hydrogen involved during post-deposition steps. The interfacial region is a preferential location of charge trapping. The source of the charge close to the interface with Si (usually positive but not always) originates from the specific bonding of Ta atoms in this region. Due to the high coordination of Ta, Ta2O5 has high number of bonds, forms an overconstrained interface with Si, and therefore degradation in current is expected. This is why a presence of SiO2-like interfacial layer is not only desirable to gain high-quality interface, but it is even obligatory. This is why it is not necessary to remove this layer – contrary, the challenge here must be addressed to its control so that the interface to be close as possible to this of SiO2/Si. The covalent bonding with a low coordination makes SiO2 an excellent glass former, so that SiO2 is amorphous. The bonding can relax locally to minimize the defect concentrations. The greater ionic character of the bonding and the higher atomic coordination numbers mean that the highk oxides are poor glass formers (it is difficult to maintain these oxides amorphous during high temperature processing). The effect of poor glass forming ability and high coor-

Peak, eV 23.0 23.9 24.9 25.8 27.2 29.1

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E. Atanassova, A. Paskaleva / Microelectronics Reliability 47 (2007) 913–923

98

100 102 104 Binding Energy, eV

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Fig. 3. Decomposition of Ta 4f and of Si 2p spectra at a distance 14 nm from the surface [10].

50 40 % Failures

dination is that the oxides have higher defect concentrations. These oxides have very high heats of formation, so the equilibrium concentration of non-stoichiometric defects should be low. The non-equilibrium concentration of defects is high because the oxide network is not so able to relax and rebond to remove defects. C–V hysteresis of high-koxides is one of the potential problems limiting the application. The type of slow states and their parameters can be estimated similarly as in devices with SiO2. Dedicated investigations concerning slow states in Ta2O5 stack capacitors practically are missing. As structural imperfections act as electrically active centers they must be effectively annealed. Figs. 4 and 5 illustrate the effect of O2 treatment at 850 C. The process is beneficial for the dielectric constant of bulk oxide and the reduction of oxide charge to 1010 cm 2. The annealing is not accompanied by additional oxidation of Si; it could effectively reduce oxygen vacancies, leading to 3–4 orders of magnitude lower current; it stimulates the increase of optical thickness and of refractive index due to the improved density of the films. A transition from PF mechanism to Schottky emission limited current after annealing is established, i.e. by appropriate technological removal of bulk traps the transition to the desirable electrode-limited mechanism is easily achieved. It suggests that there is a potential to control additionally the current by using relevant top electrodes. The annealed films have higher breakdown fields and the

30 20 10 0 1.6

2.4

3.2 4.0 Ebd, MV/cm

4.8

5.6

Fig. 4. Breakdown histograms of Ta2O5 before (j) and after (h) O2 anneal at 850 C [5].

immunity to radiation damage (c irrad. 106–108 rad) is also improved (Fig. 6). Since the Ta2O5 could be used in radiation rich conditions, it is critical to have knowledge of radiation effects in Ta2O5 devices. At present these effects are very poorly studied. First experiments show that the irradiation will be a problem in terms of leakage current – the extent of the current increase depends on the layer thickness, and the effect is stronger for thinner films and higher doses. Ta2O5 is often heated in H2 in order to check the effect of this commonly used annealing ambient. At present, clear

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) PMA [11]. -9

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Fig. 6. The effect of c irradiation on I–V curves [12].

answer of the question what is the effect of H2 on high-k dielectrics is missing. There is a limited amount of data for the energy level of interstitial atomic hydrogen in some high-k insulators, with respect to the oxide band edges indicating that H acts as a shallow (in ZrO2; HfO2; La2O3; Y2O3) or deep (in Al2O3 and silicates HfSiO4, ZrSiO4) donor levels [7]. Systematical results for the impact of hydrogen on the system Ta2O5/Si are missing. All the same, how does hydrogen behave in Ta2O5? Our results [11] imply that post-metal annealing (PMA) in H2 reduces the oxide charge in thermal Ta2O5 (up to 1010 cm 2) but definitely gives rise to C–V hysteresis indicating a generation

of slow states with a density of 5 · 1011 cm 2; et increases to 35 and the breakdown field slightly improves. The leakage current characteristics are not really affected (Fig. 7) suggesting that even if net annealing of oxide charge occurs the current is not sensitive to this process. It emerges that the annealing has a beneficial effect of reducing both oxide and interface traps; it influences mainly C–V curves while interface states have no effect on the I–V curves. Hydrogen undoubtedly involves slow states, i.e. worsens the interfacial region (most likely the part closer to Ta2O5 interface). PMA has rather deleterious than beneficial effect on sputtered Ta2O5 (it makes the oxide charge more positive). It seems the effect of hydrogen strongly depends on the initial parameters of the stack – in one case PMA generally improves whereas in another case degrades the parameters. Evidently, it is difficult to make an explicit inference and to identify the effect of hydrogen on the behavior of the capacitors without a detailed consideration of the processing conditions and of the charge state of hydrogen (H+, H or H0) taking part in that process. Every interpretation of data must also consider the key role of SiO2-like interfacial layer and its strong sensitivity to hydrogen (effective passivation of interface traps with hydrogen). Usually hydrogen tends to reduce high-k oxides. Thus the final effect of PMA can be a result of two competing processes (reduction of bulk Ta2O5 and annealing of interface region) and the domination of one of them. Obviously a lot of unresolved ‘‘hydrogen’’ problems are still laying ahead. 2.5. Crystallization effects So far we have discussed how to improve the electrical characteristics of stack by relevant annealing steps. As a typical high-k material, however, Ta2O5 crystallizes if subjected to relatively high temperatures (600–700 C). Although crystalline Ta2O5 has usually a greater e, its current can be higher because the grain boundaries serve as an additional leakage path. On the other hand, it is generally

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Fig. 8. HRTEM micrograph in (1 1 0) projection: (a) as-depos. films; the steps at Si/SiO2 interface are labeled with S; inset – FFT from Si matrix; (b) after anneal at 850 C; Z indicates fringes at Ta2O5/SiO2 interface, ‘a’ RHEED pattern after etching; ‘b’ FFT of Ta2O5 image, two spots correspond to (0 0 1) interplanar distances in orthorhombic Ta2O5; ‘c’ FFT from the region Z (0 0 1) and (1 1 0 0) spots of orthorhombic Ta2O5 [13].

tribution and can give rise to large statistical variation for nanometer devices across the chip. It is essential to introduce alternative dielectric remaining amorphous after device integration. Strategies have been proposed to prevent crystallization and deleterious effects of electrical transport along grain boundaries. Doped Ta2O5 and/or bi-layers containing Ta2O5 are likely to meet these challenges. (10 nm Ta2O5/5 nm Nb2O5 bi-layer has another temperature of crystallization as compared with pure Ta2O5 [14].) The concept of doping high-k oxides is that dopants act as network modifiers, can reduce current and interface state density, can also stabilize the amorphous phase. Acceptable capacitor characteristics are expected and more important they intact after standard device -3

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recognized that the annealing repairs oxygen vacancies and can in some cases effectively reduce leakage current (stimulating annealing as it was mentioned above and established by many authors). Despite of the intensive investigations the exact relationship between the leakage current and crystalline structure of Ta2O5 has not been clarified and seems that it is not possible. This circumstance is related to the fact that the crystallization effects depend by a complex manner on film parameters (including its thickness) and annealing conditions, and each combination film parameters/thermal processing should be studied individually. The exact temperature of crystallization depends on both the thickness and the stoichiometry of the layer (the thinner layer maintains amorphous phase even at 800 C [2]). Fig. 8 illustrates the crystallization effects in sputt. 20 nm Ta2O5 [13]. As deposited and O2 annealed at 800 C films are amorphous whereas the heated ones at 850 C crystallize in orthorhombic b phase (the appearance of crystal phase is confirmed by XRD data as well). The nucleation of crystalline Ta2O5 is well pronounced and (0 0 1) planes are detected. The crystallization process starts inhomogeneously usually at the interface SiO2/ Ta2O5 and is stimulated by the presence of compositional and structural defects. It implies that the crystallization may not be limiting factor for achieving tolerable level of leakage current and after appropriate technological steps stimulating net annealing and suppressing crystallization, it is possible to reach low enough current. The 850 C anneal favors a larger e at a smaller leakage current, but the crystal phase manifests electrically as slow states. Therefore, the results could be discussed in the terms of relative impact of two concurrent mechanisms during treatment – an appearance of crystal phase and real annealing. Generally, the crystallization is undesirable feature since it introduces non-uniformity in the range of grain size. Poly-crystalline dielectrics have non-uniform leakage dis-

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Fig. 10. AFM 3D topography before (a) after (b) 5 s lw irrad. [15].

The top electrode comprises the next part of challenges in capacitor stack. Due to the incompatibility of Si with high-k dielectrics, metal electrodes are proposed to change poly-Si gate and even to develop capacitor in MIM instead MOS configuration. Adding to this challenge is the problem of integrating a metal-gate process in the conventional process flow (the incorporation of metal gates increases the integration complexity). The introduction of metal electrodes introduces its own set of manufacturing and reliability challenges and requires the development of specific process modules and adequate integration schemes. The usefulness of each of metal(s) candidates or memory design depends on their ability to achieve the desired work function and respectively leakage level. One of the key issues here is the control of the electrode work function throughout processing. For example, the effect of various electrodes (Al, W, Au, TiN, TiN/W) on the characteristic of capacitors with Ta2O5 [3,16] shows that some parameters such as interface state densities, breakdown fields and

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charge trapping are defined by the properties of Ta2O5 itself. The dielectric constant, oxide charge, leakage current at high fields, charge to breakdown and stress-induced leakage currents are remarkably affected by the electrode. The nature and spatial distribution of gate-depositioninduced defects are sensitive to the technological process – the effect is so strong that it tends to outweigh the effect of the intrinsic properties (work function) of the gate material. The gate deposition technique and the type of metal electrode have a significant impact on the properties of the capacitors. Two processes are emerging: (i) gate-deposition induced defects in Ta2O5 itself, and (ii) reactions at metal/Ta2O5 interface. These processes define the general parameters of the defects created (microstructural nature, electrical activity, localization), lead to potential lowering of e, and affect the leakage current behavior and conduction mechanisms. Their effect is stronger during electrical stress. A large portion of the generated defects is located within thin interfacial strained layer at the metal/Ta2O5 interface. Al and TiN/W electrodes are preferable in the terms of dielectric constant. All capacitors demonstrated low leakage current (10 7 A/cm2 up to 1 MV/cm) suggesting that these gates have a potential as upper electrodes of Ta2O5 capacitors. At higher fields the current becomes

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integration, i.e. these dielectrics will not require replacement technology, a circumstance of a first meaning for Si industry. Another solution is to find alternative annealing method(s) to replace high temperature heating and consequently to avoid crystallization. We have used microwave radiation at room temperature as an annealing process. The lw radiation can provide low leakage current by improving the film microstructure at strongly reduced thermal budget (room temperature and extremely short times). An improvement of a number of parameters (stoichiometry and microstructure of the layer; leakage current and breakdown fields; surface morphology) (Figs. 9 and 10) is established after 5 s lw irradiation. The capacitance increases with 30% and oxide charge reduces below 1011 cm 2. The irradiation is not accompanied either by crystallization effects or additional oxidation of Si both circumstances indicating that short time lw radiation has a potential to replace high-temperature annealing processes at least for Ta2O5.

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10-9 0 Appl. voltage, V

1

E, MV/cm 10 -8 0.0

0.5

1.0

1.5

Fig. 11. I–V curves for capacitors with various gates [3,16].

E. Atanassova, A. Paskaleva / Microelectronics Reliability 47 (2007) 913–923

dependent on the electrode material regardless that PF mechanism appears to be dominant in the most of the cases. The sputtered TiN is responsible for the higher leakage current observed for TiN and TiN/W gates, i.e. the deposition condition is critical in this case. The low leakage current detected for W and Au gate capacitors (Fig. 11) at higher fields is a natural consequence of the known inertness of these two materials, i.e. in this case the intrinsic properties of the electrode are essential. W deposition is not accompanied by an introduction of a detectable damage. Different defect creation mechanisms during sputtering of W and TiN (two component material) are most likely responsible for the observed behavior of the two type capacitors. The results show that the sputtering technique is a beneficial technology for W deposition ensuring stable gate contact to Ta2O5 and tolerable level of the current, while radiation induced damage during deposition of TiN make this method less favorable in the case of TiN gate. The generated defects during deposition of the top electrode are also responsible for the strong dependence of the conduction mechanism on electrode material, and is a critical factor controlling the conductivity. Their effect can be strong enough to mask the effect of the electrode work function. Therefore, the choice not only of the gate material but its deposition technique remains a concern for Ta2O5. In fact, many of the metals considered for high-k oxides tend to be quite reactive with the dielectric. As a result, the electrical thickness, leakage current and the work function of the electrode itself may be uncontrollably modified during processing. Metal nitrides (TiNx, TiAlN) are interesting candidates since they tend to be more stable in contact with high-k dielectrics than the transition metals. 2.7. Long-term reliability Long-term reliability is directly related to the leakage current and to all problems concerning its reduction. Many questions on the physics of degradation mechanisms in Ta2O5, which are typical of all high-k materials, remain unanswered. Although the reliability research on high-k dielectrics is steadily growing, due to the growing importance of these materials, their detailed reliability characterisation and charge trapping issues are still poorly understood at this stage. There are predictions regarding the intrinsic high-k degradation in terms of extrinsic factors (breakdown is provoked by process-induced defects). The analyses and models are made using mainly the knowledge of SiO2. Many of them, however, are too speculative and are not based on any deeper understanding of the differences between the degradation of SiO2 and high-k materials. For example, the specific structural properties of high-k materials raise the question whether the existing methodology for reliability assessments developed for SiO2, can be applied. In the case of SiO2, a fast accelerated high-voltage electrical stress can be applied to obtain an electron trap generation dependence that can be extrapo-

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lated to low voltages in order to estimate the device lifetime under actual operating conditions. In the case of high-k materials the effect of high and low electrical field stress may be very different: while a high field may cause structural damage, a low field stress is likely to result in less additional structural degradation. Some of the defectrelated issues may be addressed by applying a post-deposition anneal to high-k films. Calculations indicate that N2 and NH3, their ions and derivatives can bond to oxygen vacancies in various charge states or initiate an oxygen substitution process [17] which may passivate the oxide charges and electron-trapping centers. For Ta2O5 (as for many high-k oxides) a strong polarity dependence of the electrical properties was found and explained by the specific band structure of the stack. Electron and hole trapping lead to a distortion in the energy band of the high-k dielectrics, which enhance the dielectric internal electric field and further induces preferential breakdown either in the interfacial layer or in the bulk oxide. This model is able to explain the polarity dependent breakdown observed in high-k stacks [18]. The reliability characteristics of Ta2O5 capacitors are also sensitive to the metal gate [16]: for example, the capacitors with sputtered W; TiN or TiN/W gates are very vulnerable to a CCS degradation; Al capacitors are less sensitive to a stress-induced traps generation; CCS does not create measurable SILC in Au-capacitors. The highest charge to breakdown is observed for Al-gate samples. It emerges that the traps responsible for the bulk trapping and those leading to breakdown are not one and the same. An important part of DRAM development is the ability to predict device lifetimes and failure rates. Ta2O5 failure mechanisms are entirely different from those of SiO2 and the reliability models cannot be simply transferred. Regardless of the progress made in this field many crucial questions remain unanswered (for example, whether or not the oxygen species have a direct role in breakdown). There still is a lack of consensus concerning the mechanism that causes the breakdown in high-k insulators. High-k reliability is still dominated by defect-related degradation mechanisms and remains out of intrinsic explanation. Additionally, the trapping events in high-k dielectrics are with very short time constants compared to the case of SiO2, indicating for the need of pulsed measurements. In summary, the understanding of physical differences between reliability phenomenon of Ta2O5 as high-k oxide and SiO2 is still a future task. 3. Conclusions and future predictions The same electron feature of Ta2O5 as a high-k oxide, that facilitates its desirable k values – the d electron origin of Ta–O bonds – is also responsible for its intrinsic limitations. In a word, the only drawback of SiO2 is its low permittivity, the only advantage of high-k materials is their high-k. Besides intrinsic and integration issues the performance of Ta2O5-based capacitors depends strongly on the fabrication process. In contrast to high quality SiO2 which

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E. Atanassova, A. Paskaleva / Microelectronics Reliability 47 (2007) 913–923

Table 1

DRAM Stacked Capacitor Potential Solutions, ITRS, 2005 (Selected data), [1] Year of production

2007

2010

2013

2016

2019

DRAM ½ - pitch (nm)

65

45

32

22

16

Top Electrode Capacitor Dielectric Material

Metal: Ti, TiN, W, Pt, Ru, RuO2, IrO2 … Ta2O5, Al2O3, HfO2

Ultra high k; new materials,

Ta2O5, TiO2

strontium-based, perovskites ?

Metal: Ti, TiN, W, Pt, Ru, RuO2, IrO2,others

Bottom Electrode EOT at 25fF (nm)

1.1

0.60

0.50

0.4

0.20

Leakage current (nA/cm2)

131.7

124.7

137.4

151.3

183.7

DRAM Trench Capacitor Potential Solutions, ITRS, 2005 (Selected data), [1] Year of Production

2007

2010

2013

2019

DRAM ½ Pitch (nm)

65

45

32

16

EOT, (nm) Upper electrode Dielectric material Bottom electrode

3.9

2.0

Metal

Metal

Metal

1.4

Metal

0.5

High-k

High-k

High-k

High-k

Silicon

1:Silicon

Metal

Metal

2:Metal Capacitor structure/dielectric

solutions exist

Metal-InsulatorSilicon/high-k

1: MIS/High-k

Metal-Insulator-

2: MIM/High-k

Metal/High-k

solutions are known

behaves very much alike regardless of the growth method, the properties of Ta2O5 are very sensitive to the deposition process. The challenge is to prepare films with uniformity and compositional control on the atomic level. However, there are no principal problems limiting the use of Ta2O5 as a dielectric in storage capacitors of nanoscale DRAMs. To gain success in achieving tolerable level of leakage current and high enough capacitance a number of film-related parameters must be carefully and simultaneously optimized. The overcoming of these issues requires persistent efforts in both the fundamental understanding of stack properties and the capacitor engineering. Ta2O5 studies give hope that pure Ta2O5 can be further extended for applications in memory devices of sub-70 nm generations (Table 1). A variety of options exist in this field: chemical modification of Ta2O5 matrix by adding suitable metal agents, development of novel dielectrics using a layered combination of Ta2O5 and other high-k dielectrics. Continuous optimization of the key parameters of these mixed oxides may give an answer of the question how far can we go with Ta2O5. Multicomponent dielectrics based on Ta2O5 emerge as promising contenders to extend the potential of pure Ta2O5. Lower leakage current, higher e, lower EOT and stable amorphous phase can be achieved by controlling the composition and bond structure (more or less oxidized or silicate rich layers can be obtained). On the way of development of these new dielectrics a number of challenges in changing research environment have to be overcome. There is a debate about the various solutions. One point of agreement, however, emerges – a philosophy of continual improvement of the storage capacitor properties. The requirements of

not known solutions

rapid introduction of the modified high-k dielectrics into effective production technologies additionally multiply the challenges. Needless to remember the known enormous task of development of all high-k dielectrics – in a very short time frame to replace the nearly perfect SiO2/Si system with a high-k dielectric based one for the sole reason higher e. A strategy of the investigations in the next stage will be characterised with harmonization of variety of advanced fabrication methods (including epitaxial version of the films) and improved characterisation techniques (electrical and microstructural, considering the specificity of multicomponent high-k layers on Si or metal layer). New technological schemes and deeper understanding of fundamental properties of these materials are necessary to develop real solution for stack capacitor that complies with future roadmap requirements. The techniques currently available for compositional and electrical analysis need to be improved; the complexity of high-k materials requires characterisation with high depth resolution (non-destructive excellent quantitative depth profiling). A reliable methodology for the physical characterisation of very thin high-k layers by combination of techniques with potential for in-line use and classical off-line techniques is necessary. Thus by optimization of the analysis conditions a strong improvement of the data interpretation is expected. A key role in this process will play the modeling. Contrary to FETs where high-k/Si interface remains the critical stopper for integration of high-k materials at circuit level, the introduction of MIM configuration of the capacitors in DRAMs will completely eliminate issues with thermodynamical stability of Ta2O5based high-k layer on Si. Engineering of metal electrode/

E. Atanassova, A. Paskaleva / Microelectronics Reliability 47 (2007) 913–923

high-k interface, the choice of electrodes and how to tune their work functions remain challenging but essential tasks to final solution for successful capacitor integration. The electrode deposition induced damage and respectively poor control of capacitor formation resulting in reduced yield compound the problem with metal gates. In exploring the concept of metal gate and mixed Ta2O5-based dielectrics first results give encouraging indications to believe that the roadmap requirements for future technology nodes will be reached. Although the interface Si/high-k will be replaced by Me/high-k one, to achieve sub-1 nm EOT scaling, the growth of the high quality very thin high-k films and respectively appropriate interface control are required. In terms of trapped charges and reliability the performance of high-k devices is still rather poor compared to those with SiO2. Insufficient reliability data and a lack of microscopic understanding of the mechanism(s) of degradation in high-k films will motivate future intensive work in this field. It is of paramount importance, however, to first establish an accurate methodology for reliability at circuit level of high-k materials, i.e. the reliability concern of Ta2O5-based layers is a part of the reliability topic of high-k materials. High density of pre-existing traps in high-k materials can even lead to a situation when a given high-k dielectric although preferable from a scaling point of view today, to be problematic from a reliability point of view tomorrow.

[4]

[5]

[6]

[7]

[8] [9]

[10]

[11] [12]

[13]

Acknowledgement

[14]

The work was supported by Bulgarian National Science Foundation, contract F1508.

[15]

References

[16]

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