Si dual-sputtered method for nonvolatile memory application

Microelectronics Reliability 50 (2010) 639–642

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Characteristics optimization of N2O annealing on tungsten nanocrystal with W/Si dual-sputtered method for nonvolatile memory application Jer-Chyi Wang a, Pai-Chi Chou a, Chao-Sung Lai a,*, Wen-Hui Lee a, Chi-Fong Ai b a b

Department of Electronic Engineering, Chang Gung University, Kweishan 333, Taoyuan, Taiwan Institute of Nuclear Energy Research, Atomic Energy Council, Longtan 325, Taoyuan, Taiwan

a r t i c l e

i n f o

Article history: Received 1 December 2009 Received in revised form 6 January 2010 Available online 2 March 2010

a b s t r a c t The tungsten nanocrystals (W-NCs) memories fabricated by W/Si dual-sputtering and O2 and N2O annealing process were investigated. Significant W-NCs dots were formed by N2O annealing and proved by the energy dispersive X-ray spectrometer (EDX) analysis. Superior electrical properties of W-NCs memories were optimized for 20/30 W/Si dual-sputtered ratio, 10–15 nm blocking oxide thickness and N2O annealing at 950 °C. A pronounced capacitance–voltage hysteresis was observed with a memory window of 6.5 V under +9/9 V sweeping. Ó 2010 Elsevier Ltd. All rights reserved.

1. Introduction Since 1985, Flash EEPROM (Electrically Erasable and Programmable Memory) has become the most popular form of nonvolatile memories (NVMs) [1]. For operation, electrons are injected by channel hot electrons into a floating gate (FG) resulting in a threshold voltage shift which is detected via the current sensing. The magnitude of this threshold shift is related to the charge in the FG, the thickness of the control and tunneling oxide, and other device parameters [2]. To achieve the nonvolatility for FG Flash memories, the tunneling oxide thickness has to be maintained thick enough (around 7 nm) so as to prevent FG charge loss toward the contact regions under normal read and retention conditions [3]. However, as tunneling oxide shrinking with device scaling, the tolerance of dielectric leakage will degrade rapidly owing to significant charge loss and will cause serious reliability issues. These drawbacks have compelled FG memories to be inappropriate for future memory technology [4]. To overcome the contradictory problem between the low programming voltage and high nonvolatile characteristics of NVMs, the discrete charge storage concept such as silicon-oxide–nitrideoxide–semiconductor (SONOS) and nanocrystals (NCs) memories were proposed [5,6]. In a NCs memory, the charge loss through lateral paths can be suppressed due to the inter-nanocrystal spacing and therefore thinner tunneling oxide even down to 1.5 nm can be used [7]. Recently, metal NCs memories have attracted more attention owing to some advantages over the semiconductor counterparts. The metal NCs memories have higher density of states

* Tel.: +886 3 2118800x5786; fax: +886 3 2118507. E-mail address: [email protected] (C.-S. Lai). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.01.027

around the Fermi level, which are more immune to the Fermi-level fluctuations caused by contamination [8,9]. In addition, with the use of metal NCs, it is easier to fabricate an asymmetric barrier height between a NC and silicon substrate for high speed operation without sacrificing the data retention. Among the metal NCs memories, tungsten nanocrystal (W-NC) memory has been considered as a promising candidate because of its suitable work function (around 4.55 eV) and high CMOS technology compatibility. The W-NC memories have been investigated in different structures and nucleation process in order to successfully obtain the effective and reasonable operation voltage [10,11]. In this paper, we use W/ Si dual-sputtering method to deposit WSix films and annealed in N2O and O2 ambient to form W-NCs. Low operation voltage and large memory window (6.5 V, at +9/9 V sweep) can be achieved by using the W-NCs memories optimized by different annealing process and blocking thickness.

2. Experimental The detailed process flow and schematic for fabricating a W-NCs memory are shown in Fig. 1. First, a 4 nm SiO2 layer was thermally grown on a cleaned p-type h100i Si wafer as the tunneling oxide. Subsequently, a 10 nm tungsten silicide was deposited by the dual-sputtered method with different W/Si sputtered power ratios of 20/10, 20/30 and 20/50 for DC and RF power, respectively in Argon ambient at 2E2 torr. Before WSi deposition, we pumped down the background of the sputter system to 9E6 torr to prevent the oxidation during dual-sputtering and then performed presputtering in Ar ambient to eliminate the oxide on the targets. After the WSix films had been deposited, the crystalline and bonding characteristics of the as-deposited WSix film were analyzed by

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J.-C. Wang et al. / Microelectronics Reliability 50 (2010) 639–642

Fig. 1. Process flow and schematic cross-sectional structure of W-NC memory with dual-sputtering and annealing optimization.

the X-ray diffraction pattern (XRD) and the X-ray photoelectron spectroscopy (XPS), respectively, as presented in Fig. 2. We can observe that clear WSix peaks of all the samples were found. Furthermore, the intensity of W–O bonds (W4f5/2 and W4f7/2) was declined with increasing Si sputtered ratio to prevent WOx formation [12]. Then, a SiO2 layer with thickness from 10 to 25 nm was fabricated on the wafer as a blocking oxide by PECVD and the annealing processes were applied to form W-NCs at 800, 850, 900, and 950 °C in furnace for 20 or 40 min in O2 and N2O ambient. Thereafter, a 300 nm Al metal layer was thermally evaporated as gate electrode. Table 1 summarized the detailed experimental splits for dualsputtered ratios, annealing conditions, and different blocking oxide

W/Si=20/50

Intensity (a.u.)

WSi2 <112>

W5Si3 <521>

W/Si=20/30 WSi2 <112>

W5Si3 <521>

W/Si=20/10 WSi2 <112>

40

W5Si3 <521>

W5Si3 W5Si3 <512> <422>

W5Si3 W5Si3 <512> <422>

W5Si3 W5Si3 <512> <422>

50

Table 1 Summary of experimental splits for dual-sputtered ratios, annealing conditions, and different blocking oxide thickness of W-NC memories. Experiments

Splits

W/Si sputtered power ratio 20W/10W 20W/30W 20W/50W

Annealing conditions Gas

Temperature

O2, N2O

800950 °C

Blocking oxide thickness 1025 nm

thickness. Besides, the capacitance–voltage (C–V) characteristics and flatband voltage shift were characterized by HP4285 LCR meter. 3. Results and discussion Fig. 3 shows the high-resolution transmission electron microscopy (HRTEM) images of 20/30 dual-sputtered power ratio W-NC memories with N2O and O2 annealing. It can be observed that more isolated NC dots of the N2O annealed sample are obtained as compared to the O2 annealed ones. Fig. 3c presents the EDX analysis of the crystallite for W-NCs with N2O annealing. The obvious peaks of W can also prove the formation of W-NCs. Fig. 4 demonstrates the C–V hysteresis of W-NC memories with the dual-sputtered power ratios of 20/10, 20/30, and 20/50. The hysteresis loops were first swept from 7 V to 7 V and then swept

60

(a)

EDS analysis of W-NCs

2 theta (degrees)

(c)

W-W/Si

W/Si=20/50 W-O

W4f7/2 W4f5/2

W4f

(c)

Intensity (a.u.)

o

TOA=90

2

W/Si=20/30 W-O W4f7/2

W4f7/2 W4f 5/2 W4f5/2

SiO2 W-NCs

W4f5/2W4f7/2 W/Si=20/10 W-O W4f7/2

W4f5/2

(b) 44 42 40 38 36 34 32 30 28 26

SiO2 SiO2

10 nm 5 nm

Binding energy (eV) Fig. 2. XRD spectrum and XPS analysis of the W-NC memories with W/Si dualsputtering ratio for 20/10, 20/30, and 20/50. Clear WSix peaks of all the samples were found.

Fig. 3. HRTEM images of 20/30 dual-sputtered power ratio W-NCs with (a) N2O and (b) O2 annealing; and (c) the EDX crystallite analysis for W-NCs with N2O annealing. It can be observed that more isolated NC dots of the N2O annealed sample are obtained as compared to that of the O2 annealed ones.

J.-C. Wang et al. / Microelectronics Reliability 50 (2010) 639–642

back. Of all the samples, a large hysteresis memory window of about 4.3 V for the sample with 20/30 dual-sputtered ratio was obtained. Less Si sputtered ratio cannot perform stable hysteresis curves owing to the WOx formation, as revealed in Fig. 2. On the contrary, it is hard to form W-NCs with too many Si elements when the Si sputtered power is as high as 50 W. Excess Si in WSix films might react with condensed W elements and form WSix again. Therefore, for the following researches we chose 20/30 dual-sputtered ratio as the optimization. To further improve the memory characteristics, nitrous oxide (N2O) annealing was applied to form the W-NCs. Fig. 5 presents the flat band voltage shift of 20/30 dual-sputtered power ratio W-NC memories with N2O and O2 annealing. We can observe that the W-NC memories with N2O annealing presents larger VFB shift than that with O2 annealing at annealing temperature of 850 °C. It can be attributed to the smaller binding energy of N–O bonds (397 eV) than that of O–O bonds (531.6 eV) to provide oxygen atoms for W-NCs formation. Moreover, the dependence of sweeping gate voltage on flat band voltage shift of W-NC memories with different blocking oxide thickness of 20/30 dual-sputtered power ratio W-NC memories was shown in Fig. 6. When the sweeping voltage is below 12 V,

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the sample with thinner blocking oxide exhibits larger flat band voltage shift. It is due to the large electric field induced more electron injection as shown in Fig. 6b. On the other hand, when operating at higher voltage (>12 V), the VFB shift of the W-NC memories with thinner blocking oxide decreases abruptly, which is resulted from the serious electron back tunneling (EBT) from the Al metal gate as revealed in Fig. 6c.

-7 V ⇒ 7 V ⇒ -7 V

1.0

C/Cox

0.8

W/Si

0.6

20/10

0.4

20/30

0.2

20/50

0.0

-6

-4

-2

0

2

4

6

Gate voltage (V) Fig. 4. The C–V hysteresis characteristics of W-NC memories with W/Si dualsputtering ratio for 20/10, 20/30, and 20/50 at ±7 V sweeping. A large hysteresis memory window of about 4.3 V for the sample with 20/30 dual-sputtered ratio was obtained.

8

o

N2O 850 C 40min o N2O 900 C 20min o N2O 900 C 40min o O2 850 C 40min o O2 900 C 20min o O2 900 C 40min

VFB shift(V)

7 6 5 4 3 2 1 1

2

3

4

5

6

7

8

9 10

Sweep voltage(V) Fig. 5. The VFB shift comparison of W-NC memories with 20/30 dual-sputtered ratio and different N2O and O2 annealing. W-NC memories with N2O annealing presents larger VFB shift than that with O2 annealing at annealing temperature of 850 °C.

Fig. 6. Dependence of blocking oxide thickness and the sweeping voltages for 20/30 dual-sputtered power ratio W-NC memory on (a) VFB shift and gate injection phenomenon at (b) low sweeping voltage (<7 V) and (c) high sweeping voltage (>13 V), respectively.

J.-C. Wang et al. / Microelectronics Reliability 50 (2010) 639–642

Memory window (V)

642

14 12 10 8 6 4 2

o

800 C o 850 C

o

900 C o 950 C

(a)

In O2 ambient (+9/-9 V sweeping)

14 o o 800 C 900 C 12 (b) o o 10 850 C 950 C 8 In N2O ambient (+9/-9 V sweeping) 6 4 2 0 10 15 20 25

Blocking oxide thickness (nm) Fig. 7. The memory window comparison of 20/30 dual-sputtered power ratio WNC memory at Vg = ±9 V of (a) O2 and (b) N2O annealing with different annealing temperature and blocking oxide thickness respectively. The N2O annealed samples can be avoided from the formation of WOx in the charge storage layer under thin blocking oxide.

Fig. 7 shows the memory window dependence on blocking oxide thickness of 20/30 dual-sputtered power ratio W-NC memories with O2 and N2O annealing under +9/9 V sweeping. With O2 annealing (Fig. 7a), the memory window increases with annealing temperature and is optimized at the blocking oxide thickness of 20 nm. Too thin and too thick blocking oxide will both result in the reduction of memory window, which are responsible for the formation of WOx in the charge storage layer and the less oxygen diffused through blocking oxide to form the W-NCs, respectively. On the other hand, with N2O annealing (Fig. 7b), the memory window increases with annealing temperature and decreases with blocking oxide thickness. The N2O annealed samples can be avoided from the formation of WOx in the charge storage layer under thin blocking oxide. From these figures, the N2O annealed samples can perform the memory window of 6.5 V with 10–15 nm blocking oxide while the O2 annealed samples have to increase the blocking oxide thickness to 15–20 nm. Therefore, the W-NC

memories with N2O annealing exhibit superior memory characteristics and scaling capability than that with O2 annealing and can be used for future NVMs application. 4. Conclusions The W-NC memories with different W/Si dual-sputtered method, annealing process, and blocking oxide thickness were studied and optimized. With W/Si dual-sputtered ratio of 20/30, blocking oxide thickness of 10–15 nm, and N2O annealing at 950 °C, the memory window for 6.5 V under +9 V/9 V sweeping can be obtained. The superior characteristics of W-NC memories are successfully demonstrated and can be applied in future NVMs. Acknowledgements The authors thank the National Science Council, ROC, for their financial support under Contract No. NSC98-2218-E-182-002-MY2. References [1] Hanafi HI, Tiwari S, Khan I. Fast and long retention-time nano-crystal memory. IEEE Trans Electron Dev 1996;43:1553–8. [2] Wang YQ, Gao DY, Hwang WS, Shen C, Zhang G. Fast erasing and highly reliable MONOS type memory with HfO2 high-k trapping layer and Si3N4/SiO2 tunneling stack. IEDM Tech Dig 2006:1–4. [3] She M, King TJ. Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance. IEEE Trans Electron Dev 2003;50:1934. [4] Wang X, Kwong DL. A novel high-k SONOS memory using TaN/Al2O3/Ta2O5/ HfO2/Si structure for fast speed and long retention operation. IEEE Trans Electron Dev 2006;53:78. [5] Li B, Liu J, Liu GF, Yarmoff JA. Ge/Si heteronanocrystal floating gate memory. Appl Phys Lett 2007;91:132107. [6] Lee J-J, Kwong DL. Metal nanocrystal memory with high-j tunneling barrier for improved data retention. IEEE Trans Electron Dev 2005;52:507. [7] Salvo BD, Ghibaudo G. Experimental and theoretical investigation of nanoCrystal and nitride-trap memory devices. IEEE Trans Electron Dev 2001;48:1789. [8] Pei Y, Nishijima M, Fukushima T, Tanaka T, Koyanagi M. Memory characteristics of self-assembled tungsten nanodots dispersed in silicon nitride. Appl Phys Lett 2008;93:113115. [9] Kim J-H, Yang JY, Lee JS, Hong JP. Memory characteristics of cobalt–silicide nanocrystals embedded in HfO2 gate oxide for nonvolatile nanocrystal flash devices. Appl Phys Lett 2008;92:013512. [10] Chang TC, Liu PT, Yan ST, Sze SM. Electron charging and discharging effects of tungsten nanocrystals embedded in silicon dioxide for low-voltage nonvolatile memory technology. Electrochem Solid-State Lett 2005;8:71–3. [11] Yoon J-K. J Alloy Compd 2006:591. [12] Beyers R. Thermodynamic considerations in refractory metal–silicon–oxygen systems. J Appl Phys 1984:147.