Characterization of MIS structures and PTFTs using TiOx deposited by spin-coating

Microelectronics Reliability 54 (2014) 893–898

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Characterization of MIS structures and PTFTs using TiOx deposited by spin-coating C. Meneses a, J.G. Sanchez a, M. Estrada a,⇑, A. Cerdeira a, J. Pallarés b, B. Iñiguez b, L.F. Marsal b a b

SEES, Depto. De Ingeniería Eléctrica, CINVESTAV-IPN, Av. IPN 2208, CP 07360 México DF, Mexico Departament dÉnginyeria Electronica Electrica i Automatica, Universitat Rovira i Virgili, Avda. Paisos Catalans 26, 43007 Tarragona, Spain

a r t i c l e

i n f o

Article history: Received 11 October 2013 Received in revised form 20 January 2014 Accepted 21 January 2014 Available online 11 February 2014

a b s t r a c t This paper presents a method to deposit titanium oxide (TiOx) films from a sol containing IV titanium isopropoxide Ti[OCH(CH3)2]4, 2-methoxyethanol, CH3OCH2CH2OH and ethanolamine H2NCH2CH2OH, in order to obtain layers with thickness above 220 nm with the required characteristics to be used in Metal–Insulator–Semiconductor, MIS, structures and polymeric thin film transistors, PTFTs. The effect of using different component ratios is described. The dielectric constant was in the order of 12, the critical electric field was 5  105 V/cm and the density of states at the interface was less than 1  1011 cm2. The analysis of MIS structures prepared with these TiOx layers shows that they are suitable for using in PTFTs. The fabrication of independent bottom gate PTFTs with poly(3-hexylthiophene), P3HT, on top of the TiOx layer is described, obtaining a major reduction in the operation voltage range from 30 V to 4 V, while maintaining the typical mobility for P3HT PTFTs. Ó 2014 Elsevier Ltd. All rights reserved.

1. Introduction The use of high dielectric constant (high-k) materials can provide significant advantages in thin film transistor, TFTs, performance. For low cost organic and polymeric TFTs, OTFTs and PTFTs, the deposition method of this high-k dielectric should be compatible with low cost technology and the specific characteristics of the organic materials, while maintaining the required electric and interface characteristics necessary for operationally stable PTFTs. Several low temperature deposition methods such as anodic oxidation of titanium [1], electron beam evaporation [2], reactive sputtering [3], spray pyrolysis [4] and sol–gel [5–8], have been reported to prepare TiOx layers. Among them, the sol–gel method is low cost and can be used for spin-coating deposition technique. However, it presents several problems to overcome in order to obtain good quality and relatively thick layers, around or greater than 200 nm, which can be used in Metal–Insulator–Semiconductor (MIS) structures and TFTs. Among these problems are obtaining layers with higher critical electric field and avoid layer cracking, which usually appears as the thickness increases. Most transition-metal alkoxides hydrolyze on contact with water, resulting in a metal hydroxide precipitate. Controlling hydroxide precipitation is essential to obtain high-quality ⇑ Corresponding author. Tel.: +52 55 57473786; fax: +52 55 57473978. E-mail address: [email protected] (M. Estrada). http://dx.doi.org/10.1016/j.microrel.2014.01.020 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.

products. Different chelating agents such as glycol [7] and organic acids [5–8], which occupy some of the coordination sites of the alkoxide, have been used to lower the rate and extent of hydrolysis. The effect of using different solvents in the sol preparation, on the hydrolysis and condensation reactions of the alkali can be found in [9]. Studies on the effect of solvents and acids to reduce or avoid layer cracking with the increase in thickness were reported in [10,11]. In this work, we present and discuss a method to deposit titanium oxide (TiOx) from a sol, in order to increase the thickness of the deposited layer, avoid cracking and produce layers with the required characteristics to be used in MIS structures, which electrical characterization is also presented. Afterwards, PTFTs using these TiOx layers as gate dielectric were fabricated and characterized. 2. Experimental procedure 2.1. TiOx layer preparation As already mentioned, the deposition of TiOx layers by spincoating represents a useful solution for low cost OTFTs. In this study we analyzed four different methods of sol preparation, see Table 1. Method 1 of sol preparation used as reactants IV titanium isopropoxide Ti[OCH(CH3)2]4, >99.999%, 2-methoxyethanol, CH3OCH2CH2OH, >99.9%: and ethanolamine, H2NCH2CH2OH, >99%, in a ratio of 1:5:0.5 mL, all from Sigma Aldrich.

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Table 1 Different methods of sol preparation. Method

Components

Component ratio

1

(1) IV titanium isopropoxide (2) 2-Methoxyethanol (3) Ethanolamine

1:5:0.5 mL

2

(1) IV titanium isopropoxide (2) 2-Methoxyethanol (3) Ethanolamine

1:4:0.36 mL

3

(1) IV titanium isopropoxide (2) Valeric acid (3) H2O

1:2.4:0.1 mL.

4

(1) (2) (3) (4)

1:2.4:4:0.5 mL

IV titanium isopropoxide Valeric acid 2-Methoxyethanol Ethanolamine

Components were mixed in a hermetically sealed vial inside a glove box and stirred during 3 h in a silicon oil bath at 100 °C. All reactions were carried out in closed recipients, isolated from atmosphere. Some samples were left for 1 h in ambient conditions to hydrolyze the TiOx layer, after which they were annealed in N2 atmosphere at 60 °C during 30 min to evaporate the remaining solvents and provide film solidification. TiOx layers were deposited by spin-coating at 1000–2000 rpm during 30 s. With this sol, the maximum thickness obtained was 220 nm [12]. To further increase the thickness of the deposited layer, we added an evaporation step to the sol preparation, in which the sol was left at 150 °C stirring continuously during 1 h to evaporate the non-reacting reagents, as well as residual products. The sol obtained was more viscous and a layer thickness of more than 400 nm could be obtained. In Method 2, the rate of the sol reagents was changed by increasing the IV titanium isopropoxide to the rate of 1:4:0.36, obtaining a maximum layer thickness of 320 nm. Including a final evaporation step at 150 °C, the maximum layer thickness was increased to 490 nm. Thinner TiOx layers can be obtained diluting the sol in ethanol at different ratios. As mentioned, layer cracking is a frequent problem present in TiOx layers [10]. In our conditions, cracking was observed for film thickness greater than 250 nm if deposited on Si, or greater than 200 nm if deposited on Au. The appearance of layer cracking at lower film thickness when deposited on Au is expected, due to the higher surface tension of Au. The density and depth of the cracks increase as the layer thickness increases. It was also observed, that deposited layers can be damaged if immersed in some organic solvents or water. For example, films deposited from the sol obtained by the second method, dissolved more quickly in water than those prepared from a sol obtained

using the first method. This is an important issue to take into account, since water is required for rinsing or as part of etchants during the photolithographic process, necessary to fabricate TFTs. To try to overcome layer cracking, we used Method 3 reported in [11], where IV titanium isopropoxide was first mixed with valeric acid, after which water was added to obtain a total ratio of 1:2.4:0.1 mL. Using the previously mentioned procedure, no layer cracking was observed for a thickness up to 320 nm, but it was not possible to obtain acceptable uniformity in the deposited layers. The presence of particles was observed in the layer, in spite of 0.2 lm filtering during the spin-coating process. The index of refraction was smaller, n = 1.6, compared with the value of 1.68 obtained for Methods 1 and 2. Finally, in Method 4, IV titanium isopropoxide was first mixed with valeric acid with the same reagent ratio as reported in [11], but without adding water. The reagents were put in a hermetically sealed vial inside glove box and stirred during 1 h at ambient temperature, after which 2-methoxyethanol and ethanolamine were added to form a sol with the total component ratio of 1:2.4:4:0.5 mL. All the components were mixed in a hermetically sealed vial inside a glove box and stirred during 3 h in a silicon oil bath at 100 °C to provide reactions to occur isolated from atmosphere. With a spinning rate of 7000 rpm layers of 225 nm were obtained, but again, they were not uniform as those obtained following the method reported in [11]. The maximum thickness obtained was smaller than in the previous case, which can be explained by the lack of water to enhance hydrolysis and no cracking was observed. Again, the refraction index was smaller, n = 1.6, probably due the effect of the acid. For the reasons mentioned, we decided not to use the methods containing valeric acid in the device fabrication. Fig. 1 shows photos of (a) a uniform layer, (b) a cracked layer, (c) a non-uniform layer. From the above results it is seen that using Method 1, good quality and non-cracked TiOx layers of up to 230 nm can be deposited by spin-coating, which seem suitable for PTFTs fabrication.

3. Fabrication and characterization of MIS structures MIS structures were prepared using TiOx as the insulator layer, which was deposited from the sol prepared according to the first method. The TiOx layer was deposited on Si substrates and Au was used as metal gate. Both p and n-type silicon with different resistivity were used as the semiconductor substrate. The CV curves were measured at 1 kHz and 1 MHz, using the Agilent E4980A Precision LCR Meter. Curves 1 and 2 in Fig. 2 correspond to CV measurements of non-hydrolyzed and hydrolyzed samples, respectively. Both MIS

Fig. 1. TiOx film: (a) good quality and uniform; (b) cracking of the layer, which appears as the thickness increases above 250 nm and (c) non-uniform film obtained after adding valeric acid, trying to prevent cracking.

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1.0 1.0

(2) hydrolyzed (ki=12)

Measured on day 1 Crel sweep from -1 to 1 V Crel sweep from 1 to -1 V

C'min/Ci

0.8

Crel

Crel=C/Ci

0.8

0.6

Xi=189 nm Type N substrate NB=2.5x1015 cm-3 fmeasurement=1 MHz

(1) non-hydrolyzed (ki=55) 0.4

Xi=156 nm Type P substrate NB=2.5x1018 cm-3 fmeasurement=1MHz

0.6

0.2

C'min/Ci

Measured after 15 days Crel sweep from -1 to 1 V Crel sweep from 1 to -1 V

0.4 -5

0

0.0 -1.0

5

Voltage (V)

structures were measured at a frequency of 1 MHz, varying the gate voltage from negative to positive values. P-type Si was used as substrate. In these curves, it is seen that the value of the ratio of the minimum capacitance at high frequency to the capacitance

C 0min 1 ¼ Ci 1 þ ki kWs Xmax i

C 0min Ci

is much smaller in the non-hydrolyzed

can be calculated as [13]:

ð1Þ

where Wmax is the maximum length of the depleted region in the Si substrate, which is equal to [13]:

W max ¼

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ks eo ðwinv Þ qN B

ð2Þ

and eo is the vacuum permittivity, q is the electron charge, ks is the dielectric constant of the silicon substrate equal to 11.7 and ki is the dielectric constant of the TiOx to be calculated. Xi is the thickness of the dielectric layer, NB is the doping concentration of the Si used as semiconductor substrate and winv ¼ 2wF is the surface potential corresponding to strong inversion, where wF is the Fermi level corresponding to the silicon doping NB. The capacitance of the insulator layer Ci, which is equal to:

Ci ¼

eo ki Xi

0.5

1.0

Fig. 3. Capacitance–voltage curves of MIS structures with hydrolyzed TiOx layers as dielectric, showing the reduction of the hysteresis after several days of fabricated.

positive to negative voltages, can be due to positive free charges or oriented dipoles in the dielectric layer, while the deformation is attributed to interface traps [15]. In measurements carried out 15 days later, hysteresis as well as the deformation disappeared, which can be attributed to further saturation of dangling bonds with the consequent reduction of the density of interface traps and charge displacement. Fig. 4 shows the effect of the measurement frequency on CV curves. At 1 kHz, it is seen that CV curves shifted 0.15 V to more negative voltages. This is due to more interface traps that can follow the measurement signal, increasing the density of charged interface states. The flat band voltage was obtained from the CV curves at 1 MHz [13] and it was typically around zero volts, which is good in order to obtain low threshold voltages. The density of charged interface states was calculated as [13]:

Nss ¼

V FB qC i

ð4Þ

The density of interface states was calculated using (4), obtaining values in the order of 1011 cm2 or below.

1.0

Measurement from negative to positive voltage after 1 min left at -1V

ð3Þ

is used to determine the value of ki. Silicon was used as the semiconductor material in the MIS structures to eliminate possible influence of others not so well studied materials, as for example an organic semiconductor, in the behavior of the analyzed MIS structure. Without hydrolyzation, calculated ki was greater than 50, but it varied from sample to sample. For hydrolyzed samples, ki reduced typically to values below 15, but in a repeatedly way on different samples, indicating that the introduction of water stabilizes the molecule at the price of reducing ki. Nevertheless, ki is still almost 4 times greater than for other dielectrics used in PTFTs [14]. After hydrolyzation of the TiOx layers, the stability of the CV curves increases during the first days. Fig. 3 shows that the hysteresis observed in the CV curves of hydrolyzed samples measured right after fabrication, practically disappears after 15 days, due to further hydrolyzation over time. The parallel shift observed in the CV curve measured right after fabrication, when swept from

0.8

Crel

sample. The value of

C 0min Ci

0.0

Voltage (V)

Fig. 2. Capacitance–voltage curves of MIS structures, showing the effect of hydrolyzation on the TiOx layers.

of the insulator layer,

-0.5

ΔV shift

0.6

0.4

Measurement frequency:

0.2

1 MHz 1 kHz 0.0 -1.0

-0.5

0.0

0.5

1.0

Voltage (V) Fig. 4. Capacitance–voltage curves of MIS structures with TiOx as dielectric, showing that the curves shift to more negative voltages as the measurement frequency is reduced.

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C. Meneses et al. / Microelectronics Reliability 54 (2014) 893–898

The frequency dependence of the dielectric constant of TiOx was also analyzed. Previously [16], it was shown that the ki of polymeric materials as Poly(methyl-methacrylate) (PMMA), in the frequency range below 1 MHz, varies with frequency as described by the empirical expression given by Cole–Cole [17]:

ki ¼ kiH þ

ðkio  kiH Þ ð1 þ jxsÞ

P

ð5Þ

;

where kio is the dielectric constant measured at very low frequency and kiH is the relative permittivity measured at very high frequency, s is a parameter associated to the relaxation time and P is an adjusting parameter between 0 and 1. In the case of TiOx, a similar frequency dependence of the ki was found. Fig. 5 shows the variation of ki in the range of 400 Hz–1 MHz for structures using TiOx and PMMA as dielectric, It is seen that the 18

3.2

kio kiH

16

τ

P

PMMA 3.22 2.69

TiOx 17.2 10

Cole-Cole law ki TiOx

3.1

ki PMMA

5x10-4 2.1x10-4 0.3 0.6

ki TiOx

2.9 12 2.8 10 2.7 8 103

104

105

106

Frequency (Hz) Fig. 5. Frequency dependence of TiOx dielectric constant, ki.

ki PMMA

3.0

14

variation of the ki in TiOx tends to stabilize at lower frequencies than in PMMA, at around 100 kHz. Deposited TiOx layers were characterized by their insulating properties. The measured critical electric field in deposited TiOx films was higher than 5  105 V/cm, while a current density of less than 104 A/cm2 was typical for films with thickness above 180 nm. 4. PTFTs with TiOx as gate dielectric TiOx deposited from the above presented sol method was used as dielectric layer in the fabrication of PTFTs with poly(3-hexylthiophene), P3HT as semiconductor. The best TiOx characteristics to be used as the dielectric layer for TFTs were obtained with the sol prepared by the first method, with or without evaporation. Bottom gate PTFTs were fabricated as indicated in Fig. 6. The first step was a deposition of 50 nm of Au, followed by the photolithography of the gate contact, after which a TiOx layer was deposited using the first method with or without the evaporation step. A second photolithography to open holes through the TiOx layer was done by RIE in CF4, followed by a second deposition of Au layer. A third photolithography defines the regions of drain (D) and source (S). The next step is the deposition of P3HT as active layer, followed by PMMA deposition for surface passivation and a third deposition of Au layer, on which a fourth photolithography is used to open holes throughout these two layers in order to reach the D, gate (G) and S contacts, using plasma etch in O2. A final Au deposition is followed by a photolithography that defines the contacts located on the upper surface of the device, connecting the upper D and S contact and the bottom G with the external surface contacts of the device. Fig. 6 shows the cross section of the bottom gate PTFT and its upper view. Fig. 7a and b shows the output and transfer characteristics of fabricated PTFT, where a significant reduction of the threshold

Fig. 6. (a) Upper view of the TFT layout; (b) cross section along A1 and (c) cross section along A2.

C. Meneses et al. / Microelectronics Reliability 54 (2014) 893–898

897

5. Conclusions L=30 μm W=300 μm Xi=438 nm de TiOx Xs=60 nm de P3HT

2.0x10-8

1.5x10-8

-IDS [A]

VGS=-4 V

VGS=-3 V

1.0x10-8

VGS=-2 V VGS=-1 V

5.0x10-9

0.0 0

1

2

3

4

-VDS [V]

(a) 6x10-9 5x10-9

Tranfer characteristics VDS=-0.5 V

4x10-9

|-IDS| [A]

3x10-9

Acknowledgements This work was supported by CONACYT Project 127978 in Mexico, the Spanish Ministry of Economy and competitiveness (MINECO) under Grant No. TEC2012-34397, Catalan authority under Project 2009 SGR 549. We also thank Dr. Mariana Stepanova from URV, for her support in the fabrication of the masks, as well as CONACYT project ICyTDF 323/2010 and Dr. Máximo López, head of the Department of Physics at CINVESTAV, for photolithographic facilities.

2x10-9

10-9

0

1

2

3

4

-VGS [V]

(b) Fig. 7. (a) Output characteristics and (b) transfer characteristics of TiOx TFT, working in the 0 to 4 V range. X-axis shows the values of VDS and VGS, respectively and y-axis corresponds to the values of IDS.

voltage and of the operating voltage range is observed, compared to P3HT PTFTs using PMMA as dielectric. When using PMMA, the operating range was 30 V, while with TiOx, it reduced to 4 V due to the increased ki. In Table 2, the values of the threshold voltage, VT, mobility, lFET, and the parameter for the voltage dependence of the mobility in TFTs, c, are shown. The main issues to obtain PTFTs with good electrical characteristics were to use TiOx layer thickness of 200 nm or above, avoiding layer cracking, and to develop a fabrication process compatible with photolithographic techniques, in order to access all electrodes from the upper surface of the device, as shown in Fig. 6.

Table 2 Parameters of the fabricated PTFTs. Parameter

We show different approaches of preparing a sol containing IV titanium isopropoxide, 2-methoxyethanol and ethanolamine to deposit TiOx layers by spin-coating, indicating that best results with respect to film quality and thickness are obtained with a component ratio of 1:5:0.5 mL, after which an evaporation step of the sol can be added, if necessary to increase the film thickness. The characterization of MIS structures using TiOx as dielectric, deposited from this sol, showed low density of charged interface states, with typical values of flat band voltage around zero volts. The Cole–Cole empirical equation successfully describes the frequency dependence of the TiOx dielectric constant, which is similar to the observed for other dielectrics used in PTFTs, as the polymer PMMA. A fabrication process for bottom gate PTFTs with P3HT on top of a previously deposited by spin-coating TiOx layer is described, for which a major reduction from 30 V to 4 V in the operation voltage range is achieved, maintaining the typical mobility and operational stability for P3HT PTFTs. However, in spite of the obtained results, the use of these TiOx layers in TFTs, present several problems that should be solved in order to improve device characteristics, which are, a relatively low critical electric field and high leakage current density, as well as the difficulty in increasing layer thickness without cracking.

VT (V)

lFET0 (cm2/V s)

c

lFET at VGS = 4 V (cm2/V s)

0.53

9.5  103

0.14

1.1  102

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