Characterization of Si-PIN radiation detector with photon counting mode CMOS readout front-end

Characterization of Si-PIN radiation detector with photon counting mode CMOS readout front-end

ARTICLE IN PRESS Nuclear Instruments and Methods in Physics Research A 576 (2007) 47–51 www.elsevier.com/locate/nima Characterization of Si-PIN radi...

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ARTICLE IN PRESS

Nuclear Instruments and Methods in Physics Research A 576 (2007) 47–51 www.elsevier.com/locate/nima

Characterization of Si-PIN radiation detector with photon counting mode CMOS readout front-end Sungchae Jeona,c, Young Huha,, Seongoh Jina, Jongduk Parka, Jae Yun Leea, Bo Sun Kangb, Gyuseong Choc a

Electro-Bio Sensor Research Group, 1271-11 Sa-1 dong, Sangrok-gu, Ansan, Gyeonggi-do, Republic of Korea b NFRC, Operation Research, 52 yeoeun-dong, Yusong-gu, Taejeon 305-333, Republic of Korea c KAIST, 373-1 Kusong-dong, Yusong-gu, Taejon 305-701, Republic of Korea Available online 4 February 2007

Abstract An X-ray pixel detector with photon counting technique for digital X-ray imaging was designed and developed. Si detector was fabricated starting from 5 in., FZ-refined, 620 mm-thick, /1 1 1S oriented, n-typed silicon wafer with high resistivity of 6000–12,000 O cm. Readout front-end, which consists of the preamplifier, comparator, and bias circuits including the band-gap reference circuits, was designed and fabricated using 0.25 mm-triple-well CMOS standard process. In detector, the several types of guard-ring structures were tested. The biased p-type guard ring showed more reasonable results in the leakage current and breakdown voltage. The experimental results for the readout chip prove that its functionality is correctly operated up to 100 mV, 2.5 M events/s. In radiation experiment under irradiation of 60Co at dose rate 10 krad/h the measurement indicate that the band gap reference generator (BGR) circuits work up to 240 krad and the maximum variation of output voltage is 0.4% (peak-to-peak) of operational voltage at the range of 0–240 krad. It cannot lead to any critical problem for use in its operation. r 2007 Elsevier B.V. All rights reserved. PACS: 07.50.Ek; 07.85.Fv; 29.40.Wk Keywords: Single photon counting; Si detector; CSA; Preamplifier; Comparator; BGR

1. Introduction Single Photon Counting (SPC) imager has been under investigation to overcome the limitations of integration mode detector and offered an attractive solution for medical X-ray imaging applications [1,2]. In this way the imaging system has many advantages, such as a good linearity in the response function, less dose, a good image contrast, and low noise immunity. In our hybrid system the SPC imager consists of two core parts. One is silicon based pixel detector which converts the absorbed X-ray into a charge signal. Silicon is the best known and used in the detector material. The other is the readout electronics operating in photon counting mode, which consist of the Corresponding author. Tel.: +81 31 500 4810, fax: +81 31 500 4820.

E-mail address: [email protected] (Y. Huh). 0168-9002/$ - see front matter r 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2007.01.118

analog and simple digital functional blocks. These functions are usually realized by CMOS technology because of its advantage of the mature technology, as functional integrity and reliability [3,4]. In this paper, we concentrate on the design for the selected topologies that were employed in photon counting imager and the evaluation of band gap reference generator (BGR) for radiation exposure.

2. Detector description The SPC imager has been designed and manufactured for use in X-ray imaging. It consists of the sensor and readout front-end chip, which consists of biasing circuits including a BGR, charge sensitive amplifier (CSA), and discriminator.

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2.1. Sensor

independent of detector capacitance for gain and low noise for X-ray application [6]. Its negative input node is connected to feed back capacitor and PMOS resistor in parallel. Every transistor is operated in saturation region to get the high differential mode gain and the current mirror circuit is adopted to get wider output range. The second stage of the readout circuit is the discriminator that is placed at the end of preamplifier. The block diagram of discriminator is shown in Fig. 2. This stage consists of a differential comparator and two consecutive CMOS inverters in order to improve the shape of the output pulses. The threshold of the discriminator is supplied by threshold voltage supplier, which consists of the voltage divider, voltage buffer, and resistor trimmer. The threshold level is precisely controlled by a four-bit control word, which divides into 16 steps below the nominal value. The readout front-end chip also includes the band gap reference circuit, which is used for all kinds of integrated circuits from biasing circuits to precise comparator to provide the voltage and current references with low sensitivity to the temperature and supply voltage variation. A schematic of the BGR is shown in Fig. 3. The BGR was implemented using differential amplifier with low-VT NMOS transistor, self-bias circuit, and cascode current mirror for wide-swing output. With different transistor size ratio of current mirror the emitter’s area ratio of bipolar 1 transistors (Q1, Q2) was reduced by 10 .

High-resistance silicon detector for use in direct conversion of X-rays has been designed and fabricated. Designed test chips have contained PIN-type detectors of different guard-ring structures and different gettering techniques [5] to optimize the device and process. The silicon wafers used in this work were 5-in. diameter, FZ-refined, 620-mm-thick, /1 1 1S oriented, n-typed silicon substrates with high resistivity of 6–12 kO cm. The pixel had a 100 mm  100 mm size and was separated by guard ring. Three different guard-ring types, such as n-type, p-type floating, and biased p-type, were implemented on the frontside. On the backside of the wafers, two gettering technologies, namely phosphorus ion implantation and POCl3 diffusion, were utilized to compare the performance of detector fabrication in reducing the leakage current. 2.2. Photon counting mode readout front-end The readout front-end was designed and realized in a standard 0.25 mm-triple-well CMOS technology, this provides high integration capability for components needed to implement the counting mode operation in a small pixel. The readout front-end was designed to reduce the power consumption by using single power supply in which the voltage was set at the standard for this technology, i.e. 2.5 V. In the first stage, preamplifier was implemented with charge sensitive amplifier, which was designed by using folded cascode CMOS operational amplifier shown in Fig. 1. This structure has many advantages, such as

3. Results In this study, Si detector and fabricated readout chip were evaluated separately. With help of a HP-4145

VB1

MP2

MP1 VB2 VIN MN1

MN2

MN4

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VB MP3

MN3

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MN5

MN6

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Rf

Fig. 1. Schematic of the charge sensitive amplifier.

MN7

Vout

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MP1

R trimmer VTHR MP2

-

SEL<0:3>

Comp_OUT I + VIN

Fig. 2. Block diagram of the discriminator.

Va

Low_VT Low_VT

2wp

wp

2wp

wp

2I

I Vh

2wp

In

+ ΔVEB R1

Q1 1

2wp Vref 2I Ih R3

R2 2R1 Q2

N

Fig. 3. Schematic of the band gap reference generator.

semiconductor analyzer and oscilloscope, the measurement of their performance was performed.

3.1. Leakage current of photodiode The effectiveness of guard ring and gettering technologies in detector fabrication aimed at leakage current has been investigated. Fig. 4 shows the reverse leakage current of fabricated detectors with different guard ring in different gettering technologies.

In n-type guard ring the results show the most efficient reduction in leakage current and, in contrast, the degradation of the breakdown voltage. Since n-type guard ring can prevent lateral depletion spreading with increasing reverse voltage, the contribution of the surface current, which is dominant noise source in photodiode, is reduced. For p-type guard ring biased to ground, the results show the efficient reduction of leakage current, which is because the surface leakage current flows out through the electrical loop, without degradation of breakdown voltage. Figs. 4(a) and (b) indicate that the POCl3 diffusion leads to an

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a

a 600.on 500.on

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evident reduction of leakage current compared with the implantation.

Fig. 5. Output response of the BGR circuit after

3.2. Radiation response of BGR

Stop

The BGR cause a serious degradation of device performance due to radiation effects, such as change of the threshold voltage of a MOS transistor and the gain of a BJT [7,8]. A circuit of the band gap reference circuit has been tested to validate the function for radiation environment. The layout of the circuits did not use radiation tolerant technique, such as enclosed layout transistors (ELTs), but only use guard rings in NMOS. In radiation experiment four different chips biased in common operation mode were tested. All devices were irradiated with a 60Co radiation source at a dose rate of 10 krad/h at a room temperature. The measurement shows two different results shown in Fig. 5. In the first one, a required minimum operational voltage decreases with increasing radiation dose to 30 krad and from then increases, illustrated in Fig. 5(a). The other case is that a required minimum operational voltage

60

Co irradiation.

TΤ Τ T Ch1 Freq 2.495MHz Low signal amplidtude

11

2

Ch1

100mν Ch2 1.00ν M 200ns A Ch1 ∫ 76.0mν Τ 0.00000s Fig. 6. Output of the readout front-end chip.

increases with increasing radiation dose and decreases after 40 krad, as shown in Fig. 5(b). In both cases, the results show that they can work up to 240 krad and not

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lead to any critical problem in nominal operation voltage (2.5 V). The maximum variation of output voltage for a 2.5 V is 0.4% (peak-to-peak) at the range of 0–240 krad.

3.3. Readout front-end In simulation study the input to the front-end is a rectangular formed voltage applied over an injection capacitance of 0.1 pF. Input charge is 2.65 fc, which corresponds to a mono-energetic photon of 60 keV. The simulated results show that output swing voltage (DV) of CSA is 76.3 mV and it is larger than that of single branch folded cascode operational amplifier, 45.1 mV. The peaking time is 7 ns and response time is about 139 ns. Fig. 6 shows the output pulses produced from the readout chip. The input signal is 100 mV amplitude and 2.5 M events/s, which is hardware limitation of our experiment. It is clear that the fabricated chip has proved its functionality.

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4. Conclusions High-purity Si detector and CMOS front-end for counting mode operation were designed and fabricated. In Si detector, the p-type guard ring biased to ground showed more reasonable results for leakage current and breakdown voltage. The experimental results for the readout chip proved that the functionality was correctly operated. In radiation test of BGR the circuits worked up to 240 krad, which could not lead to any degradation of output. References [1] [2] [3] [4] [5] [6] [7]

X. Llopart, et al., IEEE Trans. Nucl. Sci. NS-49 (5) (2002) 2279. M. Lo¨cker, et al., IEEE Trans. Nucl. Sci. NS-51 (4) (2004) 1717. E.F. Tsakas, et al., Nucl. Instr. and Meth. A 469 (2001) 106. E. Zervakis, et al., IEEE Trans. Nucl. Sci. NS-51 (4) (2004) 1840. G.F. Dalla Betta, et al., Nucl. Instr. and Meth. A 395 (1997) 344. P. O’Conner, et al., IEEE Trans. Nucl. Sci. NS-44 (3) (1997) 318. C.M. Dozier, et al., IEEE. Trans. Nucl. Sci. NS-34 (6, Pt. 1) (1987) 1535. [8] A.H. Jonston, et al., IEEE Trans. Nucl. Sci. NS-43 (6, Pt. 1) (1996) 3049.