- Email: [email protected]
Si with a novel scanning capacitance microscope combined with an atomic force microscope
..‘:.:.‘.‘.:.:.~:.:.:::x:.~:::::~.:.:.:~.~,:,:,~.:,:,:.:.:,~.:..:.*
..“...~.~ ~,,:::: ;,;i
“:“;‘“.‘~‘:.~:~.:.:..:.?:a ...........................~,.:.:,~,:~.:,:,:,; ‘“‘w::::(:,~~ .......... g:~;.~,~..y i.. ... L
. .. .
w
applied
surface science EISEVIER
Applied SurfaceScience 117/l 18(1997) 166-170
Characterization of SiO,/Si with a novel scanning capacitance microscope combined with an atomic force microscope Hideto Tomiye a,*, Hiroshi Kawami b~l,Takafumi Yao a,2 a Institutefor Materials Research, Tohoku Uniuersiry, Aoba-ku, Sendai 980-77, Japan b Nissin Electric Co., Ltd., Ukyo-ku, Kyoto 615, Japan
Abstract We have investigated the local electrical properties of an SiO,/Si structure using a novel scanning capacitance microscope (S&M) combined with an atomic force microscope (AFM). The electrical properties of the SiO,/Si system is investigated using the microscope. We investigated a lateral p-n junction is formed by ion implantation of P into a lightly B-doped Si wafer followed by thermal oxidation. It is demonstrated that the local impurity concentration profiling is achieved by the C-V characteristics. In the next experiment we have injected charge into SiO, and investigated the nature of charge storage at the SiOJSi interface. Erasing of the written-in pattern was possible by applying a positive pulse. This paper will report on the development of a novel SCaM and its application to the characterization of SiO,/Si and fabrication of a charge storage device. Keywords: Scanning capacitance microscope; Atomic force microscope; Scanning tunneling microscope; SiO,/Si;
1. Introduction Capacitance measurement is one of the most important characterization techniques for semiconductors and semiconductor devices, since it provide indispensable information on electrical properties of semiconductors, including impurity concentration, flat band voltage, deep levels, interface states, built-in potential, and so on [l]. Hence there have been various characterization techniques based on capacitance measurements. However, most of these measurements could elucidate only macro-scale electrical
* Corresponding author. _Tel.: + 81-022-2152074; fax: + 81022-2152073; e-mail: [email protected]. ’ Fax: + 81-0720-595770.
’ E-mail: [email protected].
Trapped charge
properties with lateral resolution much poorer than 100 pm. In view of the recent developments of semiconductor devices towards the nano-scale regime, there is an increasing demand for nano-scale characterization of electrical properties of semiconductors. Although the scanning capacitance microscopy (S&M) should basically elucidate local electrical properties on nanometer scale, there have been only few reports on the development of SCaMs and their application to local electrical characterization of semiconductors [2,3]. However, most of those SCaMs give capacitance due to the topographic change of the surface in addition to that of the specimen itself with a poor lateral resolution of 200 n&2 ,um [4,5]. Recently an AFM was modified to construct a SCaM by attaching a capacitance sensor [6]. However, dC/dV was measured rather than capacitance, be-
0169-4332/97/$17.00 Copyright 0 1997 Elsevier Science B.V. All rights reserved. PII SO169-4332(97)00028-7
H. Tomiye et al/Applied
Surface Science I17/
cause of the stray capacitance between the tip and the surface. In a previous paper, we have demonstrated the development of a combined SCaM/STM/AFM system which enables measurements of surface topography, current-voltage, and capacitance-voltage characteristics [7]. Since the SCaM was made by attaching a capacitance sensor to an AFM, the spatial resolution should be sacrificed to enhance the specimen capacitance compared to the stray capacitance. As a result, the lateral resolution was as large as 1 ,um. We have overcome these problems by developing a novel SCaM with lateral resolution less than 100 nm. This paper will report on the development of a novel SCaM and its application to the characterization of SiO,/Si and fabrication of a charge storage device.
2. Scanning capacitance
microscope
The most crucial element of a SCaM is cantilever, since spatial resolution and sensitivity are essentially determined by the cantilever. As mentioned above, stray capacitance associated with a conductive micro cantilever is so large that the sample capacitance can only be detected at an expense of spatial resolution, that is, increase in contact area. It should be stressed that a reduction in stray capacitance should result in both more sensitive detection of the sample capacitance and improved lateral resolution. In order to solve the problem, we have invented a
118 (1997) 166-170
167
new type cantilever made of tungsten wire which was sharpened by electrochemical etching. The cantilever was formed by bending the tip close to the tip end. Stray capacitance for this tip is estimated to be 0.01 pF which is orders of magnitudes smaller than that for a micro cantilever. We have developed a new detection technique for the deflection of the W wire cantilever, in which the cantilever is projected onto a position sensitive diode by a laser beam from the side. The vertical and lateral resolutions for an AFM mode operation were 50 nm and 100 nm, respectively, while the spatial resolution for a SCaM mode was 100 nm. The combined SCaM/AFM/STM was constructed by attaching a capacitance sensor and a current-voltage converter to an AFM with a W wire cantilever as schematically shown in Fig. 1. We can measure the local variations of capacitance, dC/dV and current at a fixed voltage as well as surface roughness for up to an area of 20 pm X 20 pm.
3. Lateral p-n junctions We investigated lateral p-n junctions formed by the following procedures: a line-and-space pattern was formed by ion implantation on a p-type B-doped Si wafer (NA w lOI cme3), where the widths of the line and space were 2 pm and 4 pm, respectively; P+ ion was implanted into the Si wafer at 50 kV to a dose of lOI4 cm- *, followed by annealing at 950°C
beam deflectoin
computer Fig. 1. Schematic of the combined SCaM/AFM/STM in which a new detection technique for the deflection TheW wire cantilever is projected onto a position sensitive diode by a laser beam from the side.
of the cantilever
is invented.
H. Tomiye et al./Applied
168
-5.0
-2.5
0
2.5
Surface Science 117/118
I
5.0
Sample Bias Voltage [V] Fig. 2. (a) SCaM image, (b) C-V characteristics. The SCaM image (10 ymX 10 pm) was obtained at a sample bias voltage of 0 V. Point 1 is located in the bright area corresponding to higher capacitance, while point 2 is located in the lower-capacitance area.
for 30 min in H,. A thermal oxide layer of 10 nm thick was formed at 1000°C for 15 min. Fig. 2 (a) shows a SCaM image at 0 V. The detected capacitance (C) is a series combination of the capacitance of the SiO, layer (C,,) and that of a depletion layer in the Si substrate (Csi) formed just below the cantilever: l/C = l/C,, + l/Csi. Since C,,, is constant, the SCaM image reflects the variation of the capacitance of the depletion layer at 0 V. Since the Csi value should decrease with decrease in impurity concentration, the bright region corresponds to the implanted region, while the dark one to the un-implanted one. It should be noted that both the implanted and unimplanted areas are clearly detected
(1997) 166-170
even through an oxide layer in a non-destructive manner. The variation of the capacitance across the lateral p-n junction suggests the existence of a transition width of 1.25 pm. The origins of the transition region are the apex of the cantilever and grading in the p-n junction due to diffusion. It is interesting to note that a process simulation suggests a diffusion length of 260 nm during thermal annealing and thermal oxidation. The C-V characteristic at point 2 in the darker area shows a typical high-frequency C-V curve for p-type MOS (F ig. 2(b)). Holes accumulate at the SiO,/Si interface at a positive sample bias voltage, resulting in a high capacitance of the semiconductor. As a result, the total capacitance is close to the capacitance of the SiO, layer: C = C,,,. At a negative sample bias, on the other hand, a depletion layer is formed at the SiO,/Si interface, resulting in decrease in the total capacitance. Completely reverse characteristics are observed in the C-V curve at point 1 in the bright area, that is, the C-V characteristics of a typical n-type MOS structure. The capacitance at point 2 in the depletion regime is smaller than that of point 1, which implies that the impurity concentration at point 1 in the implanted region is larger than that at point 2 in the unimplanted region. The variation of the capacitance at point 1 is so small that the signal-to-noise ratio becomes lower. The resultant capacitance of the SiO,/Si under an accumulation condition should be close to that of the SiO, layer (C,,). The capacitance at point 1 in the accumulation regime is smaller than that at point 2. This may be explained in terms of the difference in oxide thickness. The oxidation speed of a heavily doped region becomes faster than that of a doped region [8], which results in a thicker oxide layer on highly P-doped Si, but a thinner layer on lightly B-doped Si. Consequently, the SiO, capacitance on the unimplanted area becomes larger than that on the implanted area. The l/C2-V plots for points 1 and 2 are well represented by straight lines with opposite slopes. The analysis of the slopes suggests that point 1 is of n-type with higher impurity concentration, while point 2 is of p-type with a lower impurity concentration, which completely agrees with the expected electrical properties of the implanted and unimplanted regions.
H. Tomiye et al./Applied
Surface Science 117/118
169
(1997) 166-170
4. Charge storage memory The sample used for the fabrication of charge storage memories was n-type Si (P-doped, 4.0 CI cm) with a thermal oxide layer of 10 nm thick. A negative sample bias was applied to inject charge into the SiO, layer. The charge injected regions are formed in circles as shown in Fig. 3(a), where a voltage pulse of - 6 V with 100 ms pulse width was applied. This pattern was bit-mapped on 128 X 128 grids and then written by computer control. The threshold voltage for writing was about - 5 V. Erasing of the written-in pattern was possible by apply-
Fig. 3. (a) SCaM image for 20 pm X 20 pm at a sample bias of 0 V. The charge injected regions are formed in circles as shown in this figure, where a voltage pulse of -6 V with 100 ms pulse width was applied. (b) shows a capacitance image after applying + 6 V pulses with 80 ms pulse width onto the center circle of (a).
-2.0
-1.0
0
1.0
2.0
3.0
Sample Bias Voltage [V] Fig. 4. The C-V characteristics were measured at 8 X 8 preset points during scanning. Point 1 is located in the bright area, where charges were injected, point 2 was not biased, and point 3 is located in the dark area, where erasing pulses were applied.
ing a positive bias. Fig. 3(b) shows a capacitance image after applying +6 V pulses with 80 ms pulse width on to the center circle of Fig. 3(a). It was possible to write-in a pattern by applying a negative pulse again. Then, one can ask where the injected charge is stored. The charge storing traps may be located either in the SiO, layer or at the SiOJSi interface. It is interesting to note that the pattern persisted more than one day, which suggests that the injected charges were stored at traps with a long escape time. Since the lifetime of the injected charge at the interface is much longer than that of the charge at the surface, the charge was most likely stored at the interface traps. Fig. 4 shows the capacitance-voltage curves at point 1 in the bright area, where charges were injected (point 2 which was not biased), and point 3 in the dark area, where erasing pulses were applied. These curves show a typical high-frequency C-V curve for n-type MOS. The shift of the flat band voltage is 0.2 V for the charged injected point, while it is 0.4 V for the erased point. This change in the flat band voltage is caused by negative interface charge induced by the application of the negative bias. On the other hand, the flat band voltage at the erased point shifts to the negative voltage side, which indicates that positive charge is induced either at the interface or in the SiO, layer. A comparison of the shift of the C-V curve for those points suggests that
170
H. Tomiye et al./Applied
Su$ace Science II7/118
the amount of trapped positive charge at the erased point is larger than that of trapped negative charge, assuming no stored charge at the unbiased region.
5. Conclusions We have investigated the local electrical properties of a SiO,/Si structure using a combined SCaM/AFM/STM, in which a novel SCaM is invented. The direct capacitance measurement using the SCaM reflects the electrical properties of the Si substrate and SiO,/Si interface. A lateral p-n junction is formed by ion implantation of P into a lightly B-doped Si wafer followed by thermal oxidation. It is demonstrated that (1) the p-n junction can be observed even through the oxide layer, (2) local impurity concentration can be estimated from C-V characteristics, and (3) P diffused into lightly Bdoped region during thermal processes. In addition, we have injected charge into the SiO, layer, by which local electrical properties are greatly modified. The charge was most likely stored at the interface traps. The pattern persisted more than one day, which suggests that the injected charges were stored at traps with a long escape time. A comparison of the shift of the flat band voltage suggests that the amount of trapped positive charges at the erased point is
(1997) 166-170
larger than that of trapped negative charge, assuming no stored charge at the unbiased region. In conclusion, we have demonstrated the feasibility of the combined SCaM/AFM/STM as a powerful tool for nanometer scale characterization of semiconductor surfaces and interfaces.
Acknowledgements We would like to thank N. Akiyama of Japan Victor Co., Ltd. for providing a capacitance sensor.
References 111S.M. Sze, Physics of Semiconductor
Devices, Wiley, New York, 1969. 121J.R. Matey, J. Blanc, J. Appl. Phys. 57 (1985) 1437. [31C.C. Williams, W.P. Hough, S.A. Rishton, Appl. Phys. Lett. 55 (1989) 203. I41 C.C. Williams, J. Slinkman, W.P. Hough, H.K. Wickramasinghe, Appl. Phys. Lett. 55 (1989) 1662. [51C.D. Bugg, P.J. King, J. Phys. E 21 (1988) 147. [61 R.C. Palmer, E.J. Denlinger, H. Kawamoto, RCA Rev. 43 (1982) 194. [71H. Tomiye, H. Kawami, M. Izawa, M. Yoshimura, T. Yao, Jpn. J. Appl. Phys. 34 (1995) 3376. [81C.P. Ho, J.D. Plumer, J.D. Meindl, B.E. Deal, J. Electrochem. Sot. 15 (1978) 665.
..“...~.~ ~,,:::: ;,;i
“:“;‘“.‘~‘:.~:~.:.:..:.?:a ...........................~,.:.:,~,:~.:,:,:,; ‘“‘w::::(:,~~ .......... g:~;.~,~..y i.. ... L
. .. .
w
applied
surface science EISEVIER
Applied SurfaceScience 117/l 18(1997) 166-170
Characterization of SiO,/Si with a novel scanning capacitance microscope combined with an atomic force microscope Hideto Tomiye a,*, Hiroshi Kawami b~l,Takafumi Yao a,2 a Institutefor Materials Research, Tohoku Uniuersiry, Aoba-ku, Sendai 980-77, Japan b Nissin Electric Co., Ltd., Ukyo-ku, Kyoto 615, Japan
Abstract We have investigated the local electrical properties of an SiO,/Si structure using a novel scanning capacitance microscope (S&M) combined with an atomic force microscope (AFM). The electrical properties of the SiO,/Si system is investigated using the microscope. We investigated a lateral p-n junction is formed by ion implantation of P into a lightly B-doped Si wafer followed by thermal oxidation. It is demonstrated that the local impurity concentration profiling is achieved by the C-V characteristics. In the next experiment we have injected charge into SiO, and investigated the nature of charge storage at the SiOJSi interface. Erasing of the written-in pattern was possible by applying a positive pulse. This paper will report on the development of a novel SCaM and its application to the characterization of SiO,/Si and fabrication of a charge storage device. Keywords: Scanning capacitance microscope; Atomic force microscope; Scanning tunneling microscope; SiO,/Si;
1. Introduction Capacitance measurement is one of the most important characterization techniques for semiconductors and semiconductor devices, since it provide indispensable information on electrical properties of semiconductors, including impurity concentration, flat band voltage, deep levels, interface states, built-in potential, and so on [l]. Hence there have been various characterization techniques based on capacitance measurements. However, most of these measurements could elucidate only macro-scale electrical
* Corresponding author. _Tel.: + 81-022-2152074; fax: + 81022-2152073; e-mail: [email protected]. ’ Fax: + 81-0720-595770.
’ E-mail: [email protected].
Trapped charge
properties with lateral resolution much poorer than 100 pm. In view of the recent developments of semiconductor devices towards the nano-scale regime, there is an increasing demand for nano-scale characterization of electrical properties of semiconductors. Although the scanning capacitance microscopy (S&M) should basically elucidate local electrical properties on nanometer scale, there have been only few reports on the development of SCaMs and their application to local electrical characterization of semiconductors [2,3]. However, most of those SCaMs give capacitance due to the topographic change of the surface in addition to that of the specimen itself with a poor lateral resolution of 200 n&2 ,um [4,5]. Recently an AFM was modified to construct a SCaM by attaching a capacitance sensor [6]. However, dC/dV was measured rather than capacitance, be-
0169-4332/97/$17.00 Copyright 0 1997 Elsevier Science B.V. All rights reserved. PII SO169-4332(97)00028-7
H. Tomiye et al/Applied
Surface Science I17/
cause of the stray capacitance between the tip and the surface. In a previous paper, we have demonstrated the development of a combined SCaM/STM/AFM system which enables measurements of surface topography, current-voltage, and capacitance-voltage characteristics [7]. Since the SCaM was made by attaching a capacitance sensor to an AFM, the spatial resolution should be sacrificed to enhance the specimen capacitance compared to the stray capacitance. As a result, the lateral resolution was as large as 1 ,um. We have overcome these problems by developing a novel SCaM with lateral resolution less than 100 nm. This paper will report on the development of a novel SCaM and its application to the characterization of SiO,/Si and fabrication of a charge storage device.
2. Scanning capacitance
microscope
The most crucial element of a SCaM is cantilever, since spatial resolution and sensitivity are essentially determined by the cantilever. As mentioned above, stray capacitance associated with a conductive micro cantilever is so large that the sample capacitance can only be detected at an expense of spatial resolution, that is, increase in contact area. It should be stressed that a reduction in stray capacitance should result in both more sensitive detection of the sample capacitance and improved lateral resolution. In order to solve the problem, we have invented a
118 (1997) 166-170
167
new type cantilever made of tungsten wire which was sharpened by electrochemical etching. The cantilever was formed by bending the tip close to the tip end. Stray capacitance for this tip is estimated to be 0.01 pF which is orders of magnitudes smaller than that for a micro cantilever. We have developed a new detection technique for the deflection of the W wire cantilever, in which the cantilever is projected onto a position sensitive diode by a laser beam from the side. The vertical and lateral resolutions for an AFM mode operation were 50 nm and 100 nm, respectively, while the spatial resolution for a SCaM mode was 100 nm. The combined SCaM/AFM/STM was constructed by attaching a capacitance sensor and a current-voltage converter to an AFM with a W wire cantilever as schematically shown in Fig. 1. We can measure the local variations of capacitance, dC/dV and current at a fixed voltage as well as surface roughness for up to an area of 20 pm X 20 pm.
3. Lateral p-n junctions We investigated lateral p-n junctions formed by the following procedures: a line-and-space pattern was formed by ion implantation on a p-type B-doped Si wafer (NA w lOI cme3), where the widths of the line and space were 2 pm and 4 pm, respectively; P+ ion was implanted into the Si wafer at 50 kV to a dose of lOI4 cm- *, followed by annealing at 950°C
beam deflectoin
computer Fig. 1. Schematic of the combined SCaM/AFM/STM in which a new detection technique for the deflection TheW wire cantilever is projected onto a position sensitive diode by a laser beam from the side.
of the cantilever
is invented.
H. Tomiye et al./Applied
168
-5.0
-2.5
0
2.5
Surface Science 117/118
I
5.0
Sample Bias Voltage [V] Fig. 2. (a) SCaM image, (b) C-V characteristics. The SCaM image (10 ymX 10 pm) was obtained at a sample bias voltage of 0 V. Point 1 is located in the bright area corresponding to higher capacitance, while point 2 is located in the lower-capacitance area.
for 30 min in H,. A thermal oxide layer of 10 nm thick was formed at 1000°C for 15 min. Fig. 2 (a) shows a SCaM image at 0 V. The detected capacitance (C) is a series combination of the capacitance of the SiO, layer (C,,) and that of a depletion layer in the Si substrate (Csi) formed just below the cantilever: l/C = l/C,, + l/Csi. Since C,,, is constant, the SCaM image reflects the variation of the capacitance of the depletion layer at 0 V. Since the Csi value should decrease with decrease in impurity concentration, the bright region corresponds to the implanted region, while the dark one to the un-implanted one. It should be noted that both the implanted and unimplanted areas are clearly detected
(1997) 166-170
even through an oxide layer in a non-destructive manner. The variation of the capacitance across the lateral p-n junction suggests the existence of a transition width of 1.25 pm. The origins of the transition region are the apex of the cantilever and grading in the p-n junction due to diffusion. It is interesting to note that a process simulation suggests a diffusion length of 260 nm during thermal annealing and thermal oxidation. The C-V characteristic at point 2 in the darker area shows a typical high-frequency C-V curve for p-type MOS (F ig. 2(b)). Holes accumulate at the SiO,/Si interface at a positive sample bias voltage, resulting in a high capacitance of the semiconductor. As a result, the total capacitance is close to the capacitance of the SiO, layer: C = C,,,. At a negative sample bias, on the other hand, a depletion layer is formed at the SiO,/Si interface, resulting in decrease in the total capacitance. Completely reverse characteristics are observed in the C-V curve at point 1 in the bright area, that is, the C-V characteristics of a typical n-type MOS structure. The capacitance at point 2 in the depletion regime is smaller than that of point 1, which implies that the impurity concentration at point 1 in the implanted region is larger than that at point 2 in the unimplanted region. The variation of the capacitance at point 1 is so small that the signal-to-noise ratio becomes lower. The resultant capacitance of the SiO,/Si under an accumulation condition should be close to that of the SiO, layer (C,,). The capacitance at point 1 in the accumulation regime is smaller than that at point 2. This may be explained in terms of the difference in oxide thickness. The oxidation speed of a heavily doped region becomes faster than that of a doped region [8], which results in a thicker oxide layer on highly P-doped Si, but a thinner layer on lightly B-doped Si. Consequently, the SiO, capacitance on the unimplanted area becomes larger than that on the implanted area. The l/C2-V plots for points 1 and 2 are well represented by straight lines with opposite slopes. The analysis of the slopes suggests that point 1 is of n-type with higher impurity concentration, while point 2 is of p-type with a lower impurity concentration, which completely agrees with the expected electrical properties of the implanted and unimplanted regions.
H. Tomiye et al./Applied
Surface Science 117/118
169
(1997) 166-170
4. Charge storage memory The sample used for the fabrication of charge storage memories was n-type Si (P-doped, 4.0 CI cm) with a thermal oxide layer of 10 nm thick. A negative sample bias was applied to inject charge into the SiO, layer. The charge injected regions are formed in circles as shown in Fig. 3(a), where a voltage pulse of - 6 V with 100 ms pulse width was applied. This pattern was bit-mapped on 128 X 128 grids and then written by computer control. The threshold voltage for writing was about - 5 V. Erasing of the written-in pattern was possible by apply-
Fig. 3. (a) SCaM image for 20 pm X 20 pm at a sample bias of 0 V. The charge injected regions are formed in circles as shown in this figure, where a voltage pulse of -6 V with 100 ms pulse width was applied. (b) shows a capacitance image after applying + 6 V pulses with 80 ms pulse width onto the center circle of (a).
-2.0
-1.0
0
1.0
2.0
3.0
Sample Bias Voltage [V] Fig. 4. The C-V characteristics were measured at 8 X 8 preset points during scanning. Point 1 is located in the bright area, where charges were injected, point 2 was not biased, and point 3 is located in the dark area, where erasing pulses were applied.
ing a positive bias. Fig. 3(b) shows a capacitance image after applying +6 V pulses with 80 ms pulse width on to the center circle of Fig. 3(a). It was possible to write-in a pattern by applying a negative pulse again. Then, one can ask where the injected charge is stored. The charge storing traps may be located either in the SiO, layer or at the SiOJSi interface. It is interesting to note that the pattern persisted more than one day, which suggests that the injected charges were stored at traps with a long escape time. Since the lifetime of the injected charge at the interface is much longer than that of the charge at the surface, the charge was most likely stored at the interface traps. Fig. 4 shows the capacitance-voltage curves at point 1 in the bright area, where charges were injected (point 2 which was not biased), and point 3 in the dark area, where erasing pulses were applied. These curves show a typical high-frequency C-V curve for n-type MOS. The shift of the flat band voltage is 0.2 V for the charged injected point, while it is 0.4 V for the erased point. This change in the flat band voltage is caused by negative interface charge induced by the application of the negative bias. On the other hand, the flat band voltage at the erased point shifts to the negative voltage side, which indicates that positive charge is induced either at the interface or in the SiO, layer. A comparison of the shift of the C-V curve for those points suggests that
170
H. Tomiye et al./Applied
Su$ace Science II7/118
the amount of trapped positive charge at the erased point is larger than that of trapped negative charge, assuming no stored charge at the unbiased region.
5. Conclusions We have investigated the local electrical properties of a SiO,/Si structure using a combined SCaM/AFM/STM, in which a novel SCaM is invented. The direct capacitance measurement using the SCaM reflects the electrical properties of the Si substrate and SiO,/Si interface. A lateral p-n junction is formed by ion implantation of P into a lightly B-doped Si wafer followed by thermal oxidation. It is demonstrated that (1) the p-n junction can be observed even through the oxide layer, (2) local impurity concentration can be estimated from C-V characteristics, and (3) P diffused into lightly Bdoped region during thermal processes. In addition, we have injected charge into the SiO, layer, by which local electrical properties are greatly modified. The charge was most likely stored at the interface traps. The pattern persisted more than one day, which suggests that the injected charges were stored at traps with a long escape time. A comparison of the shift of the flat band voltage suggests that the amount of trapped positive charges at the erased point is
(1997) 166-170
larger than that of trapped negative charge, assuming no stored charge at the unbiased region. In conclusion, we have demonstrated the feasibility of the combined SCaM/AFM/STM as a powerful tool for nanometer scale characterization of semiconductor surfaces and interfaces.
Acknowledgements We would like to thank N. Akiyama of Japan Victor Co., Ltd. for providing a capacitance sensor.
References 111S.M. Sze, Physics of Semiconductor
Devices, Wiley, New York, 1969. 121J.R. Matey, J. Blanc, J. Appl. Phys. 57 (1985) 1437. [31C.C. Williams, W.P. Hough, S.A. Rishton, Appl. Phys. Lett. 55 (1989) 203. I41 C.C. Williams, J. Slinkman, W.P. Hough, H.K. Wickramasinghe, Appl. Phys. Lett. 55 (1989) 1662. [51C.D. Bugg, P.J. King, J. Phys. E 21 (1988) 147. [61 R.C. Palmer, E.J. Denlinger, H. Kawamoto, RCA Rev. 43 (1982) 194. [71H. Tomiye, H. Kawami, M. Izawa, M. Yoshimura, T. Yao, Jpn. J. Appl. Phys. 34 (1995) 3376. [81C.P. Ho, J.D. Plumer, J.D. Meindl, B.E. Deal, J. Electrochem. Sot. 15 (1978) 665.