Charge collection and SEU mechanisms

Radial. Phys. Chain. Vol. 43, No. 1/2, pp. 151—163, 1994 Printed in Great Britain. All rights reserved

0969-806X/94 $6.00 + 0.00 Copyright (i~1993 Pergamon Press Ltd

CHARGE COLLECTION AND SEU MECHANISMS 0.

MUSSEAU

CEA, BP 12, F91680 Bruyéres le Châtel, France Abstract—In the interaction of cosmic ions with microelectronic devices a dense electron—hole plasma is created along the ion track. Carriers are separated and transported by the electric field and under the action ofthe concentration gradient. The subsequent collection of these carriers induces a transient current at some electrical node of the device. This “ionocurrent” (single ion induced current) acts as any electrical perturbation in the device, propagating in the circuit and inducing failures. In bistable systems (registers, memories) the stored data can be upset. In clocked devices (microprocessors) the parasitic perturbation may propagate through the device to the outputs. This type of failure only affects the information, and do not degrade the functionnality of the device. The purpose of this paper is to review the mechanisms of single event upset in microelectronic devices. Experimental and theoretical results are presented, and actual questions and problems are discussed. A brief introduction recalls the creation of the dense plasma of electron—hole pairs. The basic processes forcharge collection in a simplenp junction (drift and diffusion) are presented. The funneling-field effect is discussed and experimental results are compared to numerical simulations and semi-empirical models. Charge collection in actual microelectronic structures is then presented. Due to the parasitic elements, coupling effects are observed. Geometrical effects, in densely packed structures, results in multiple errors. Electronic couplings are due to the carriers in excess, acting as minority carriers, that trigger parasitic bipolar transistors. Single event upset of memory cells is discussed, based on numerical and experimental data. The main parameters for device characterization are presented. From the physical interpretation of charge collection mechanisms, the intrinsic sensitivity of various microelectronic technologies is determined and compared to experimental data. Scaling laws and future trends are finally discussed.

effects of cosmic particles (Ziegler and Lanford, 1979). Lots of theoretical and experimental results are now available, covering all the aspects of the phenomena (environment, basic phenomena, device characterization).

I. INTRODUCHON

focused on the

Single Event Effects (SEE) refer to the effects of a single particle, such as a cosmic ion, in microelectronic devices, generally used in a spaceborne system. Among all possible SEE, the most commonly studied are Single Event Upsets, in which a logical information stored in a register or a memory cell, or treated by a microprocessor, is modified (“upset”), with no degradation of the device itself.

1.2. Electron—hole plasma creation by a cosmic ion

The basis of SEE is the interaction of a single particle that transfers a part of its energy to a microelectronic device. In the case of an incident ion, the transferred energy could be high so that a single ion would induce a perturbation (the converse ofcumulated y dose effects due to the interaction of large numbers of particles). In the interaction of an energetic particle, target atoms are ionized. In these inelastic interactions (coulombic process), free electrons are ejected with large energies, and the ion trajectory remains

1.1. A brief historical review of Single Event Upsets (SEU) in microelectronic devices

cosmic enough

Based on scaling laws and the involved reduction noise margins of microelectronic devices, a previsible influence of cosmic particles that could limit device integration has been predicted as early as 1962 (Wallmark and Marcus, 1962). The first failures in spaceborne devices, observed 13 years later (Binder et al., 1975), remained a lonely result until random failures were observed in large scale dynamic memories used in computers (Hershberger and Hanson, 1978). An important research effort started up at this date, first to solve problems encountered in ground-based computers, and then to assess the sensitivity of devices in space applications, Failures in DRAMs were due to ~ particles emitted by radioisotopes present in packaging materials (May and Woods, 1978), and successful solutions have been rapidly proposed, using purification of materials or device coating. Nevertheless device sensitivity has been clearly demonstrated and the research effort in

approximately a straight line. results The decay of the energy of these primary electrons in an electronic cascade, in which each electron ionizes target atoms until its energy decreases below the ionization threshold. The result of this process is the creation of a dense plasma (electrons and lattice ions) in the wake of the ion. In semiconductors where most charges do not recombine, this plasma decays in an electron—hole plasma, usually called the ion track. The energy required to create an electron—hole pair, wi,, is related to the bandgap Eg by the semi-empirical relation (Klein, 1966): w~= 2.67 Eg + 0.87 eV. 151

(I)

152

0. Musm.~u

This energy (3.6 eV in silicon) is independent of the ion mass and energy.

Along the axis of the track, the density ofelectron— hole pairs (ehp) is proportional to the Linear Energy Transfer (LET) of the ion in the target (LET = I/p dE/dx, p is the density of the target). In the radial direction, the ehp density is supposed to have a gaussian variation in the core region (Martin and Ghoniem, 1987). The radius of the track is usually defined by comparing the pair density (that may peak 3 for high LET ions) to the to more than 1020 cm

70V

55V

local dopant concentration. Due to the energy loss

mechanism (energy of primary electrons), the track radius also depends on the ion velocity, and for a same LET a swifter ion will have a larger but less dense track than a slower one, this can lead to different effects in microelectronic devices (Stapor et a!., 1988).

—.--

—.

Fig. 2. Funneling field effect: distorsion of the potential a diode.

in

2. CHARGE COLLECTION IN A NP JUNCTION

Electron—hole pairs created in the semiconductor are separated and transported by the electric field and by diffusion. The charges are finally collected at an electrode of the device where they produce a

In the substrate the ehp density exceeds the doping concentration by several orders of magnitude. The charge current equation for electrons can be written as: J~= qnp

in the basic np junction, present in nearly any

5E + qD~grad n (2) where J5 is the electron current, n the density of free electrons, p~,and D~the electron mobility and diffusion coefficient, respectively. In this expression

microelectronic device,

the two terms are responsible for two components of

2.1. Description of the device

the current that may be separated in space and time (drift and diffusion currents).

transient “ionocurrent” that may propagate through

the circuit. This part discusses charge collection

We consider a n + p diode, in which a rectifying junction is formed between an heavily 3, thickness < Idoped ~zm) thin and layerdoped (N0>pio’~ cm substrate (NA < 1Q16 cm3, an +low type thickness> 100 pm). The device is presented on Fig. I. A reverse bias V 0 creates a depletion layer (thickness w0) where an electric field is established. This

2.2.2.2.1. Funneling field effect Description of the effect. As electron and hole are created in equal densities (i~n= Ap), the

volume of the track would remain neutral. When the ion crosses a depletion layer, the electric field is locally screened by the very high density of injected

structure is struck by an energetic ion striking the surface normally. We assume an initial track radius r0, and a track length greater than the substrate

carriers (compared to the local density of fixed doping ions in the space charge region), and the potential surfaces are distorted along the track. If the total

thickness.

voltage drop is constant (externally maintained), the field magnitude is decreased. Nevertheless the portion

of the track subjected to the electric field is greatly enhanced. In this region carriers are separated,

Prompt axial current drifted by the electric field

\

\

Ion track perpendicular to the depleted region N+

_________ /

/

/‘.‘

Track ~

/

/‘,,

/‘‘‘

Ic

1 Depleted

region thickness w0

ngth

____________________________ Delayed diffusion current due to radial gradient of Concentration

Fig. 1. Representation of a n + p diode irradiated in normal incidence.

drifted by the field and collected at the electrode

(Fig. 2). This “funneling field” effect (named from the shape of the potential lines in numerical simulations) is then largely exceeding those deposited in the depleted regton. Thisforeffect has been first established by responsible the prompt collection of a total charge numerical simulations (Hsieh el a!., 1981), that corroborate previous unexplained experimental results (Yaney et al., 1979). Time resolved measurements have shown that the rise time of the current

pulse increases from 40 to 130 ps with the LET of the incident ion (‘VI,’agner et al., 1988). From experimental data of charge collection (measured by integration of the fast current pulse in

Charge collection

and SEU mechanisms

153

Table I. Summary of semi-empirical models of funneling in np diodes Model Funneling length Transient current Prompt collected charge Hu (1982) X X Messenger (1982) X McLean and Oldham (1982)

X

X

Gilbert at a!. (1985) Shur el a!. (1986) Grubin at a!. (1984) Edmonds (1991)

X

a charge preamplifier) an effective funneling length LF can be defined by comparison of the prompt collected charge QF with the deposited charge (by integration of the linear energy transfer dE/dx along the ion track): q QF =

wp

CLF

X X

X X

dE

dx

(3)

2.2.2. Discussion of semi-empirical models. Many semi-empirical models have been proposed to give a comprehensive picture of the funneling field effect in np diodes. Table 1 summarizes most of these models, and indicates the predicted parameters (funneling length, transient current or prompt collected charge). As funneling results from non-linear coupled differential equations (Poisson’s equation, current and continuity equations, etc.), there is no analytical

collection occurs only at the periphery of the columns which increases and then decreases to zero. Grubin et a!. (1984) give a simple model based on the voltage drop in serial resistors (the track and the substrate). Edmonds (1991) proposes a neat solution, based on symmetrical properties of global equations [equation (2) for example]. The collected charge is then determined by the mobility ratio. Among all these models, the most helpful to estimate funneling effect in a given diode are those proposed by McLean and Oldham (1982) on one hand, and on the other hand Hu (1982) and Edmonds (1991) that give identical expressions for the funneling length. The predicted expressions of funneling length and collected charge are (McLean and Oldham, 1982)

1

L~= ~,/p.~V

0exp(—KN0) [ 3N0 (4) solution of the problem. Tractable formulations [81tNAv~Th] based on simplifying assumptions have been proposed. Nevertheless none of these models gives a fully QF = qN0L~ (5) satisfying description of the physical phenomena. and ELF from Hu (1982) and QF from Edmonds Hu (1982) assumes that funneling is controlled by (1991)]: the axial current of minority carriers drifted in the track resistor from the electrode tothe substrate (with = (1 + (6) cos U a symmetrical current flowing in the opposite direction). The funneling length is finaly determined by the equilibrium between these two current flows. QF = (1 + Qt. (7) 14! Messenger (1982) assumes a double exponential shape of the prompt current. The current decay is In these expressions V0 is the applied bias, K a then determined by an ohmic voltage drop in the screening factor, N0 the linear density of carriers in track. This model supposes a delay time prior to the track, v~,the average velocity of holes (majority charge collection. McLean and Oldham (1982) give carriers in the substrate, with a doping concentration the expression of an effective funneling length NA), D the ambipolar diffusion constant, W the controlled by the equilibrium between a radial and an depletion thickness, 0 the angle of incidence and Q0 axial current (respectively majority and minority the total charge deposited in the depleted layer. carriers). A screening factor in the voltage drop is 2.2.3. Scaling parwneters. Table 2 summarizes the introduced to fit predictions with experimental data influence of principal physical parameters on the with high LETions (high track density). Gilbert et a!. collected charge and funneling length. (1985) propose a corrective factor to the previous Experimental and numerical data indicate that the model, calculated by analogy to the skin effect. funneling length increases linearly with the depleted Shur et a!. (1986) assume that the evolution of the layer thickness (Yaney et a!., 1979; Patin et a!., track is controlled by ambipolar drift. Charge 1989), in agreement with some models, and could ~

—~—

Table 2. Influence of physical parameters on the funneling field effect Substrate doping Voltage LET of the ion Collected charge ft ft Funneling length * = Symbols must be interpreted as follows: ~: decreases with increasing parameter; *: increases strongly with increasing parameter; =: independent of the parameter.

154

0.

MUSSEAU

exceed 10pm. Furthermore funneling depends on the substrate doping. For very low doping levels the funneling efficiency decreases to (NA
I

I

I

J

relaxation time that prevents rapid variation of the potential (Shanfield et a!., 1985). On the other hand funneling length decreases when the doping level increases (Hsieh eta!., 1981; Hu, 1982). The funneling length (in large diodes) is largely independent of the track density (and of the ion LET) (Patin et a!., 1989). Finally, funneling may depend on the total charge stored in the depletion layer, as suggested by numerical data (Takeda et a!., 1986), and indirectly by experimental results (~outendyk et a!., 1989). Collection of a charge greater than the stored charge would actually completely collapse the

I

Ideal MOSFET Gate

Source

I

I

I

I

Epilayer Substrate Real structure with parasitic elements

Fig. 3. Parasitic elements

in a CMOS/epi structure.

2.3. Collection by d~ffusion

zone

(tr = £

Collection by diffusion is represented by the second term in equation (2). As the gradient of concentration is extending radially to thetrack, carriers diffuse from the track until they reach a depleted region where they are finally collected by drift. Diffusion is effective only in the deepest part of the track beyond the funneling length. In large diodes, used by experimentalists in charge collection measurements to check models accuracy, diffusing carriers are collected by the diode itself. They are then responsible for a delayed current (compared to the prompt funneling current) which amplitude can be estimated from direct measurements. In integrated devices diffusing carriers are collected by many depletion regions neighbouring the struck diode. In large volume memories, where funneling

~ft

wipE> l0-~s for a w

1989). 2.4. D~/ferencewith nuclear physic detectors

Silicon diodes have been used for a long time as particle detectors in nuclear and high energy physic

experiments. From the large set of available data only a small part. can be used to interpret charge collection mechanisms in microelectronic devices. The basic reason arises from the large difference in substrate doping. Silicon detectors generally use a high resistivity material (very low doping, in the order of 1013 cm3), in order to get a very thick depletion

region (up to 2000 pm, so as to detect low LET particles), by applying a large reverse bias (hundreds of volts). Funneling that could only occur in partially depleted diodes is avoided by the high value of the dielectric relaxation time r~, comparable to the time tdflft required to travel accross the depleted

I

Well

diodes, in integrated circuits (e.g. large density DRAMs).

diodes, the total charge in surrounding diodes may be large enough to induce multiple errors due to a single ion (Song et a!., 1988; Zoutendyk et a!.,

Drain

t~F~

~

electric field and inhibit the funneling mechanism. This effect would be significant only for very small

may be limited by the very small size of individuals

II

=

/qnp in the order of l0-~—l0-~s; =

100 pm depleted

layer). 3. CHARGE COLLECFION IN REAL MICROELECTRONIC

STRUCTURES

3.1. Description of a real device: presence of parasitic structures

In a real microelectronic device the active region (that controls the current flow representing the information) represents only a very small part of the silicon volume. We can distinguish three classes of basic parasitic structures depending on their role in the final device: —Class 1: parasitic structures related to the main device itself (e.g. drain—substrate diode in a MOS transistor) and due to the extension of doped zones accessing to the active region. —Class 2: isolation structures between adjacent devices (reverse biased diodes, capacitors). —Class 3: resistors along the current lines in

semiconducing regions. The two former are active regions, where the electric field in depleted regions can separate injected carriers. The latter are passive regions, that may limit the current flow between active regions. All parasitic elements are shown in Fig. 3, in the case of a standard CMOS/epi structure (numbers 1—3 refer to the previously defined classes). A rough estimate indicates that the volume of Class I and Class 2 structures are respectively 1 and 2 orders of magnitude greater than the active volume (for a typical 1 pm, CMOS technology). It is then obvious that the sensitivity of CMOS microelectronic devices, resulting from charge collection mechanisms in basic structures is mostly controlled by parasitic

elements. Moreover, as the active region is completely

Charge collection and SEU mechanisms

155

some new

coupling). This effect leads to multiple errors along

mechanisms may occur, triggered by the ion interaction,

the ion track in memory arrays, that can’t be corrected by standard methods (EDAC). —Multiple bit upsets (Zoutendyk eta!., 1987, 1988, 1989). As the maximum charge collected by funneling may be limited by the charge stored in the struck diode, for dense array of very small diodes, a large amount of charge may be collected by diffusion in several neighbouringjunctions. This effect has been observed in 256 k DRAMs, with low sensitivity threshold, where a weak collected charge is required to upset a cell. More than 10

surrounded by

parasitic structures,

3.2. Geometrical effects

Geometrical effects involve the perturbation of several structures by a unique ion. Carriers created in

the ion track are collected by different parasitic elements. For each depleted region the main collection mechanism depends on the distance to the track. Three major classes of geometrical effects can be detailed:

simultaneous errors in adjacent cells have been recorded. Furthermore the number of multiple bit upsets increases when the supply voltage decreases. This phenomenon will drastically increase the sensitivity of high integration devices, with no possibility of correction.

—Ion shunt effect (Hauser et a!., 1985). The ion track crosses several stacked depleted regions reversely biased (e.g. ion incident normally to a n + pnn + structure, in CMOS/epi technology). A direct current flow is first established between the external regions (n +), controlled by the total

3.3. Electronic couplings: bipolar effects

voltage drop across the device (Kreskovsky and Grubin, 1985, 1986). This current is stopped when

In many cases parasitic structures of a real device

one the potential barrier is restored in the central p region, the diodes being then discoupled (Chern et a!., 1986). Charges are collected by drift, and, depending on the applied bias, the total transiting charge may exceed what would have been collected only by funneling, —Grazing angle of irradiation (Criswell et a!., 1984, 1987). At very high angles of incidence (75—90° with respect to the normal direction), a

include bipolar transistors, formed by two adjacent diodes. Figure 4 identifies these transistors for

single ion may cross several sensitive regions.

(e.g. npn) minority carriers (electrons) are rapidly

Charges are collected by drift and diffusion. As the

drifted out of the base. Majority carriers (holes)

track is nearly parallel to the depleted regions, there is no funneling and charge collection occurs

remain “trapped” in the potential well, their collection being limited by the base resistor. This charge storage increases the base potential and by lowering

CMOS/epi,

_____

and

CMOS/SO!

resistor. When an ion crosses the bipolar transistor

(B)

PMOS

NMOS

MOSFET

transistor remains in a off-state. However all these transistors incorporate a relatively high serial base

independently in all the sensitive regions (no (A)

power

devices. For the common use of the devices both emitter—base and base—collector junction are grounded or reverse biased, and the parasitic bipolar

S

CMOS/epilayer

G

I

_________

Power MOSFET

G

(C)

/Buried oxide

MOS/SOl

Fig. 4. Parasitic bipolar transistors in real devices. (A) CMOS/epi, (B) power MOSFET, (C) CMOS/SOI.

156

0.

MUSSEAU

the emitter—base voltage barrier then turns on the bipolar transistor.

4.1. Characterization of the sensitivity of complex devices

This effect is commonly observed in CMOS/bulk

In practical use the sensitivity of most complex

circuits and n-type power MOSFETs where it induces permanent failures (latchup and second breakdown burnout, respectively). In MOS on SOI test structures, without efficient base—emitter body ties, the turn on of the parasitic bipolar transistor by a high LET ion is responsible of the recently observed single bipolar latch effect (Musseau et a!., 1991) A related effect has been reported in GaAs short channel field effect transistors on semi-insulating substrate. Electrons created in the substrate are drifted by the source-drain field and rapidly collected, while the remaining holes “trapped” in the

devices can be estimated by simple measurements, with no direct reference to the previous parameters. 4.1.1. Sensitivity threshold (critical charge). For

insulating substrate lower the potential barrier (and increase the substrate conductivity). The net result is an enhancement of the collected charge, due to this so called “bipolar” mechanism (Campbell et a!., 1989). 3.4. Influence of the radial structure of the track As previously reported, charge collection mechanisms are simply related to the energy deposited in the ion track. The immediate consequence is the determination of device sensitivity versus ion LET, as reported in most test data. Nevertheless charge collection measurements in CMOS/SOS devices, with a well defined collection length have

shown a significant influence of the ion energy, for a given LET (Stapor et a!., 1988). The observed differences are attributed to the radial density of carriers in the track (the greater the ion energy, the larger the track radius) and to recombination in the core of the track (increasing with carrier density). This influence of the track structure will probably

become significant in largely submicron devices, where the track radius (approximately 0.1 pm) and the transistor length will be comparable. 4. SINGLE EVENT UPSET OF COMPLEX DEVICES Complex devices result from the assembling of a very large number of individual transistors, each one including its own parasitic elements. These structures,

principal or parasitic, are responsible for the collection of carriers deposited in ion track, that induces a transient current at one (or several) electrical node of the device. The response of the device to this perturbation is then determined by three parameters:

a given electrical node, the sensitivity threshold is determined by the smallest perturbation that induces a detectable error on the outputs of the device. This threshold may depend on the pulse

shape, but as prompt collection duration is shorter than the response time of usual devices (1992 state of the art), this could mostly affect collection by diffusion. Although electrical simulations show a great influence of the pulse shape (Diehl et a!., 1982; Dall’Agnese et a!., 1986; Cable et a!., 1986; Zoutendyk et a!., 1987), that could vary the

threshold, but there is no experimental evidence such an effect. The sensitivity threshold of a complex device is

finally determined by the threshold of the most sensitive part. It is measured by a charge Q~(critical charge, by integration of the fast transient current), that can be converted into an energy E~: E

=

=

q

j

L dE = ~

~ (x) dx

(8)

The critical energy is determined by integration of the

energy deposition in the device along the ion track (length L). This expression mathematically defines the differential collection yield, ~ as the ratio of the charge collected at x = 0 to the charge deposited at abscissa x along the ion track. Equations (3) and (8) are simply related when collection occurs by funneling, with a yield equal to 1. In this particular

case, electron—hole recombination is neglected. 4.1.2. Cross section (sensitive area). The cross section is equal to the total area of the sensitive electrical nodes of the device. This sensitive area depends on the characteristics of the incident particles, and increases with increasing energy deposition, until an asymptotic value is reached (ar). Experimentally cross section is calculated by the ratio of the number of upsets by the fluence of

particles. 4.1.3. Sensitive volume. As the stopping power of cosmic ions is generally constant over the short interaction length involved in these phenomena, equation (8) can be simplified to define the LET

—the duration of the pulse, compared to the time response of the device, —the noise margins of the perturbated electrical node,

threshold (critical LET: LET~): E~ dE l’x=L

—the total charge in the transient current. These parameters are correlated and can’t be addressed separately. They depend on both the ion (mass, energy), the structure of the device and the conditions of interaction (hit point, angle of

= p LETC L,~ (9) In this equation the integral represents an effective collection length Lee, obtained by averaging the collection yield over the total track length, for the whole sensitive area of the device. For a single

incidence),

sensitive area, in which funneling dominates (short

=

—

X

~

(x)dx =

p LETC

I

?l~(x)dx

Charge collection and SEU mechanisms

(A)

157

take into account the influence of track structure. A more general expression of the critical energy [equation (9)] must detail the variation of ~~(x)with

Storage capacitor

the track structure, including recombination for high

Bit line

=L_~ —

____

—

~

_r...

~

~I1 1.

:

I_.~_ T_....,_ —

/

LET ions. Furthermore the collection efficiency

depends of the device and on the geometryonof the the structure interaction. The definition of cross section implicitly assumes that the track section is small compared to the

Word line

:~- DRAM cell

1I.~_

sensitive area (in order to get a local probability of failure). In submicronic devices (technologies with

—

Access transistor

NMOS DRAM: Electrical structure (B)

Storage capacitor Ia ~I

Bit line

—

Access transistor Ia . Word line

_________________

~

4.2. Charge sensitive devices (dynamic memories DRAM, charge coupled devices CCD)

p— substrate

NMOS DRAM: Physical structure Fig. 5. NMOS dynamic memory cells. (A) Electrical structure, (B) physical structure. ion track, or a large area) this effective collection length is identical to the effective funneling length. In most cases (complex device with many small size sensitive cells), it represents only a convenient par-

ameter to describe global charge collection allowing rules of thumb derivations.

The sensitive volume is then defined by the product of the asymptotic cross section by the effective collection length. This concept only represents a first order approximation of the sensitivity of a device, but it can be very usefull to estimate and compare the sensitivity of different technologies, 4.1.4. Physical limitations of this simp!jfied mode!, The definition of the sensitivity threshold does not

(A)

01

02

03

transistor gates smaller than 0.5 pm), the ion track becomes of comparable dimensions (about 0.1 pm), and the accuracy in the determination of cross section will be limited by the size of the track (including track structure effects previously discussed).

4.2.1. Basic structure. In charge sensitive devices, the logical or analogue information is represented by the amount of minority carriers stored in the depletion region of a MOS capacitor. Typical structures of DRAM and CCD cells are presented in Figs 5 and 6.

Dynamic memories use respectively inversion and deep depletion modes ofthe MOS capacitor (presence or absence of a charge of minority carriers) to

distinguish between low and high logical levels. This is an unstable process that requires a periodic refreshing of stored levels in the passive elements. In CCD potential wells are held in depletion, and by clocked variation of the applied voltages on successive electrodes, carriers are transferred from a well to the next. In logical applications, CCD operates like DRAM, with a given charge to separate two logical levels. In analog applications, like optical imaging, carriers are generated by the photons interacting in the device, and the charge is

proportional to the light intensity. 4.2.2. Sensitive region. Charge sensitive devices use depleted regions as active structures. For these cir-

01

cuits, the operating structure is also the most sensitive to heavy ions and determines the sensitive volume. In very dense CCD individual cells may be strongly

________________________________ ..:

Si0

2

________________________________ 5V iov 5V 5V (B)

_____________________________________

coupled by a single ion that could distort adjacent potential wells. 4.2.3. Upset mechanism. Carriers deposited along the ion track are primarily collected by funneling. When the maximum charge is reached (determined by the charge stored in the capacitor), remaining carriers are collected by diffusion. The time constants of transient currents have no importance, as the information stored in passive capacitors. Furthermore,isassimply sensitive elements are very densely

_______________________________ 5V

~

15V

5V

Fig. 6. Charge coupled devices. (A) Cross

section of a

three-phase CCD structure, (B) charge transfer from a well to the next,

packed, charge collection in neighbouring volumes may induce simultaneous upsets from a single ion (Bisgrove, 1986; Zoutendyk et a!., 1989). Due to these two mechanisms, minority carriers are

transported into one or several potential wells of the

158

0.

MUSSEAU

(B)

(C)

(A) Vdd

Vdd bit

bit

bit

I

I

I

~

~V~bit

_____ .*.

data

Word

~

data

Fig. 7. Electrical structure of SRAM cells. (A) bipolar TI’L technology. (B) CMOS technology. (C) NMOS technology.

device. In dense arrays of imaging CCD the net result will be a parasitic image of charge collection, with

determined by electrical simulations (Diehl et a!., 1982), this result has been confirmed by simultaneous

saturation of pixels where funneling occurs. In

measurement and imaging of the charge collection in a cell, using a nuclear microprobe (Horn eta!., 1992). At first order there are two distinct sensitive regions related to both electrical nodes, one in the

DRAMs, depending on

the cell logical value,

collected carriers increase the total charge in the inversion layer (no upset) or fill the empty potential well (upset). The sensitivity of a DRAM cell strongly depends on the stored value (Knudson, 1981). 4.3. Static memories (SRAM) 4.3.1 Basic structure. Static memory cells are bistable devices, that basically consist in a pair of cross-coupled inverters. Both high and low levels are present at the two internal nodes of the cell. If the cells were symetrical, “0” and “1” levels would have the same sensitivity. Nevertheless many experimental results are in discrepancy with this simplified assumption. Typical bipolar (TTL), NMOS and CMOS static cells are described in Fig. 7. As active elements are used in the storage process (transistors), the

stored energy (and then the sensitivity threshold) is greater than for DRAMs. 4.3.2. Sensitive region (CMOS technology). The sensitivity of static memory cells is due to parasitic structures tied to the internal nodes, where carriers can be promptly collected by the local electric field. In CMOS devices the sensitive regions are the drains of the off-biased transistors of the cell. First

I

2

3j ~

Off

~ On

lt

a 1

NMOS

Sensitive node

4.3.3. Upset mechanism. The detailed upset mechanism has been investigated by electrical simulations, by injection of a transient current in one of the internal nodes of the cell. In standby mode, CMOS or NMOS SRAMs are voltage sensitive devices in which the transient current charges (or discharges) a capacitor to induce a local voltage drop. Figure 8 illustrates the upset mechanism in a CMOS cell. Carriers collected in the NMOS drain split into three transient currents. Two currents flow

Vdd

PMOS

NMOS and the other in the PMOS. Nevertheless as collection mechanisms may be affected by the reverse biased well insulating NMOS from PMOS transistors, the final cross section may differ from the total area of transistor drains: —In CMOS on bulk substrate, all carriers deposited in the well may be collected at the drain of the transistor (Kreskovsky and Grubin, 1986). Due to this coupling between the drain and the well, cross section is determined by the well area (Musseau et a!., 1990). —In CMOS on epitaxial layer, the ion track may short-wire the substrate and a transistor drain of the same type. This effect may increase the collected charge by ion shunt (and lower the sensitivity threshold), but little influence on the cross section is expected.

—

Fig. 8. Upset mechanism of a CMOS cell.

through goes through the inverter the feedback to the path. supplyThis voltages latterand is inteone grated byand inverter theinduces input capacitance a voltage drop. of the If symmetrical this voltage drop is large enough to turn on the off-biased PMOS theDue restored. celltowill theupset. competition Otherwise between the initial directstate flowwill to the be supply lines and the integration mechanism in the feedback loop, SRAMs are very sensitive to the time constants of the transient current (Axness et a!., 1986; Weaver et a!., 1987; Cable et a!., 1986). This property

Charge collection and SEU mechanisms

(A)

(B) E

B

C

(C) E

~ i’-~~ I ~

B

I ~‘T,.LIZfl ______________

Buried ~

Substrate p—

Fig. 9. Bipolar T’FL

technology.

Depleted regions

(A)

159

C

E

j

has been largely used to harden memories by the use of resistive feedback paths (Andrews et a!., 1982; Diehl et a!., 1982). This influence of the collection time constants may

C

L1

/i\

Coupling

Physical structure. (B) Sensitive region.

B

unneling

(C) Collection length.

Several points that strongly depend on the test software must then be addressed:

—the identification of the sensitive region, —the error multiplicity, —the total duration of the perturbation.

also explain the relatively low order of multiplicity of simultaneous errors in SRAMs (Koga et a!., 1988; Song et a!., 1988). Charge collected by diffusion in adjacent cells, with longer time constants, will be less effective in upsetting these cells than charge promptly collected by funneling, Finally, asymmetrical results reported for different patterns (i.e. different sensitivity for “0” and “1”, despite a symmetrical electrical structure of the cell) may be due to the coupling of parasitic structures

can be done by using dedicated test programs to decorrelate the influence of the different parts of the device. Nevertheless the best way is to scan the circuit with a microbeam or a focused laser, to directly trigger the sensitive regions. Due to the propagation through the device and to the possibility of a latch in registers, the initial

between the hit cell and its neighbour. The cell

transient may induce several perturbations that could

symmetry is then broken and the threshold or the cross section of a node can be deeply modified by the

be detected after different delayed times. This effect and the error multiplicity will basically determine the

close parasitic structures of the adjacent cells.

value of the experimental cross section, that could be

4.4. Microprocessors and clocked devices Since 1981 many efforts have been made to determine the sensitivity of microprocessors to cosmic ions. Most of the first tests have been focused on registers of the devices where upsets could be induced. A new class of failures has been observed afterwards (May et a!., 1984). The ion could deviate the microprocessor from its standard program. The sensitivity of the microprocessor is then strongly dependant on the test program (Elder et a!., 1988). 4.4.1. Error mechanism. Basically a single event

A rough identification of the sensitive regions

overestimated if the errors could not be properly correlated to the real number of initial transients. 5 INTRINSIC SENSITIVITY OF MICROELECTRONIC TECHNOLOGIES

The sensitivity of a device depends both on its

induced transient is very similar to a noise spike, but

functionnality and on its technology. While the former dependence may be strongly related to the test program and may be unpredictable, the later can be roughly estimated from a basic analysis of the physical structure of the technology. 5.1. Theoretical derivation of the sensitivity

with a roughly constant shape. In a synchronous device an ion induced pulse will be taken as a logic signal if the three following conditions are

Assuming a simplified description of the sensitivity of a device by its threshold and its asymptotic cross

satisfied:

section, the “intrinsic” sensitivity of a technology can be simply estimated by a four step analysis:

—its amplitude is greater than the noise margins, —it

occurs during the active period of the clock,

—it occurs in an active region of the device, The sensitivity then increases with the integration (lower noise margins) and the clock frequency. The initial pulse is first reshaped by the logical cells struck by the ion. Then it propagates in the device

and may be multiplied. For example an initial transient in a stack pointer can perturbate several registers.

Finally the perturbation is detected when the registers

are upset or when it reaches the device output pins (Newberry, 1992).

—Physical description of the elementary structure, including parasitic elements. —Identification of the most sensitive element and the main charge collection mechanism. —Determination of the cross section. —Estimation of the sensitivity threshold.

Three typical technologies with different behaviours are choosen to illustrate the suggested method: bipolar TTL, CMOS on bulk and CMOS on SOI. The elementary structures (single bipolar transistor and CMOS inverters) are presented in Figs 9—11.

0. Musse~u

160

(A)

(B)

NMOS

(C)

PMOS

p— epilayer

Depleted regions

Funneling

Coupling

p+ substrate Fig. 10. CMOS/bulk technology. (A) Physical structure. (B)

(A)

Sensitive region. (C) Collection length.

(B) NMOS

(C)

PMOS

____

Depleted regions ——

____

____

7/7//////~/

__________

2~

Buried oxide

—

~///~

____

/2//~//~~

Collection length

Silicon substrate

Fig. 11. CMOS/SOI technology. (A) Physical structure. (B) Sensitive region. (C) Collection length.

To compare these technologies, we assume that their design rules are identical (1 pm interconnect lithography and 2pm minimum spacing between n + and p + regions). Furthermore the elementary structures are assumed to belong to devices with the same critical charge. Under this assumption the sensitivity threshold LETC, given by equation (9), is inversely proportional to the effective collection length Lee. 5.1.1. Bipolar TTL. In a bipolar transistor the most important parasitic element is the reverse biased collector—substrate junction, that isolates the transistors. Due to the presence of a heavily doped buried layer (to reduce collector resistivity), the depth of this junction is on the order of 10pm. For a 1 pm technology, its area may vary from 80 to 300 pm2

(determined by the transistor layout). In this structure the most effective collection is funneling, with a

controled by the reverse biased well-substrate junction. The funneling length is of the order of 10pm,2,and the sensitive area may vary from 50 to 150 pm depending on the efficiency of the coupling between drain and well). 5.1.3. CMOS/SO!. In CMOS on SOl technologies using a thin silicon film, transistors are isolated from

the substrate by a buried oxide layer that suppresses reverse biased junctions. The most sensitive element is the drain body junction of the off-biased MOS transistor. The collection length is strictly limited to the silicon thickness (0.1—1 pm, depending of the incidence angle) and the sensitive area is smaller than the gate area (0.5—5 pm2). 5.1.4. Comparison of technologies. Results of the comparison are summarized in Table 3. The intrinsic

transistor itself. The total collection length is then

sensitivity of the three technologies is plotted in Fig. 12. Each technology is characterized by a domain, determined by the extreme values of the

(~10 pm)

sensitive area of an elementary cell and by the

and the transistor thickness, 5.1.2. CMOS on bulk. The sensitivity of this kind of technology has been previously discussed and is

reciprocal of the collection length, equivalent to a LET threshold. This analysis clearly predicts different sensitivities for these technologies.

possible enhancement of the collection by the bipolar equal to the sum of the funneling length

bipolar TFL, CMOS/bulk and CMOS/SOI technologies Sensitive area (jim2) Collection length (jim)

Table 3. Comparison of the intrinsic sensitivity of

Mm.

Max.

Mm.

Max.

Bipolar TTL

80

300

10

20

CMOS/bulk

50

ISO

5

10

CMOS/SOI

0.5

5

0.1

Charge collection and SEU mechanisms IE+03

—

+

~Bipolar ~

E

IE+02

L111J

CMOS/bulk

IE+05

-

IE+04

-

161 CMOS/SOS

Bipolar x CMOS 0

A

+

A NMOS

+ A

O

E 1E+03

IE+O1

_________

1

I I

“2

I

CMOS/SOI i

~1E+OO!o

‘

~

1E—02

A

~ “LI4~!~ ~ ~

1

IE—OI

IE+OO

and

comparison

X 5

a —

t~0

e

+0

r4,

~ 1 Ei0O

Oo

a

1E+Ol ‘~lE-~O1

Relative sensitivity threshold Theoretical analysis

~

1Ax)~x5

‘4,

1

1E—.—O1

-

IE+02

~ 1E+Ol -

Fig. 12.

~, =

I

of the

°

x

i E—02

sensitivity of bipolar TfL, CMOS/bulk and CMOS/SOI

technologies.

0.1

5.2. Experimental data on SRAM

The accuracy of the previous analysis method can be estimated by comparison to experimental data. For this purpose we focus on available data on static RAMs in bipolar, CMOS and CMOS on insulator technologies. For such devices, with simple functionality, the test program has very little influence, that allows direct comparisons. Each device is simply characterized by its LET threshold [LETC, MeV/(mg/cm2)] and its asymptotic cross section per bit (o~,,cm2). Data come from annual lists of tested devices (Nichols et a!., 1983, 1984, 1987, 1989, 1991; Koga and Kolasinski, 1984; Harboe-Sorensen et a!., 1988), or from papers dedicated to CMOS/SOI devices (Davis eta!., 1985; Leray et a!., 1988; Ferlet-Cavrois et a!., 1992). All these data are presented in Fig. 13 (cross section per bit versus LET threshold). Despite the differences in device integration (data cover one

decade of evolution of microelectronic devices) this figure gives a global point of view on the sensitivity

of the three technologies and confirms the main trends of the simplified theoretical analysis.

6. CONCLUSION

In this review and discussion the close dependence

between single event upset sensitivity and charge collection mechanisms has been emphasized. It is

noticeable that, despite the huge number of transistom in modern complex devices, the global sensitivity

of a circuit is strongly influenced (or may be totally determined) by charge collection in its elementary structures. As transistors will be scaled down, to increase the device size and complexity, the noise margins (and the critical charge) will decrease. Furthermore the influence of parasitic elements, inherent to the technology will increase, and their importance may finally dominate. Carrier transport mechanisms

depend on coupling between neighbouring structures, and new mechanisms will probably increase the

I

IE—03

Fig. 13.

iiiiiiil

ii~iiiiI

1

10

i

i~’iiiiiI I

II

1002)

LET threshold MeV/(mg/cm Experimental comparison of the sensitivity

SRAMs in various technologies.

of

collected charge or the number of perturbated structures. Despite the significant reduction in device size,

the net effect of scaling down in some technologies could be a significant increase of device sensitivity. REFERENCES

Andrews J. L., Schroeder J. E., Gingerich B. L., Kolasinski W. A., Koga R. and Diehi S. E. (1982) Single event error immune CMOS RAM. IEEE Trans. Nsa!. Sci. NS-29, 2040. Axness C. L., Weaver H. T., Fu J. S., Koga R. and Kolasinski W. A. (1986) Mechanisms leading to single event upset. IEEE Trans. Nucl. Sci. NS-33, 1577.

Binder D., Smith E. C. and Holman A. B. (1975) Satellite anomalies from galactic cosmic rays. IEEE Trans. Nuci. Sd. NS-22, 2675.

Cable J. S., Carter J. R. and Witteles A. A. (1986) Verification of a SEU model for advanced 1 pm CMOS structures using heavy ions. IEEE Trans. NucI. Sci.

NS..33, A. 1586. Campbell B., Knudson A. R., McMorrow D., Anderson W., Roussos J., Espy S., Buchner S., Kang K., Kerns D. and Kerns S. (1989) Ion induced charge collection in GaAs MESFETs. IEEE Trans. Nuci. Sci. NS-36, 2292. Chern J. S., Yang P., Pattnaik P. and Seitchik J. A. (1986) Alpha particle induced charge transfer between closely spaced memory cells. IEEE Trans. Electron Devices ED-

33, 822.

Cnswell T. L., Measel P. R. and Wahlin K. L. (1984) Single event upset testing with relativistic heavy ions. IEEE Trans. Nucl. Sci. NS-31, 1559. Criswell T. L., Oberg D. L., Wert J. L., Measel P. R. and Wilson W. E. (1987) Measurement of SEUthresholds and cross sections at fixed incidence angles. IEEETrans. Nuc!. Sci. NS-34, 1316. Dall’Agnese P., Bafleur M., Sicard E., Buxo J. and Granadel P. (1986) Modélisation physique des défaillances

fonctionnelles des et circuits intégrés CMOS-VLSI en ambiance spatiale de rayonnement. Bordeaux, 274.

Davis G. E., Hite L. R., Blake T. G. W., Chen C. E., Lam H. W. and DeMoyer R. (1985) Transient radiation effects in SOI memories. IEEE Trans. Nucl, Sci. NS-32, 4432. Diehl S. E., Ochoa A., Dressendorfer P. V., Koga R. and Kolasinski W. A. (1982) Error analysis and prevention of cosmic ion induced soft errors in static CMOS RAMs. iEEE Trans. NucI. Sci. NS-29, 2032.

162

0. Mussu~u

Edmonds L. D. (1991) A simple estimate of funneling assisted charge collection. IEEE Trans. Nucl. Sci. NS-38, 828—833.

Elder J. H., Osborn J., Kolasinski W. A. and Koga R. (1988) A method for characterizing a microprocessor’s vulnerability to SEU. IEEE Trans. Nucl. Sci. NS-35, 1678. Ferlet-Cavrois V., Musseau 0., Leray J. L., CoIc Y. M., Lecarval G. and Guichard E. (1992) Comparison of the sensitivity to heavy ions of SRAM in different SIMOX technologies, presented at the SOS/SOI Conference, Jacksonville. Gilbert R. M., Ovrebo G. K. and Schifano J. (1985) Plasma screening of funnel fields. IEEE Trans. Nuci. Sd. NS-32, 4098. Grubin H. L., Kreskovsky J. P. and Weinberg B. C. (1984) Numerical studies of charge collection and funneling in silicon device. IEEE Trans. NucI. Sci. NS-31, 1161. Harboe-Sorensen R., Adams L. and Sanderson T. K. (1988) A summary of SEU test results using californium 252. IEEE Trans. Nucl, Sci. NS-35, 1622. Hauser J. R., Diehl-Nagle S. E., Knudson A. R., Campbell A. B., Stapor W. J. and Shapiro P. (1985) Ion track shunt effects in multi-junction structures. IEEE Trans. Nucl. Sci. NS-32, 4115. Hershberger S. and Hanson D. (1978) Electron News 24, 1. Horn K. M., Doyle B. L. and Sexton F. W. (1992) Nuclear microprobe imaging of single event upsets. IEEE Trans. NucI. Sci. 39, 7—12. Hsieh C. M., Murley P. C. and O’Brien R. R. (1981) Dynamics of charge collection from alpha particle tracks in integraded circuits. Proc. 19th Ann. In:. Reliability Phys. Symp., Orlando, Fla., p. 38. Hu C. (1982) Alpha particle induced field and enhanced collection of carriers. IEEE Electron Dev. Let:. EDL-3, 31. Klein C. A. (1966) Physics of semiconductors I. Phys. Soc. lap. 21, 307. Koga R. and Kolasinski W. A. (1984) Heavy ion induced single event upsets of microcircuits; a summary of the aerospace corporation test data. IEEE Trans. Nucl. Sci. NS-31, 1190. Koga R., Kolasinski W. A., Osborn J. V., Elder J. H. and Chitty R. (1988) SEU test techniques for 256k static RAMs and comparisons of upsets induced by heavy ions and protons. IEEE Trans. Nucl. Sci. NS-35, 1638. Kreskovsky J. P. and Grubin H. L. (1985) Simulation of charge collection in a multilayer device. IEEE Trans. Nucl. Sd. NS-32, 4140. Kreskovsky J. P. and Grubin H. L. (1986) Simulation of single radiation particle tracks in silicon and gallium arsenide semiconductor devices. SRA final report

R86—940004—F. Leray J. L., Dupont-Nivet E., Musseau 0., Cole V. M., Umbert A., Lalande P., Péré J. F., Auberton-Hervé A. J., Bruel M., Jaussaud C., Margail J., Giffard B., Truche R. and Martin F. (1988) From substrate to VLSI: Investigation of hardened SIMOX without epitaxy, for dose, dose rate and SEU phenomena. IEEE Trans. Nucl. Sci. NS-35, 1355. Martin R. C. and Ghoniem N. M. (1987) Monte Carlo simulation Coupled ion-electron transport in semiconductors. Phys. Stat. So!. A. 104, 743. May T. C. and Woods M. H. (1978) A new physical mechanism for soft errors in dynamic memories. In Conf. on reliability Physics, San Diego, Calif. May T. C., Scott G. L. and Meieran E. S. (1984) IEEE/IRPS 95, In:. Reliability Symp. Las Vegas, Calif. McLean F. B. and Oldham 1. R. (1982) Charge funneling in N- and P- type Si substrate. IEEE Trans. Nuci. Sci. NS29, 2018.

Messenger G. C. (1982) Collection of charge on junction

nodes from ion tracks. IEEE Trans. Nuc!. Sci. NS29, 2024. Musseau 0., Leray J. L., Coic and Patin Y. (1990) Single event upset sensitivity of a SRAM: an overview from testing procedures to device hardening. In Proc. ESA Electronic Component Con!. Noordwijk, pp. 351—356. Musseau 0., Leray J. L., Ferlet V., Umbert A., Cole Y. M. and Hesto P. (1991) Charge collection mechanisms in MOS/SOl transistors irradiated by energetic heavy ions. IEEE Trans. Nuci. Sci, NS-38, 1226. Newberry D. M. (1992) SEU in logic devices and systems; Considerations for analysis and test. Presented at the 1992 Single Event Effects Symposium, Los Angeles, Calif. Nichols D. K., Price W. E. and Malone C. J. (1983) Single event upset (SEU) ofsemiconductor devices—a summary of JPL test data. IEEE Trans. Nucl. Sci. NS-30, 4520. Nichols D. K., Price W. E., Malone C. J. and Smith L. S. (1984) A summary of JPL single event upset test data from May 1982, through January 1984. IEEE Trans. Nucl. Sci. NS-31, 1186. Nichols D. K., Smith L. S., Price W. E., Koga R. and Kolasinski W. A. (1987) Recent trends in parts SEU susceptibility from heavy ions. IEEE Trans. Nuci. Sci. NS-34, 1332. Nichols D. K., Smith L. S., Soli G. A., Koga R. and Kolasinski W. A. (1989) Latest trends in parts SEP susceptibility from heavy ions. IEEE Trans. Nuci. Sd. NS-36, 2388, Nichols D. K., Price W. E., Kolasinski W. A., Koga R., Pickel J. C., Blandford J. T. and Waskiewicz A. E. (1985) Trends in parts susceptibility to single event upset from heavy ions. IEEE Trans. Nucl. Sci. NS-32, 4189. Nichols D. K., Smith L. S., Schwartz H. R., Soil G., Watson K., Koga R., Cram W. R., Crawford K. B., Hansel S. J. and Lau D. D. (1991) Update on parts SEE susceptibility from heavy ions. IEEE Trans. Nuci. Sci. NS-38, 1529—1539. Patin Y., Humeau C. and Vidiella G. (1989) Etude expérimentale de Ia collection de charges dans des diodes pn irradiées par des ions lourds. In Radecs 89, La Grande Motte, France. Shanfield Z., Moriwaki M. M., Digby W. M., Srour J. R. and Campbell D. E (1985) Characteristics ofSEU current transients and collected charge in GaAs an Si devices. IEEE Trans. Nucl. Sd. NS-32, 4104. Shur M., Lee K., Choe R. and Berger E. (1986) Charge collection by drift during single particle upset. IEEE Trans. Nuci. Sci. NS-33, 1140. Song Y., Vu K. N., Cable J. S., Witteles A. A., Kolasinski W. A., Koga R., Elder J. H., Osborn J. V., Martin R. C. and Ghoniem N. M. (1988) Experimental and analytical

investigation of single event multiple bit upsets in polysilicon load 64k NMOS SRAMs. IEEE Trans. Nucl. Sci. NS-35, 1673. Stapor W. J., McDonald P. T., Knudson A. R., Campbell A. B. and Glagola B. G. (1988) Charge collection in silicon for ions of different energy but same linear energy transfer (LET). IEEE Trans. Nucl. Sci. NS-35, 1585. Takeda E., Takeuchi K., Yamasaki E., Toyabe 1., Ohshima K. and Itoh K. (1986) The scaling law of alpha particle induced soft errorsfor VLSI’s. In 1EDM-86, Los Angeles, Calif. p. 542. Wagner R. S., Bordes N., Bradley J. M., Maggiore C. J., Knudson A. R. and Campbell A. B.(1988) Alpha, boron, silicon and iron ion induced current transients in low capacitance silicon and GaAs diodes. IEEE Trans. Nuci. Sci. NS-35, 1578. Wallmark J. T. and Marcus S. M. (1962) Minimum size and maximum packing density of nonredundant semiconductor devices. In Proc. IRE, p. 286. Weaver H. T., Axness C. L., McBrayer J. D., Browning J. S., Fu J. S., Ochoa A. and Koga R. (1987) An SEU

Charge collection and SEU mechanisms tolerant memory cell derived from fundamental studies of SEU mechanisms in SRAM. IEEE Trans. Nuci. Sci. NS-34, 1281. Yaney D. S., Nelson J. T. and Vanskike L. L. (1979) Alpha-particle tracks in silicon and their effect on dynamic MOS RAM reliability. IEEE Trans. Electron Dev. ED-26, 10. Ziegler J. F. and Lanford W. A. (1979) Effect of cosmic rays on computer memories. Science 206, 776. Zoutendyk J. A., Edmonds L. D. and Smith 1. S. (1989)

RPC 43-If2—L

163

Characterization of multiple bit errors from single ion tracks in integrated circuits. IEEE Trans. Nuci. Sci. NS-36, 2267, Zoutendyk J. A., Schwartz H. R. and Nevill L. R. (1988) Lateral transport from heavy ion tracks in integrated circuit chips. IEEE Trans. Nuci. Sci. NS-35, 1644. Zoutendyk J. A., Schwartz H. R., Watson R. K., Hasnain Z. and Nevill L. R. (1987) Single event upset (SEU) in a DRAM with on-chip error correction. IEEE Trans. Nuci. Sci. NS-34, 1310.