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Cleaning technology for improved gate oxide integrity
MicroelectronicEngineering22 (1993)21-28 Elsevier
21
Cleaning technology for improved gate oxide integrity M. Meuris, S. Verhaverbeke, P.W. Mertens, IL F. Schmidt, MM. Heyns, M. Kubotal, A. Philipossian2’, K. Dillenbeck8, D. Grilf4, A. Schneg& and R. de Blanks IMEC, Kapeldreef 75, B-3001 Leuven, Belgium ISony Corp., Asahi-cho,Atsugi-shi,Kanagawa-ken,Japan ZDigitalEquipmentCorporation,77 Reed Road, H&on, MA 01749, USA 3As?&zndChemical Inc., P-0. Box 2219, Columbus,Ohio43216, USA 4Wacker_Chemitronic, P-0. Box 1140, D-8263 Burghausen, Germany SASMInternatbnal, Rembrandtlaan2A, 3723 BJ Bilthoven,The Netherlands
The effect of metal contamination and silicon surface defects on the gate oxide yield is investigated. The characteristics of various cleaning procedures are studied and correlated with the integrity of thin gate oxides. The standard wet cleaning recipe is optimized and a new cleaning strategy is proposed. Selective contamination experiments in chemicals are used to investigate the effect of small amounts of metal con taminants on the gate oxide integrity. HFlast processes are investigated and a new wet cleaning strategy is proposed. 1 - INTRODUCTION Metal contamination, particles and silicon surface roughness are important causes of defect-related gate-oxide breakdown in MOS-technology. In the recent past a lot of research work has been directed towards these topics. The use of cleaner chemicals with fewer metal impurities has improved the quality of the cleaning procedures. The origin and effects of Sisurface roughness on the gate oxide breakdown and MOS-device characteristics have been demonstrated12 and considerable progress has been ma& in understanding and controlling this effect by improving the wafer characteristics and the cleaning procedures. This paper deals with the cleaning technology topics concerning the cleaning recipies itself. For the RCA cleaning procedure the important parameters are reviewed and the importance of the quality of the chemicals used is discussed. Finally, a new cleaning concept will be presented.
* presentaddress : Intel Corporation, Santa Clara, CA 0167-9317/93/$06.00
0 1993 - Elsevier Science Publishers B.V. All rights reserved.
22
M. Mew-is et al. I Improved gate oxide integrily
2 - EXPERIMENTAL
TECHNIQUES
The wafers used were 400> silicon wafers with a 125 mm diameter. The RCAcleaning treatment was performed in quartz containers and consisted of a SC1 step followed by a SC2 step. The SCl-step (NH4OH/H202/H20) and SC2-step (HCl/H202/H20) were both performed at 75°C for 10 min. The metallic contamination present on the wafer surface after cleaning or in the oxide after thermal oxidation was evaluated using the combination of vapour phase decomposition (VPD), droplet surface etching @SE) with a 0.5% HF, 1% H202, 98.5% Hz0 solution and total reflectance X-ray fluorescence (TXRF)s. Metals which can not be detected by TXRF were analysed using poly-encapsulated SIMS. Si-surface roughness was measured with lightscattering or Atomic Force Microscopy (AFM). On the oxidized wafers poly-Si gate capacitors were fabricated for electrical characterization. The oxidation was typically pexformed in dry 02 (no chlorine added) at 9OOOCin a double-walled furnace tube to a thickness of 15 nm. The transition between defect-related and intrinsic breakdown events occurs typically around 12 MV/cm in a Weibull plot. The breakdown yield of the capacitors is, therefore, defined as the percentage of capacitors surviving a field of 12 MV/cm in a ramped voltage test (or EBD test). 3 - THE SCl-CLEAN In previous studies43 the NH4OH/I-I~~20 ratio in the SCl-clean was optimised. It was found that by varying the ratio from 0.2/l/5 to l/1/5 the particle removal efficiency after a 10 min. immersion time remained equal. The metal contamination after a subsequent SC2 cleaning (HCl/H202/H20 mixture) was also found to be equal. However, large differences were found in the yield and a cleaning with the 0.25: 1:5 SC- 1 mixture resulted in much better gate oxide integrity than the 1: 1:5 mixture. This was correlated with the Si-surface roughness as measured by AFM where it was found that the 1:1:5 mixture roughened the silicon surface much more than the 0.25:1:5 mixture did. So it was found that silicon surface roughness was a major parameter affecting gate oxide integrity.
z> i L
0.8
0.6
Ac A
OA IT3 0
0,
z* ._
0.4
L
z
0.2
0
0.25/1/s
0
0.05/1/s
A
001/i/5
Fig. 1 : Particle removal ejficiency as a function of etched SiO2 thickness for mixtures with various etch rates for thermal SiO2 (0.25: 0.2 nmlmin; 0.05: 0.1 nmfmin; 0.01: 0.05 nmlmin)
M. Meuris et al. / improved gate oxide integrity
23
These observations can be explained by the oxidising and etching which occurs in the SCl-solution4. When silicon is exposed to the SCl-mixture, the peroxide will oxidize the silicon surface while the ammonia will etch this chemical oxide away; i.e. a chemical oxide layer will continually form and dissolve as a result of the compensating effect of the two chemical components. This slowly etches the silicon. A high etch rate (obtained by a large N&OH concentration) will increase the particle removal efficiency by undercutting the particles, but causes a larger surface roughening during a 10 min clean Consequently, one has to find an optimum between particle removal effkiency and silicon surface roughening. In OUT case this optimum was found when 2 nm of thermal Si@ is etched. This point can be obtained by either changing the ammonia concentration, the cleaning time or the temperature of the cleaning mixture. Because most experiments are always done at a fixed time, the question arrises if the particle removal efficiency is dependent on the etch speed or on the etched depth of the cleaning mixture. In fig. 1 the particle removal efficiency is plotted as a function of etched Si@ during a SC1 cleaning for 3 different etch speeds. One can observe that the the only parameter affecting particle removal is the etch depth, independent from a different etch speed of the mixture. Any overetching (i.e. etching of more than 2 nm SQ) does not improve the particle removal efficiency further but increases the Si-surface roughness and, thereby, results in a degraded gate oxide integrity. 4 - QUALITY OF CHEMICALS The metal content of the chemicals and the metal contamination on the silicon wafer after the SCl-clean were shown to have a linear correlation3. After the SCZclean no correlation between the metal content of the chemicals used in the SC1 and SC&step and the final metal contamination on the wafers could be detected. It was found that the metal contamination on the wafers after a complete RCA-clean using ULSI-grade chemicals from various vendors and with different metal content does not vary significantly. However, clear differences in the gate oxide integrity were observed on the wafers which were RCA-cleaned in the various chemicals. The yield was found to correlate with the Si-surface roughness measured after the cleaning, i.e. the chemicals of certain vendors increased the Si-surface roughness during cleaning much stronger than the chemicals of other vendor&. This increase in Si-surface roughness resulted in a lower gate oxide yield.
As was illustrated above, especially the SC1 step can etch the silicon and, therefore, can possibly roughen the Si-surface. The WOH in the SC1 step has a relatively high etch rate for silicon. Hfi which is oxidising the silicon acts as an inhibitor of this silicon etching by the formation of a thin chemical oxide. This chemical oxide is only slowly etched by the SCl-solution. Therefore, the amount of Hz02 must always be sufficient to protect the silicon surface. However, the Hz02 concentration reduces as a function of time due to the decomposition reaction 2H2@ -> 2 Hz0 + 02. Recently it was shown6 that the decomposition of Hz02 is strongly dependent on the concentration of Fe in the SCl-solution. If decomposition of Hz02 is faster than the evaporation of NH3, the NH4OH/H202 ratiocanreach a level after a certain time where the protection of the silicon by the Hfi is not sufficient anymore and direct etching of silicon can occur, which results in roughening. Also the gas formation during the decomposition itself can be responsible for surface roughening. For determining the decomposition rates, a gasometric technique was developed that measures the amount of @ generated through the decomposition of Hz02 as a function of time. A special tool was constructed to avoid errors from the evaporation of water and ammonia. Since the decomposition rate was found to be timedependent7 in a SC1 solution, all measurements were carried out until a constant decomposition rate was achieved. Different grades of H& (30 w-% f 2) were used.
24
M. Meuris et al. I Improved gate oxide integrity
0
20
10 spiking
level
30
(w-ppb)
Fig. 2 : Dependence of the decomposition rate of the ultra-pure Hz02 ‘A” at 70°C on the Fe and Cu contumikation level. The Hz& labeled “A” is an ultrapure one with typical metal levels between co.05 to 0.4 ppb.
Hz@ labeled “B” has typical metal contamination levels between
:.
: GtWLel(t=3-13min)
aseUe2(t=15-25min)
casette 3 (t = 27 - 37 min)
Fig. 3 : Light point defects (CENSOR ANS-100 : LSE 0 0.10 - 0.19 pm) after treatment in a I w-ppb Fe spiked SC1 solution (0.25/I/5 at 70°C). The different wafers were taken out from consecutively cleaned batches (t=age of the bath since mixing of the components).
M. Mew-iset al. I Improvedgate oxide integrity
25
The decomposition rate of the three types of Hfi is shown in figure 4. In this figure it is clearly seen that the stability of Hz@ “C” is similar to that of the ultra-pure “A” because of the very effective stabilizer. However, when Nl!QOH is added it seems that the stabilizer becomes inactive and rapid decomposition occurs for Hz02 “C”. Increasing the Nl%tOH concentration and/or the temperature of the SCl-bath were both found to increase the decomposition rate and, therefore, increase the risk for strong Si-surface roughening. From these results it can be concluded that the pre-treatment of the wafers before SC1 (in terms of roughness) and the SC1 itself (in terms of decomposition and metal outplating) is much more important than the post-treatment by X2. Metals deposited onto the wafer in the SCl-step are effectively removed by the SC2 step. Despite this possibility to remove these metals, they already contributed to the roughening of the Si-surface by increasing the decomposition of the Hz% in the SCl-step. This roughening is an important cause of defect-related breakdown of oxides grown on these silicon surfaces. Therefore, ultra-clean chemicals are needed in the complete cleaning sequence.
0
A
C
grade of peroxide
Fig. 4 : Decomposition rate of three different grades of Hz02 and their SC1 mixtures (0.05IlL5) at 70 T.
5 - A NEW WET CLEANING CONCEPT In fig. 1 it was aheady illustrated that the particle removal during the SC1 cleaning step is independent on the thermal oxide etch speed (determined by the NH4OH concentration and the temperature of the bath) and reaches a constant value as soon as 1.5 to 2 nm of thermal oxide is removed. On the basis of this knowledge a new cleaning concept is proposed. In the SC1 mixture particles are removed by the continuous oxidising effect of the H202 and dissolution or etching effect of the NlQOH. Due to this action, the particles are undercut and lift off. In the IMEC-clean concept the oxidising and etching action of the silicon surface is separated. This is summan‘red in table I. ln step 1 the organic contamination is removed and a thin oxide is grown. In step 2 this chemical oxide is removed. The total etch depth of the cleaning procedure should be sufficient to remove the particles. The advantage of separating the cleaning in two steps is that the formation of the oxide layer is a self-limiting process, resulting in an easier control of the Sisurface roughness. For step 1 a H$304/H2@ mixture can be used Also ozonated mixtures are
26
M. Meuris et al. I Improved gate oxide integrity
Table I : Concept of the IMEC-clean. Step I : growth of about I.5 nm chemical oxide; Step 2 : removal of the oxide; drying procedure; Optionally Step 3 : easier drying due to the growth of a hydrophilic Si surface. Step
1
oxide
Step 2 growth
l
H2SWH202
l
H2SO4/O3
l
H2OlO3
l
uv-03
oxide
l
(Step
3)
optional
removal
wet DHF
l
lHFvapour+
drying
chemical oxide
l
IPA vapour
growth
l
hot DI-water
l
spin dry
l
N2 blow
rinsing
Table II: Metal contamination (in 1010 at.cm-2.2; Detection Limit (DL) = 0.1 1010 at.cme2) afrer IMEC vs. RCA+HF clean. The indication Sx(IMEC)+HF and Sx(RCA)+HF means that respectively the IMEC and the RCA-clean were repeated 5 times and followed by a HF-dip.
cleaning
treatment
original
metal level +
Ca
Fe
15
1
2
1
0.3 0.8
CDL 0.5
0.7 4.9
CDL 0.3
CDL CDL
cu
Zn
1
IMEC RCA+HF
0.7 2.5 I
I CDL 4.5
Sx(IMEC) + HF Sx(RCA) + HF
Table III: Yield of gate oxide capacitors grown on EPI wafers (0.15 cm2; breakdownfield > 12 MVlcm). Afrer the cleans all wafers went to the same HF-last, rinsing and drying procedure and underwent the same proceessing. The indication Sx(IMEC)+HF and Sx(RCA)+HF means that respectively the IMEC and the RCA-clean were repeated 5 times ana' followed by a HFdip. cleaning
treatment
Yield
[%I 82+4 80+5
IMEC RCA+HF
I Sx(IMEC) + HF Sx(RCA) + HF
I
68f 52f
8 15
M. Meuris et al. / Improved gate oxide integrity
27
possible such as H2SO4/O3, H2O/O3* or UV-03. The only requirement of step 1 is to grow an oxide of a minimal thickness (about 1.5 nm). The chemical oxide of a H2S04/H202 mixture was reported to be around 1.3 nm9 and can be used for this purpose. In step 2 this chemical oxide is removed. This step has to be optimized in such a way that the Si-surface is completely passivated (high contact angle), that the silicon surface is not roughened and that a high selectivity versus thermal or deposited oxide layers is obtained. Obtaining such a HF-last process is discussed in mf.l0,11,12. After the final rinsing the wafers have to be dried. When a good drying technique for hydrophobic surfaces is available no pretreatment of the silicon surface is required. In the other case a very clean chemical oxide can be grown using e.g. ozonated D&water or an Hz% based mixture. This step, however, has the potential danger of introducing Si-surface roughness and/or metallic contamination. Using the sequence of 2 min. H$O4/H202 (4/l at 9O’C) followed by 2 min. HF (0.5% I-IF/ 0.1% IPA in DI water at room temperature) in a wet bench it was illustrated that the typical particle removal efficiency of the IMBC clean is as good as the performance obtained with the best optimized RCA-clean. In these experiments ail chemicals were of a
28
M. Meuris et al. I Improved gate oxide integrity
3. M. Meuris, M. Heyns, W. Ktiper, S. Verhaverbeke
and A. Philipossian, Proceedings of the 178th ECS Meeting, Washington DC (1991) p.488 and A. Philipossian, 4. M. Meuris, M.M. Heyns, P.W. Mertens, S. Verhaverbeke Microcontamination 1@5 (1992) p.3 1 P.W. Mertens, M>M> Heyns, L. Hellemans, Y> 5. M. Meuris, S. Verhaverbeke, Bruynseraede, and A. Philipossian, Jpn. J. Appl. Phys. Vol. 31 (1992) pp. L1514L1517. of the 1992 Semiconductor Pure Water and 6. Y. Oshida in “Chemical Proceedings Chemicals Conference”, Ed. M.K. Balazs, 1992, p.63 M. Kubota, M.M. Heyns 7. H.F. Schmidt, M. Meuris, P.W. Mertens, S. Verhaverbeke, and K. Dillenbeck :“H202 quality, the key towards successful wet chemical cleaning”, Chemicals session of the Institute of Environmental Science Annual Technical Meeting, Las Vegas, Nevada, May 2-7,1993, to be published in the proceedings 8. T. Isagawa, T. Imaoka, M. Kogure, H. Shimada and T. Ohmi, Proc. IES Meeting, May 1992, p.438 9. S. Aoyama, Y. Nakagawa and T. Ohmi, pmceedings of Solid State Device Manufacturing conference SSDM’92, August 26-28, Tsukuba, Japan, p. 126 10. S. Verhaverbeke, M. Meuris, M. Schaekers, L. Haspeslagh, P. Mertens, M.M. Heyns, R. De Blank and A. Philipossian, proceedings of 1992 Symposium on VLSI Technology, Digest of Technical Papers p.22 11. J.L. Alay, S. Verhaverbeke, W. Vandervorst and M.M. Heyns, proceedings of Solid State Device Manufacturing conference SSDM’92, August 26-28, Tsukuba, Japan, p. 123 12. S. Verhaverbeke, M. Iacovacci, P. Mertens, M. Meuris, M Heyns, R. Schreutelkamp, K. Maex, J. Alay, W. Vandervorst, R. de Blank, M. Kubota and A. Philipossian in “Proceedings of the Int’l Electron Devices Meeting (IEDM) 1992 IEDM”, San Francisco, Dec. 1992, p. 637
21
Cleaning technology for improved gate oxide integrity M. Meuris, S. Verhaverbeke, P.W. Mertens, IL F. Schmidt, MM. Heyns, M. Kubotal, A. Philipossian2’, K. Dillenbeck8, D. Grilf4, A. Schneg& and R. de Blanks IMEC, Kapeldreef 75, B-3001 Leuven, Belgium ISony Corp., Asahi-cho,Atsugi-shi,Kanagawa-ken,Japan ZDigitalEquipmentCorporation,77 Reed Road, H&on, MA 01749, USA 3As?&zndChemical Inc., P-0. Box 2219, Columbus,Ohio43216, USA 4Wacker_Chemitronic, P-0. Box 1140, D-8263 Burghausen, Germany SASMInternatbnal, Rembrandtlaan2A, 3723 BJ Bilthoven,The Netherlands
The effect of metal contamination and silicon surface defects on the gate oxide yield is investigated. The characteristics of various cleaning procedures are studied and correlated with the integrity of thin gate oxides. The standard wet cleaning recipe is optimized and a new cleaning strategy is proposed. Selective contamination experiments in chemicals are used to investigate the effect of small amounts of metal con taminants on the gate oxide integrity. HFlast processes are investigated and a new wet cleaning strategy is proposed. 1 - INTRODUCTION Metal contamination, particles and silicon surface roughness are important causes of defect-related gate-oxide breakdown in MOS-technology. In the recent past a lot of research work has been directed towards these topics. The use of cleaner chemicals with fewer metal impurities has improved the quality of the cleaning procedures. The origin and effects of Sisurface roughness on the gate oxide breakdown and MOS-device characteristics have been demonstrated12 and considerable progress has been ma& in understanding and controlling this effect by improving the wafer characteristics and the cleaning procedures. This paper deals with the cleaning technology topics concerning the cleaning recipies itself. For the RCA cleaning procedure the important parameters are reviewed and the importance of the quality of the chemicals used is discussed. Finally, a new cleaning concept will be presented.
* presentaddress : Intel Corporation, Santa Clara, CA 0167-9317/93/$06.00
0 1993 - Elsevier Science Publishers B.V. All rights reserved.
22
M. Mew-is et al. I Improved gate oxide integrily
2 - EXPERIMENTAL
TECHNIQUES
The wafers used were 400> silicon wafers with a 125 mm diameter. The RCAcleaning treatment was performed in quartz containers and consisted of a SC1 step followed by a SC2 step. The SCl-step (NH4OH/H202/H20) and SC2-step (HCl/H202/H20) were both performed at 75°C for 10 min. The metallic contamination present on the wafer surface after cleaning or in the oxide after thermal oxidation was evaluated using the combination of vapour phase decomposition (VPD), droplet surface etching @SE) with a 0.5% HF, 1% H202, 98.5% Hz0 solution and total reflectance X-ray fluorescence (TXRF)s. Metals which can not be detected by TXRF were analysed using poly-encapsulated SIMS. Si-surface roughness was measured with lightscattering or Atomic Force Microscopy (AFM). On the oxidized wafers poly-Si gate capacitors were fabricated for electrical characterization. The oxidation was typically pexformed in dry 02 (no chlorine added) at 9OOOCin a double-walled furnace tube to a thickness of 15 nm. The transition between defect-related and intrinsic breakdown events occurs typically around 12 MV/cm in a Weibull plot. The breakdown yield of the capacitors is, therefore, defined as the percentage of capacitors surviving a field of 12 MV/cm in a ramped voltage test (or EBD test). 3 - THE SCl-CLEAN In previous studies43 the NH4OH/I-I~~20 ratio in the SCl-clean was optimised. It was found that by varying the ratio from 0.2/l/5 to l/1/5 the particle removal efficiency after a 10 min. immersion time remained equal. The metal contamination after a subsequent SC2 cleaning (HCl/H202/H20 mixture) was also found to be equal. However, large differences were found in the yield and a cleaning with the 0.25: 1:5 SC- 1 mixture resulted in much better gate oxide integrity than the 1: 1:5 mixture. This was correlated with the Si-surface roughness as measured by AFM where it was found that the 1:1:5 mixture roughened the silicon surface much more than the 0.25:1:5 mixture did. So it was found that silicon surface roughness was a major parameter affecting gate oxide integrity.
z> i L
0.8
0.6
Ac A
OA IT3 0
0,
z* ._
0.4
L
z
0.2
0
0.25/1/s
0
0.05/1/s
A
001/i/5
Fig. 1 : Particle removal ejficiency as a function of etched SiO2 thickness for mixtures with various etch rates for thermal SiO2 (0.25: 0.2 nmlmin; 0.05: 0.1 nmfmin; 0.01: 0.05 nmlmin)
M. Meuris et al. / improved gate oxide integrity
23
These observations can be explained by the oxidising and etching which occurs in the SCl-solution4. When silicon is exposed to the SCl-mixture, the peroxide will oxidize the silicon surface while the ammonia will etch this chemical oxide away; i.e. a chemical oxide layer will continually form and dissolve as a result of the compensating effect of the two chemical components. This slowly etches the silicon. A high etch rate (obtained by a large N&OH concentration) will increase the particle removal efficiency by undercutting the particles, but causes a larger surface roughening during a 10 min clean Consequently, one has to find an optimum between particle removal effkiency and silicon surface roughening. In OUT case this optimum was found when 2 nm of thermal Si@ is etched. This point can be obtained by either changing the ammonia concentration, the cleaning time or the temperature of the cleaning mixture. Because most experiments are always done at a fixed time, the question arrises if the particle removal efficiency is dependent on the etch speed or on the etched depth of the cleaning mixture. In fig. 1 the particle removal efficiency is plotted as a function of etched Si@ during a SC1 cleaning for 3 different etch speeds. One can observe that the the only parameter affecting particle removal is the etch depth, independent from a different etch speed of the mixture. Any overetching (i.e. etching of more than 2 nm SQ) does not improve the particle removal efficiency further but increases the Si-surface roughness and, thereby, results in a degraded gate oxide integrity. 4 - QUALITY OF CHEMICALS The metal content of the chemicals and the metal contamination on the silicon wafer after the SCl-clean were shown to have a linear correlation3. After the SCZclean no correlation between the metal content of the chemicals used in the SC1 and SC&step and the final metal contamination on the wafers could be detected. It was found that the metal contamination on the wafers after a complete RCA-clean using ULSI-grade chemicals from various vendors and with different metal content does not vary significantly. However, clear differences in the gate oxide integrity were observed on the wafers which were RCA-cleaned in the various chemicals. The yield was found to correlate with the Si-surface roughness measured after the cleaning, i.e. the chemicals of certain vendors increased the Si-surface roughness during cleaning much stronger than the chemicals of other vendor&. This increase in Si-surface roughness resulted in a lower gate oxide yield.
As was illustrated above, especially the SC1 step can etch the silicon and, therefore, can possibly roughen the Si-surface. The WOH in the SC1 step has a relatively high etch rate for silicon. Hfi which is oxidising the silicon acts as an inhibitor of this silicon etching by the formation of a thin chemical oxide. This chemical oxide is only slowly etched by the SCl-solution. Therefore, the amount of Hz02 must always be sufficient to protect the silicon surface. However, the Hz02 concentration reduces as a function of time due to the decomposition reaction 2H2@ -> 2 Hz0 + 02. Recently it was shown6 that the decomposition of Hz02 is strongly dependent on the concentration of Fe in the SCl-solution. If decomposition of Hz02 is faster than the evaporation of NH3, the NH4OH/H202 ratiocanreach a level after a certain time where the protection of the silicon by the Hfi is not sufficient anymore and direct etching of silicon can occur, which results in roughening. Also the gas formation during the decomposition itself can be responsible for surface roughening. For determining the decomposition rates, a gasometric technique was developed that measures the amount of @ generated through the decomposition of Hz02 as a function of time. A special tool was constructed to avoid errors from the evaporation of water and ammonia. Since the decomposition rate was found to be timedependent7 in a SC1 solution, all measurements were carried out until a constant decomposition rate was achieved. Different grades of H& (30 w-% f 2) were used.
24
M. Meuris et al. I Improved gate oxide integrity
0
20
10 spiking
level
30
(w-ppb)
Fig. 2 : Dependence of the decomposition rate of the ultra-pure Hz02 ‘A” at 70°C on the Fe and Cu contumikation level. The Hz& labeled “A” is an ultrapure one with typical metal levels between co.05 to 0.4 ppb.
Hz@ labeled “B” has typical metal contamination levels between
:.
: GtWLel(t=3-13min)
aseUe2(t=15-25min)
casette 3 (t = 27 - 37 min)
Fig. 3 : Light point defects (CENSOR ANS-100 : LSE 0 0.10 - 0.19 pm) after treatment in a I w-ppb Fe spiked SC1 solution (0.25/I/5 at 70°C). The different wafers were taken out from consecutively cleaned batches (t=age of the bath since mixing of the components).
M. Mew-iset al. I Improvedgate oxide integrity
25
The decomposition rate of the three types of Hfi is shown in figure 4. In this figure it is clearly seen that the stability of Hz@ “C” is similar to that of the ultra-pure “A” because of the very effective stabilizer. However, when Nl!QOH is added it seems that the stabilizer becomes inactive and rapid decomposition occurs for Hz02 “C”. Increasing the Nl%tOH concentration and/or the temperature of the SCl-bath were both found to increase the decomposition rate and, therefore, increase the risk for strong Si-surface roughening. From these results it can be concluded that the pre-treatment of the wafers before SC1 (in terms of roughness) and the SC1 itself (in terms of decomposition and metal outplating) is much more important than the post-treatment by X2. Metals deposited onto the wafer in the SCl-step are effectively removed by the SC2 step. Despite this possibility to remove these metals, they already contributed to the roughening of the Si-surface by increasing the decomposition of the Hz% in the SCl-step. This roughening is an important cause of defect-related breakdown of oxides grown on these silicon surfaces. Therefore, ultra-clean chemicals are needed in the complete cleaning sequence.
0
A
C
grade of peroxide
Fig. 4 : Decomposition rate of three different grades of Hz02 and their SC1 mixtures (0.05IlL5) at 70 T.
5 - A NEW WET CLEANING CONCEPT In fig. 1 it was aheady illustrated that the particle removal during the SC1 cleaning step is independent on the thermal oxide etch speed (determined by the NH4OH concentration and the temperature of the bath) and reaches a constant value as soon as 1.5 to 2 nm of thermal oxide is removed. On the basis of this knowledge a new cleaning concept is proposed. In the SC1 mixture particles are removed by the continuous oxidising effect of the H202 and dissolution or etching effect of the NlQOH. Due to this action, the particles are undercut and lift off. In the IMEC-clean concept the oxidising and etching action of the silicon surface is separated. This is summan‘red in table I. ln step 1 the organic contamination is removed and a thin oxide is grown. In step 2 this chemical oxide is removed. The total etch depth of the cleaning procedure should be sufficient to remove the particles. The advantage of separating the cleaning in two steps is that the formation of the oxide layer is a self-limiting process, resulting in an easier control of the Sisurface roughness. For step 1 a H$304/H2@ mixture can be used Also ozonated mixtures are
26
M. Meuris et al. I Improved gate oxide integrity
Table I : Concept of the IMEC-clean. Step I : growth of about I.5 nm chemical oxide; Step 2 : removal of the oxide; drying procedure; Optionally Step 3 : easier drying due to the growth of a hydrophilic Si surface. Step
1
oxide
Step 2 growth
l
H2SWH202
l
H2SO4/O3
l
H2OlO3
l
uv-03
oxide
l
(Step
3)
optional
removal
wet DHF
l
lHFvapour+
drying
chemical oxide
l
IPA vapour
growth
l
hot DI-water
l
spin dry
l
N2 blow
rinsing
Table II: Metal contamination (in 1010 at.cm-2.2; Detection Limit (DL) = 0.1 1010 at.cme2) afrer IMEC vs. RCA+HF clean. The indication Sx(IMEC)+HF and Sx(RCA)+HF means that respectively the IMEC and the RCA-clean were repeated 5 times and followed by a HF-dip.
cleaning
treatment
original
metal level +
Ca
Fe
15
1
2
1
0.3 0.8
CDL 0.5
0.7 4.9
CDL 0.3
CDL CDL
cu
Zn
1
IMEC RCA+HF
0.7 2.5 I
I CDL 4.5
Sx(IMEC) + HF Sx(RCA) + HF
Table III: Yield of gate oxide capacitors grown on EPI wafers (0.15 cm2; breakdownfield > 12 MVlcm). Afrer the cleans all wafers went to the same HF-last, rinsing and drying procedure and underwent the same proceessing. The indication Sx(IMEC)+HF and Sx(RCA)+HF means that respectively the IMEC and the RCA-clean were repeated 5 times ana' followed by a HFdip. cleaning
treatment
Yield
[%I 82+4 80+5
IMEC RCA+HF
I Sx(IMEC) + HF Sx(RCA) + HF
I
68f 52f
8 15
M. Meuris et al. / Improved gate oxide integrity
27
possible such as H2SO4/O3, H2O/O3* or UV-03. The only requirement of step 1 is to grow an oxide of a minimal thickness (about 1.5 nm). The chemical oxide of a H2S04/H202 mixture was reported to be around 1.3 nm9 and can be used for this purpose. In step 2 this chemical oxide is removed. This step has to be optimized in such a way that the Si-surface is completely passivated (high contact angle), that the silicon surface is not roughened and that a high selectivity versus thermal or deposited oxide layers is obtained. Obtaining such a HF-last process is discussed in mf.l0,11,12. After the final rinsing the wafers have to be dried. When a good drying technique for hydrophobic surfaces is available no pretreatment of the silicon surface is required. In the other case a very clean chemical oxide can be grown using e.g. ozonated D&water or an Hz% based mixture. This step, however, has the potential danger of introducing Si-surface roughness and/or metallic contamination. Using the sequence of 2 min. H$O4/H202 (4/l at 9O’C) followed by 2 min. HF (0.5% I-IF/ 0.1% IPA in DI water at room temperature) in a wet bench it was illustrated that the typical particle removal efficiency of the IMBC clean is as good as the performance obtained with the best optimized RCA-clean. In these experiments ail chemicals were of a
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M. Meuris et al. I Improved gate oxide integrity
3. M. Meuris, M. Heyns, W. Ktiper, S. Verhaverbeke
and A. Philipossian, Proceedings of the 178th ECS Meeting, Washington DC (1991) p.488 and A. Philipossian, 4. M. Meuris, M.M. Heyns, P.W. Mertens, S. Verhaverbeke Microcontamination 1@5 (1992) p.3 1 P.W. Mertens, M>M> Heyns, L. Hellemans, Y> 5. M. Meuris, S. Verhaverbeke, Bruynseraede, and A. Philipossian, Jpn. J. Appl. Phys. Vol. 31 (1992) pp. L1514L1517. of the 1992 Semiconductor Pure Water and 6. Y. Oshida in “Chemical Proceedings Chemicals Conference”, Ed. M.K. Balazs, 1992, p.63 M. Kubota, M.M. Heyns 7. H.F. Schmidt, M. Meuris, P.W. Mertens, S. Verhaverbeke, and K. Dillenbeck :“H202 quality, the key towards successful wet chemical cleaning”, Chemicals session of the Institute of Environmental Science Annual Technical Meeting, Las Vegas, Nevada, May 2-7,1993, to be published in the proceedings 8. T. Isagawa, T. Imaoka, M. Kogure, H. Shimada and T. Ohmi, Proc. IES Meeting, May 1992, p.438 9. S. Aoyama, Y. Nakagawa and T. Ohmi, pmceedings of Solid State Device Manufacturing conference SSDM’92, August 26-28, Tsukuba, Japan, p. 126 10. S. Verhaverbeke, M. Meuris, M. Schaekers, L. Haspeslagh, P. Mertens, M.M. Heyns, R. De Blank and A. Philipossian, proceedings of 1992 Symposium on VLSI Technology, Digest of Technical Papers p.22 11. J.L. Alay, S. Verhaverbeke, W. Vandervorst and M.M. Heyns, proceedings of Solid State Device Manufacturing conference SSDM’92, August 26-28, Tsukuba, Japan, p. 123 12. S. Verhaverbeke, M. Iacovacci, P. Mertens, M. Meuris, M Heyns, R. Schreutelkamp, K. Maex, J. Alay, W. Vandervorst, R. de Blank, M. Kubota and A. Philipossian in “Proceedings of the Int’l Electron Devices Meeting (IEDM) 1992 IEDM”, San Francisco, Dec. 1992, p. 637