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CLEO lights way to optical ICs
World Abstracts on Microelectronics and Reliability
393
conductor parts manufactured in house strains resources, slows firms' plans to enter the merchant market,
two may, at first, seem superfluous, the technologies used to serve the different applications are diverging.
Microeleetronics and power. ALAN FOSTER. Electronics and Power 459 (June 1984). The field of power electronics contains two distinct application areas--in electronic power and electrical power. Although drawing a distinction between the
CLEO lights way to optical ICs. TERRY FELDT. Electronics 102 (28 June 1984). Laser conference spotlights devices for optical signal processing, but practical monolithic optical circuits are still a long way off.
5. M I C R O E L E C T R O N I C S - - D E S I G N
Electrical characteristics of large scale integration (LSI) MOSFETs at very high temperatures. Part I; theory. F. SHOUCAIR,W. HWANG and P. JAIN. Microelectron. Reliab. 24, 465 (1984). A systematic investigation of the effects of high temperature (27°C to 300°C) on long N and P channel MOS transistors suitable for Large Scale Integration (LSI) is presented. The theory of the MOSFET is used to study the temperature behavior of the device's electrical parameters. The main temperature dependent parameters are the threshold voltage, the channel mobility, and the junction leakage currents. Zero-Temperature-Coefficient (ZTC) gate bias voltages are predicted, in the nonsaturation (linear) region, and in the saturation region of operation, for a given device. Criteria for the existence of such bias points are developed, and nonidealities of those points discussed. The large and small signal parameters of the MOSFET biased at its ZTC points are obtained. Detailed comparisons with experimental results will be reported in an accompanying paper [1]. VLSI 1-micron MOS processing. F. MOHAMMADI. Electl Commun. 58, 405 (1984). Close attention to substrate characteristics, isolation techniques, gate design, and interconnect methods are necessary to produce MOS devices with a feature size of 1 gm. Scaling rules must be taken into account in the development of new processes and enhancements to device structures.
Multilayer resists for fine line optical lithography. E. ONG and E. L. Hu. Solid St. Technol. 155 (June 1984). Multilayer resist systems are gaining widespread acceptance in the manufacturing environment as feature sizes in manufactured devices shrink and linewidth control with single layer resist processes becomes increasingly difficult to maintain. The benefits and disadvantages of the three optical multilayer resist systems which have been used for device fabrication, namely, the organic portable conformal mask, the organic trilayer resist, and the inorganic bilayer structure are reviewed. These structures are discussed with respect to process complexity, defect density considerations, and attainable resolution and linewidth control. Designing for testability. G. W. JACOB. Electl Commun. 58, 427 (1984). With the increasing complexity of VLSI chips and systems, it is necessary to design them to be testable in order to contain rising test costs and provide high quality products. The technology of clean room design. PETER H. SINGER. Semiconductor Int. 92 (June 1984). Today's semiconductor clean rooms must be designed to minimize contamination as well as provide for operator safety, optimized process flow, flexibility, expandability and a number of other considerations. Experience in 3-micron processing: a 10 volt n-well CMOS process. D. BEERNAERT. Electl Commun. 58, 398 (1984). The advanced line circuit of System 12 demands high complexity, minimum power consumption, high performance, and high reliability of the integrated circuits. A 3gm 10V n-well
AND CONSTRUCTION CMOS process has been developed to produce the custom chips necessary in this system and offers a range of other possible applications.
Guidelines for publication of high resolution resist parameters. GARY N. TAYLOR. Solid St. Technol. 105 (June 1984). A variety of parameters is currently used to report resist properties in the technical literature. In order to establish a more uniform format for reporting, and hence comparing such data, a parameter outline has been developed. This was accomplished by circulating a set of proposals to workers active in resist and lithography research and development in the United States, Europe and Japan. Comments and suggestions were solicited for a first proposal. This led to a second proposal for which comments were again solicited. From these the present set of guidelines for reporting high resolution resist parameters was formulated. It is hoped that those guidelines will find utility and acceptance in the interested community and will aid in comparing data from various research laboratories worldwide. Recent developments in electron resists. E. D. ROBERTS. Solid St. Technol. 135 (June 1984). In the last few years, many electron resists developed by conventional methods using solvents have been described. This article reviews the relatively small number of systems based upon the new concept of dry development. This may be achieved with exposure or by subsequent treatment in gaseous plasmas. The use as electron resists formed by the Langmuir-Blodgett technique is also reviewed. The latter may be developed by solvents or by plasma treatment. Finally, a dry-etch resistant positiveworking electron resist produced in the author's laboratory is described. Design system for semi-custom VLSI circuits. A. D. CLOSE,L. FISHER, R.M. MCDERMOTT, T.A. NIX, D. M. PERRINE and J. M. SCHOEN.Electl Commun. 58, 372 (1984). The ITT semicustom design system enables complex VLSI circuits to be designed rapidly with a high expectation of correctness on the first pass. Planned improvements will make it possible to produce semi-custom circuits that are as complex as today's full-custom design circuits. VLSI for the ISDN line termination. R. D1ERCKX,P. GUEBELS and P. Six. Electl Commun. 58, 411 (1984). An important step in the evolution towards an integrated services digital network isdevelopment of the U-interface which provides a level I connection between the line terminations at the subscriber and exchange ends. Initially the U-interface for System 12 will consist of four VLSI chips, but as 1.5gm technology becomes established these will be replaced by a single chip.
Epitaxial silicon for bipolar integrated circuits. H. M. LIAW, J. ROSE and P.L. FEJES. Solid St. Technol. 135 (May 1984). Epitaxial material requirements for bipolar device applications are discussed in terms of substrate parameters, dopant and thickness uniformities, pattern shift, and transition width. Epitaxial reactors and growth parameters which affect the epitaxial film characteristics are reviewed. Recent
393
conductor parts manufactured in house strains resources, slows firms' plans to enter the merchant market,
two may, at first, seem superfluous, the technologies used to serve the different applications are diverging.
Microeleetronics and power. ALAN FOSTER. Electronics and Power 459 (June 1984). The field of power electronics contains two distinct application areas--in electronic power and electrical power. Although drawing a distinction between the
CLEO lights way to optical ICs. TERRY FELDT. Electronics 102 (28 June 1984). Laser conference spotlights devices for optical signal processing, but practical monolithic optical circuits are still a long way off.
5. M I C R O E L E C T R O N I C S - - D E S I G N
Electrical characteristics of large scale integration (LSI) MOSFETs at very high temperatures. Part I; theory. F. SHOUCAIR,W. HWANG and P. JAIN. Microelectron. Reliab. 24, 465 (1984). A systematic investigation of the effects of high temperature (27°C to 300°C) on long N and P channel MOS transistors suitable for Large Scale Integration (LSI) is presented. The theory of the MOSFET is used to study the temperature behavior of the device's electrical parameters. The main temperature dependent parameters are the threshold voltage, the channel mobility, and the junction leakage currents. Zero-Temperature-Coefficient (ZTC) gate bias voltages are predicted, in the nonsaturation (linear) region, and in the saturation region of operation, for a given device. Criteria for the existence of such bias points are developed, and nonidealities of those points discussed. The large and small signal parameters of the MOSFET biased at its ZTC points are obtained. Detailed comparisons with experimental results will be reported in an accompanying paper [1]. VLSI 1-micron MOS processing. F. MOHAMMADI. Electl Commun. 58, 405 (1984). Close attention to substrate characteristics, isolation techniques, gate design, and interconnect methods are necessary to produce MOS devices with a feature size of 1 gm. Scaling rules must be taken into account in the development of new processes and enhancements to device structures.
Multilayer resists for fine line optical lithography. E. ONG and E. L. Hu. Solid St. Technol. 155 (June 1984). Multilayer resist systems are gaining widespread acceptance in the manufacturing environment as feature sizes in manufactured devices shrink and linewidth control with single layer resist processes becomes increasingly difficult to maintain. The benefits and disadvantages of the three optical multilayer resist systems which have been used for device fabrication, namely, the organic portable conformal mask, the organic trilayer resist, and the inorganic bilayer structure are reviewed. These structures are discussed with respect to process complexity, defect density considerations, and attainable resolution and linewidth control. Designing for testability. G. W. JACOB. Electl Commun. 58, 427 (1984). With the increasing complexity of VLSI chips and systems, it is necessary to design them to be testable in order to contain rising test costs and provide high quality products. The technology of clean room design. PETER H. SINGER. Semiconductor Int. 92 (June 1984). Today's semiconductor clean rooms must be designed to minimize contamination as well as provide for operator safety, optimized process flow, flexibility, expandability and a number of other considerations. Experience in 3-micron processing: a 10 volt n-well CMOS process. D. BEERNAERT. Electl Commun. 58, 398 (1984). The advanced line circuit of System 12 demands high complexity, minimum power consumption, high performance, and high reliability of the integrated circuits. A 3gm 10V n-well
AND CONSTRUCTION CMOS process has been developed to produce the custom chips necessary in this system and offers a range of other possible applications.
Guidelines for publication of high resolution resist parameters. GARY N. TAYLOR. Solid St. Technol. 105 (June 1984). A variety of parameters is currently used to report resist properties in the technical literature. In order to establish a more uniform format for reporting, and hence comparing such data, a parameter outline has been developed. This was accomplished by circulating a set of proposals to workers active in resist and lithography research and development in the United States, Europe and Japan. Comments and suggestions were solicited for a first proposal. This led to a second proposal for which comments were again solicited. From these the present set of guidelines for reporting high resolution resist parameters was formulated. It is hoped that those guidelines will find utility and acceptance in the interested community and will aid in comparing data from various research laboratories worldwide. Recent developments in electron resists. E. D. ROBERTS. Solid St. Technol. 135 (June 1984). In the last few years, many electron resists developed by conventional methods using solvents have been described. This article reviews the relatively small number of systems based upon the new concept of dry development. This may be achieved with exposure or by subsequent treatment in gaseous plasmas. The use as electron resists formed by the Langmuir-Blodgett technique is also reviewed. The latter may be developed by solvents or by plasma treatment. Finally, a dry-etch resistant positiveworking electron resist produced in the author's laboratory is described. Design system for semi-custom VLSI circuits. A. D. CLOSE,L. FISHER, R.M. MCDERMOTT, T.A. NIX, D. M. PERRINE and J. M. SCHOEN.Electl Commun. 58, 372 (1984). The ITT semicustom design system enables complex VLSI circuits to be designed rapidly with a high expectation of correctness on the first pass. Planned improvements will make it possible to produce semi-custom circuits that are as complex as today's full-custom design circuits. VLSI for the ISDN line termination. R. D1ERCKX,P. GUEBELS and P. Six. Electl Commun. 58, 411 (1984). An important step in the evolution towards an integrated services digital network isdevelopment of the U-interface which provides a level I connection between the line terminations at the subscriber and exchange ends. Initially the U-interface for System 12 will consist of four VLSI chips, but as 1.5gm technology becomes established these will be replaced by a single chip.
Epitaxial silicon for bipolar integrated circuits. H. M. LIAW, J. ROSE and P.L. FEJES. Solid St. Technol. 135 (May 1984). Epitaxial material requirements for bipolar device applications are discussed in terms of substrate parameters, dopant and thickness uniformities, pattern shift, and transition width. Epitaxial reactors and growth parameters which affect the epitaxial film characteristics are reviewed. Recent