- Email: [email protected]
CMOS analog front-end channel for silicon photo-multipliers
ARTICLE IN PRESS Nuclear Instruments and Methods in Physics Research A 617 (2010) 319–320
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
CMOS analog front-end channel for silicon photo-multipliers$ F. Corsi a,, M. Foresta a, C. Marzocca a, G. Matarrese a, A. Del Guerra b a b
DEE-Politecnico di Bari, Via Orabona 4, I-70125 Bari, Italy Department of Physics, University of Pisa, Largo Bruno Pontecorvo 3, I-56127 Pisa, Italy
a r t i c l e in fo
abstract
Available online 22 September 2009
A complete self-triggered CMOS analog front-end suitable for silicon photo-multiplier detectors (SiPM) is proposed here, mainly intended for medical imaging applications. The exploitation of a current mode approach allows to achieve the large dynamic range and fast timing required by this kind of detectors without excessive power consumption. Results from characterization measurements on the prototype of the analog channel are also reported: the trigger signal produced by the circuit in response to a fast input current pulse exhibits a measured timing accuracy better than 60 ps and a dynamic range of about 50 pC has been obtained. & 2009 Elsevier B.V. All rights reserved.
Keywords: Silicon photomultipliers Front-end electronics
1. Introduction Solid-state silicon photo-multiplier detectors (SiPM) are likely to replace photo-multiplier tubes (PMT) in several applications in the fields of medical imaging and high energy physics [1]. Among other interesting features, they exhibit large gain and excellent timing resolution, which can be fully exploited if suitable integrated front-end electronics is available, especially when a very large number of detection channels are required by the target application. Among the possible approaches for the read-out of SiPM detectors, a current-mode solution, based on a current buffer with very low input impedance and large bandwidth used in the first stage of the analog front-end, offers several advantages in terms of linearity range, speed of operation and flexibility in the further signal processing stages [2]. In fact, by applying this approach, the circuit exhibits only low impedance nodes, characterized by small voltage swings and associated to very fast time constants. Moreover, the output signal of the front-end stage is a current, which can be easily replicated and/or scaled down by means of current mirrors. By exploiting this feature of the input current buffer, the architecture of the proposed analog channel is composed by two parallel signal paths. In the first path, one of the outputs of the current buffer, suitably scaled down to cope with the dynamic range issues, is integrated to provide a voltage signal proportional to the total charge delivered by an event detected by the SiPM. In the second signal path, another output of the current buffer, not scaled down, is used to drive a fast current discriminator with programmable threshold, which produces the
$
Work developed within the framework of the INFN DASiPM2 collaboration.
Corresponding author. Tel.: + 39 80 5963265; fax: + 39 80 5963410.
E-mail address: [email protected] (F. Corsi). 0168-9002/$ - see front matter & 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2009.09.037
trigger signal, useful to start the read-out procedures and/or to perform coincidence analysis, for instance in a PET system. A prototype of the circuit has been realized in a standard 0:35 mm CMOS process and some preliminary results from the characterization tests are reported.
2. Circuit structure and characterization results The described architecture of the proposed analog channel is schematically depicted in Fig. 1. The input current buffer is essentially a common gate stage enclosed in a feedback loop which allows for decreasing the input resistance and increasing the bandwidth of the circuit. The scaling factor M used for the first signal path has been set to 10 and both the integration capacitance CF and the damping resistance RF have been made digitally programmable in order to fit the requirements of different detectors and applications. The average value of the damping time constant is 200 ns. To make the read-out of the channel easier, the peak value of the voltage at the output of the integrator is held by means of a peak detector, based on a feedback loop which employs a PMOS current mirror as a rectifying element instead of a diode [3]. To set the DC value at the output of the integrator, i.e. the baseline level of the output pulses, a baseline holder circuit has been exploited. The virtual short circuit between the reference voltage Vbl and the integrator output holds only at extremely low frequencies, since the feedback loop is made ineffective at higher frequencies by the insertion of a very slow pole, represented by the capacitance Cblh in Fig. 1. Ad hoc circuit techniques have been exploited to realize the huge time constant required without integrating large capacitances and to prevent the well-known
ARTICLE IN PRESS 320
F. Corsi et al. / Nuclear Instruments and Methods in Physics Research A 617 (2010) 319–320
Fig. 1. Architecture of the proposed front-end channel.
Fig. 2. Voltage swing at the charge output vs width W of the LED excitation pulse.
phenomenon of the shift-down of the baseline level, associated to high values of the pulse rate [4]. A SiPM manufactured by FBK-Irst has been coupled to a prototype of the front-end electronics and a pulsed blue LED light source has been used to excite the detector. The SiPM+ LED system has been previously characterized to evaluate the average value and the standard deviation of the total charge QT delivered by the SiPM as a function of the width W of the voltage pulse used to drive the blue LED. Fig. 2 reports the measured average values of the voltage swing DV at the output of the ‘‘charge’’ path of the proposed circuit as a function of the width W, for three different gains (CF =1, 2 and 3 pF, respectively) and damping time constant fixed at 200 ns. The expected value of DV is given by
DV ¼ QT =ðMCF Þ:
ð1Þ
All the measured DV values in Fig. 2 are in good agreement with the expected ones for each value of CF and W. As an example, assuming W =9 ns, the SiPM delivers an average total charge
QT = 17.3 pC, at Vbias =32.5 V. From Eq. (1), setting CF = 1p F, DV =1.73 V is obtained, which is in good agreement with the experimental point highlighted in Fig. 2, placed at 1.76 V. Also the standard deviation of the charge output fits well the corresponding experimental values obtained from the characterization of the SiPM +LED system. For instance, considering the same point marked in Fig. 2, the value obtained with the proposed front-end is s = 1.13 pC, very close to the expected value of 1.08 pC. The linearity range of the circuit is about 50 pC. Concerning the fast signal path of the front-end, the threshold of the current discriminator can be modified by setting the configuration of a 4-bit DAC. The jitter of the trigger signal has been measured, fixing the threshold of the current discriminator at a low level and applying a voltage step, coupled by a 10 pF capacitance, to the input of the analog channel. The measured average delay between the edges of the trigger signal and the applied stimulus is about 1.77 ns, whereas its standard deviation is around 50 ps. Based on the described architecture, an 8-channel ASIC has been designed and manufactured. This chip includes an 8-bit ADC, a band-gap reference, a circuit which provides a unique fast trigger signal by fast-ORing the outputs of the current discriminators of each channel and a standard cell read-out logic, which implements different acquisition modes. The 8-channel ASIC is currently under test. References [1] P. Buzhan, et al., Silicon photomultiplier and its possible applications, Nucl. Instr. and Meth. A 504 (2003). [2] F. Corsi, et al., Preliminary results from a current mode CMOS front-end circuit for silicon photomultiplier detectors, in: Nuclear Science Symposium, 2007. [3] G. De Geronimo, P. O’Connor, A. Kandasamy, Analog CMOS peak detect and hold circuits. Part 1. Analysis of the classical configuration, Nucl. Instr. and Meth. A 484 (2002). [4] F. Corsi, M. Foresta, C. Marzocca, G. Matarrese, A. Tauro, A novel output baseline holder circuit for CMOS front-end analog channels, in: Nuclear Science Symposium, 2008.
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
CMOS analog front-end channel for silicon photo-multipliers$ F. Corsi a,, M. Foresta a, C. Marzocca a, G. Matarrese a, A. Del Guerra b a b
DEE-Politecnico di Bari, Via Orabona 4, I-70125 Bari, Italy Department of Physics, University of Pisa, Largo Bruno Pontecorvo 3, I-56127 Pisa, Italy
a r t i c l e in fo
abstract
Available online 22 September 2009
A complete self-triggered CMOS analog front-end suitable for silicon photo-multiplier detectors (SiPM) is proposed here, mainly intended for medical imaging applications. The exploitation of a current mode approach allows to achieve the large dynamic range and fast timing required by this kind of detectors without excessive power consumption. Results from characterization measurements on the prototype of the analog channel are also reported: the trigger signal produced by the circuit in response to a fast input current pulse exhibits a measured timing accuracy better than 60 ps and a dynamic range of about 50 pC has been obtained. & 2009 Elsevier B.V. All rights reserved.
Keywords: Silicon photomultipliers Front-end electronics
1. Introduction Solid-state silicon photo-multiplier detectors (SiPM) are likely to replace photo-multiplier tubes (PMT) in several applications in the fields of medical imaging and high energy physics [1]. Among other interesting features, they exhibit large gain and excellent timing resolution, which can be fully exploited if suitable integrated front-end electronics is available, especially when a very large number of detection channels are required by the target application. Among the possible approaches for the read-out of SiPM detectors, a current-mode solution, based on a current buffer with very low input impedance and large bandwidth used in the first stage of the analog front-end, offers several advantages in terms of linearity range, speed of operation and flexibility in the further signal processing stages [2]. In fact, by applying this approach, the circuit exhibits only low impedance nodes, characterized by small voltage swings and associated to very fast time constants. Moreover, the output signal of the front-end stage is a current, which can be easily replicated and/or scaled down by means of current mirrors. By exploiting this feature of the input current buffer, the architecture of the proposed analog channel is composed by two parallel signal paths. In the first path, one of the outputs of the current buffer, suitably scaled down to cope with the dynamic range issues, is integrated to provide a voltage signal proportional to the total charge delivered by an event detected by the SiPM. In the second signal path, another output of the current buffer, not scaled down, is used to drive a fast current discriminator with programmable threshold, which produces the
$
Work developed within the framework of the INFN DASiPM2 collaboration.
Corresponding author. Tel.: + 39 80 5963265; fax: + 39 80 5963410.
E-mail address: [email protected] (F. Corsi). 0168-9002/$ - see front matter & 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2009.09.037
trigger signal, useful to start the read-out procedures and/or to perform coincidence analysis, for instance in a PET system. A prototype of the circuit has been realized in a standard 0:35 mm CMOS process and some preliminary results from the characterization tests are reported.
2. Circuit structure and characterization results The described architecture of the proposed analog channel is schematically depicted in Fig. 1. The input current buffer is essentially a common gate stage enclosed in a feedback loop which allows for decreasing the input resistance and increasing the bandwidth of the circuit. The scaling factor M used for the first signal path has been set to 10 and both the integration capacitance CF and the damping resistance RF have been made digitally programmable in order to fit the requirements of different detectors and applications. The average value of the damping time constant is 200 ns. To make the read-out of the channel easier, the peak value of the voltage at the output of the integrator is held by means of a peak detector, based on a feedback loop which employs a PMOS current mirror as a rectifying element instead of a diode [3]. To set the DC value at the output of the integrator, i.e. the baseline level of the output pulses, a baseline holder circuit has been exploited. The virtual short circuit between the reference voltage Vbl and the integrator output holds only at extremely low frequencies, since the feedback loop is made ineffective at higher frequencies by the insertion of a very slow pole, represented by the capacitance Cblh in Fig. 1. Ad hoc circuit techniques have been exploited to realize the huge time constant required without integrating large capacitances and to prevent the well-known
ARTICLE IN PRESS 320
F. Corsi et al. / Nuclear Instruments and Methods in Physics Research A 617 (2010) 319–320
Fig. 1. Architecture of the proposed front-end channel.
Fig. 2. Voltage swing at the charge output vs width W of the LED excitation pulse.
phenomenon of the shift-down of the baseline level, associated to high values of the pulse rate [4]. A SiPM manufactured by FBK-Irst has been coupled to a prototype of the front-end electronics and a pulsed blue LED light source has been used to excite the detector. The SiPM+ LED system has been previously characterized to evaluate the average value and the standard deviation of the total charge QT delivered by the SiPM as a function of the width W of the voltage pulse used to drive the blue LED. Fig. 2 reports the measured average values of the voltage swing DV at the output of the ‘‘charge’’ path of the proposed circuit as a function of the width W, for three different gains (CF =1, 2 and 3 pF, respectively) and damping time constant fixed at 200 ns. The expected value of DV is given by
DV ¼ QT =ðMCF Þ:
ð1Þ
All the measured DV values in Fig. 2 are in good agreement with the expected ones for each value of CF and W. As an example, assuming W =9 ns, the SiPM delivers an average total charge
QT = 17.3 pC, at Vbias =32.5 V. From Eq. (1), setting CF = 1p F, DV =1.73 V is obtained, which is in good agreement with the experimental point highlighted in Fig. 2, placed at 1.76 V. Also the standard deviation of the charge output fits well the corresponding experimental values obtained from the characterization of the SiPM +LED system. For instance, considering the same point marked in Fig. 2, the value obtained with the proposed front-end is s = 1.13 pC, very close to the expected value of 1.08 pC. The linearity range of the circuit is about 50 pC. Concerning the fast signal path of the front-end, the threshold of the current discriminator can be modified by setting the configuration of a 4-bit DAC. The jitter of the trigger signal has been measured, fixing the threshold of the current discriminator at a low level and applying a voltage step, coupled by a 10 pF capacitance, to the input of the analog channel. The measured average delay between the edges of the trigger signal and the applied stimulus is about 1.77 ns, whereas its standard deviation is around 50 ps. Based on the described architecture, an 8-channel ASIC has been designed and manufactured. This chip includes an 8-bit ADC, a band-gap reference, a circuit which provides a unique fast trigger signal by fast-ORing the outputs of the current discriminators of each channel and a standard cell read-out logic, which implements different acquisition modes. The 8-channel ASIC is currently under test. References [1] P. Buzhan, et al., Silicon photomultiplier and its possible applications, Nucl. Instr. and Meth. A 504 (2003). [2] F. Corsi, et al., Preliminary results from a current mode CMOS front-end circuit for silicon photomultiplier detectors, in: Nuclear Science Symposium, 2007. [3] G. De Geronimo, P. O’Connor, A. Kandasamy, Analog CMOS peak detect and hold circuits. Part 1. Analysis of the classical configuration, Nucl. Instr. and Meth. A 484 (2002). [4] F. Corsi, M. Foresta, C. Marzocca, G. Matarrese, A. Tauro, A novel output baseline holder circuit for CMOS front-end analog channels, in: Nuclear Science Symposium, 2008.