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CMOS compatible micromachining by dry silicon-etching techniques
MicroelectronicEngineering 19 (1992) 191-194 Elsevier
191
CMOS Compatible Micromachining by Dry Silicon-Etching Techniques S. Adams, U. Hilleringmann, K. Goser University of Dortmund, Faculty of Electrical Engineering, Emil-Figge-Str. 68, D-4600 Dortmund 50, Fax: (0)231[7554450 Abstract
Dry etching techniques are used for monolithic integration of a mirco system consisting of a pressure sensor, integrated optics and VLSI CMOS circuits. The sensor is etched from the front side of the wafer and with the support of TEOS-spikes the membrane is deposited by PECVD technique.
1. Introduction
The fabrication of micromechanical devices is mainly based on anisotropic silicon wet etching. Solutions like KOH, NaOH, LiOH, NH4OH or EDP are used to structure threedimensional sensors and actuators. The property of this technique is the dependence of the etch rate on dopant concentration, crystal orientation and electrical potential. But combining mechanical devices and integrated circuits to form micro systems difficulties appear: A highly doped area, e.g. boron concentration of 3"1019 cm -3, is necessary to keep the process under control and to have a precise etch-stop [1]. Silicon in this area is degenerated and therefore the integration of electrical circuits is impossible. The anisotropic etching is limited to the < 111> crystal orientation of the silicon substrate and even the combination with optical devices raises problems. After KOH etching the optical loss of light waveguides increases [2]. In this paper we present a new approach forming CMOS compatible mechanical devices applying the process technique of integrated circuit fabrication. According to the reasons mentioned above silicon etching is done by reactive ion etching.
2. Technology
The plasma process allows to structure the silicon substrate independently of crystal orientation without discrepancy between the etched device and the design. The degree of anisotropy is adjustable by the choice of etching-gases, pressure and RF-power. There is no necessity of protection on the reverse side of the wafer during processing. Due to compatibility of this CMOS technique the major advantage is the possibility to perform the integrated circuits for read-out even on the mechanical devices themself. 0167-9317/92/$05.00 © 1992 - Elsevier Science Publishers B.V. All rights reserved.
192
S. Adams et al. / CMOS compatible micromachining
First of all fast plasma processes for silicon etching are well known. With etching gases like CBrF 3 or SF 6 by an addition of oxygen for smooth surfaces high etching rates (>1 pro/rain) are easily reached. Therefore common pressure sensors are built by etching from the reverse side of the wafer [3]. But as nearly the whole wafer tickness of approximately 500 pm has to be removed, this technique takes a long etching time and still an alignment between the two wafer surfaces is required. A further step narrowing the micromachining to IC technology is to form mechanical devices from the front side of the wafer. Here the underetching behaviour of SF 6 is useful. In Fig. 1 the result of this plasma etching process with high selectivity is illustrated. An oxide layer was structured like a chessboard and etched in SF 6 plasma up to an undercut of about 4 pro, while SF 6 doesn't affect the oxide squares. If the removed squares are smaller than the remaining oxide-squares a net results, as it is shown in Fig. 2. The net covers an area of 200 x 200 pm 2 and is completely underetched through 2.5 x 2.5 pm 2 holes.
Fig. 1: Chessboard-like oxide layer underetched with SF 6
Fig. 2: Completely underetched oxide net, 200 x 200 pm 2
There are no limitations of dimensions of the underetched layer, the size just depends on the geometrical arrangement of the holes. After closing the holes in the oxide layer by PECVD deposited siliconoxide a fully surrounded hallow space is built in the silicon substrate. But as shown in Fig. 3 the oxide deposition mainly results in a vertical growth of the oxide layer, so a deposition of a thick oxide layer is needed to close the holes. The requirements for a homogeneous closing behaviour of the membrane led to a more sophisticated technique. After structuring the etch holes into the oxide layer trenches are formed in the silicon substrate with a high degree of anisotropy. As etching gas a mixture of CBrF3/O 2 or SiC14]C12 is used. In the following step TEOS is deposited by LPCVD with a slightly nonconformal step coverage. The oxide layer with a thickness of 250 run is etched back by an anisotropic plasma process with a gasmixture of CHF 3 and Ar. The resulting TEOS-spikes remain at the trenchwalls. Fig. 4 shows a cross-section of a trench with TEOSspikes underetched in SF6-plasma. With support of the spikes plasma enhanced oxide deposition reaches a higher efficiency concerning lateral growth of the oxide layer. The arrival ~ngle of the oxide deposition increases up to 270 ° at the top of the trench. Therefore the lateral oxide growth equals the
193
S. Adams et al. / CMOS compatible micromachining
vertical growth in this section. An additional effect is a resulting mechanical tension between the deposited oxide layer and the TEOS-oxide underneath because of different deposition temperatures of LPCVD (750°C) and PECVD (300°C) [4]. As it is illustrated in Fig. 5 the TEOS-spikes are pulled up and expedite the closing mechanism of the trenches.
Fig. 3: SEM cross section showing the coverage of a 1.5 pm oxide layer deposited by PECVD
Fig. 4: Cross section of SF 6 underetched TEOS-spikes
3. Results
A pressure sensor consisting of a hallow space covered by an oxide membrane is integrated. The reference pressure in the hallow space is determined by the deposition pressure during PECVD. Any change of pressure in the environment of the sensor results in membrane bending, as it is wellknown in common sensors. Due to oxide membrane it is obvious to use piezoresistors or optical devices for sensing the bending, but the technology of integrated optics is more suitable. The oxide membrane needs a passivation layer against H 2diffusion, which decreases the reliability of the membrane. Therefore a SiON-layer is deposited by LPCVD or PECVD and covered by silicon oxide which is delineated by RIE [5]. The optical waveguides are structured to form interferometers [6] for read-out coupled via photodetectors to VLSI circuits for signal processing [7]. A concept of the whole micro system is illustrated in Fig. 6.
SiOv I~.
waveguidesAluminiumPoly-Si
space
J CMOS
I siliconsubstrste
Fig. 5: Closing the holes by PECVD supported by TEOS-spikes
circuit
Fig. 6: Concept of a completely integrated system
194
S. Adams et al. / CMOS compatible micromachining
All process steps are compatible to standard CMOS fabrication. Even more the combined integration of CMOS devices and mechanical components in the same area is faciliated. In trenches performed up to a depth of 8/am the TEOS-spikes serve as a passivation. After SF 6plasma etching silicon substrate will remain at the surface. The integration of CMOS circuits for analyzing mechanical effects may now be placed on the membrane itself to increase the package density and to use MOS-transistors for sensing. E.g. the electron mobility in the channel of the transistor placed at the edge of the membrane is influenced as a result of membrane bending.
4. Conclusions
In our first approach we have integrated pressure membranes in silicon substrate applying dry etching techniques. All process steps are feasible to monolithic integration technology. Dry etching techniques provide a wide field of application for micro systems on one chip consisting of electrical, optical and mechanical devices. Not only pressure sensors but also cantilever beams or resonators are under investigation. The major advantage is the CMOScompatibility and therefore the variety of read-out using interferometer, piezo-resistors or transistors.
Acknowledgement
The authors thank the BMVI" (Bundesministerium ffir Forschung und Technologie) for financial support and M. Obst, M. Kremer and A. Wiggershaus for processing the wafers.
References
4 5
6
H. Seidel, R. Voss, "Anisotropic Silicon-Etching Techniques", Micro System Technology 91, Ed.: R. Krahn, H. Reichl, Berlin 1991, p. 291-301 H. Bezzaoui, A. Baus, E. Voges, "Integrated Optics and Micromechanics on Silicon for Sensor Applications", Micro System Technology 91, Ed.: R. Krahn, H. Reichl, Berlin 1991, p. 482-487 K. Fischer, R. Hoffmann, J. Mfiller, "Design and fabrication of a mircomechanical interated optical pressure sensor", Micro System Technology 91, Ed.: R. Krahn, H. Reichl, Berlin 1991, p. 472-481 G. Schumicki, P. Segebrecht, "Prozegtechnologie", Springer Verlag, 1991 U. Hilleringmann, K. Knospe, C. Heite, K. Schumacher, K. Goser, "A Silicon Based Technology for Monolithic Integration of Waveguides and VLSI CMOS Circuits", Proceedings ESSDERC 91, Elsevier 1991, p. 289-292 D. Peters, K. Fischer, J. Mtiller, "Integrated Optics Based on Silicon Oxynitride Thin Film Deposited on Silicon Substrates for Sensor Applications", Sensors and Actuators, 1991, p. 425-431 U. Hilleringmann, K. Goser, "Results of Monolithic Integration of Optical Waveguides, Photodiodes and CMOS Circuits on Silicon", this issue
191
CMOS Compatible Micromachining by Dry Silicon-Etching Techniques S. Adams, U. Hilleringmann, K. Goser University of Dortmund, Faculty of Electrical Engineering, Emil-Figge-Str. 68, D-4600 Dortmund 50, Fax: (0)231[7554450 Abstract
Dry etching techniques are used for monolithic integration of a mirco system consisting of a pressure sensor, integrated optics and VLSI CMOS circuits. The sensor is etched from the front side of the wafer and with the support of TEOS-spikes the membrane is deposited by PECVD technique.
1. Introduction
The fabrication of micromechanical devices is mainly based on anisotropic silicon wet etching. Solutions like KOH, NaOH, LiOH, NH4OH or EDP are used to structure threedimensional sensors and actuators. The property of this technique is the dependence of the etch rate on dopant concentration, crystal orientation and electrical potential. But combining mechanical devices and integrated circuits to form micro systems difficulties appear: A highly doped area, e.g. boron concentration of 3"1019 cm -3, is necessary to keep the process under control and to have a precise etch-stop [1]. Silicon in this area is degenerated and therefore the integration of electrical circuits is impossible. The anisotropic etching is limited to the < 111> crystal orientation of the silicon substrate and even the combination with optical devices raises problems. After KOH etching the optical loss of light waveguides increases [2]. In this paper we present a new approach forming CMOS compatible mechanical devices applying the process technique of integrated circuit fabrication. According to the reasons mentioned above silicon etching is done by reactive ion etching.
2. Technology
The plasma process allows to structure the silicon substrate independently of crystal orientation without discrepancy between the etched device and the design. The degree of anisotropy is adjustable by the choice of etching-gases, pressure and RF-power. There is no necessity of protection on the reverse side of the wafer during processing. Due to compatibility of this CMOS technique the major advantage is the possibility to perform the integrated circuits for read-out even on the mechanical devices themself. 0167-9317/92/$05.00 © 1992 - Elsevier Science Publishers B.V. All rights reserved.
192
S. Adams et al. / CMOS compatible micromachining
First of all fast plasma processes for silicon etching are well known. With etching gases like CBrF 3 or SF 6 by an addition of oxygen for smooth surfaces high etching rates (>1 pro/rain) are easily reached. Therefore common pressure sensors are built by etching from the reverse side of the wafer [3]. But as nearly the whole wafer tickness of approximately 500 pm has to be removed, this technique takes a long etching time and still an alignment between the two wafer surfaces is required. A further step narrowing the micromachining to IC technology is to form mechanical devices from the front side of the wafer. Here the underetching behaviour of SF 6 is useful. In Fig. 1 the result of this plasma etching process with high selectivity is illustrated. An oxide layer was structured like a chessboard and etched in SF 6 plasma up to an undercut of about 4 pro, while SF 6 doesn't affect the oxide squares. If the removed squares are smaller than the remaining oxide-squares a net results, as it is shown in Fig. 2. The net covers an area of 200 x 200 pm 2 and is completely underetched through 2.5 x 2.5 pm 2 holes.
Fig. 1: Chessboard-like oxide layer underetched with SF 6
Fig. 2: Completely underetched oxide net, 200 x 200 pm 2
There are no limitations of dimensions of the underetched layer, the size just depends on the geometrical arrangement of the holes. After closing the holes in the oxide layer by PECVD deposited siliconoxide a fully surrounded hallow space is built in the silicon substrate. But as shown in Fig. 3 the oxide deposition mainly results in a vertical growth of the oxide layer, so a deposition of a thick oxide layer is needed to close the holes. The requirements for a homogeneous closing behaviour of the membrane led to a more sophisticated technique. After structuring the etch holes into the oxide layer trenches are formed in the silicon substrate with a high degree of anisotropy. As etching gas a mixture of CBrF3/O 2 or SiC14]C12 is used. In the following step TEOS is deposited by LPCVD with a slightly nonconformal step coverage. The oxide layer with a thickness of 250 run is etched back by an anisotropic plasma process with a gasmixture of CHF 3 and Ar. The resulting TEOS-spikes remain at the trenchwalls. Fig. 4 shows a cross-section of a trench with TEOSspikes underetched in SF6-plasma. With support of the spikes plasma enhanced oxide deposition reaches a higher efficiency concerning lateral growth of the oxide layer. The arrival ~ngle of the oxide deposition increases up to 270 ° at the top of the trench. Therefore the lateral oxide growth equals the
193
S. Adams et al. / CMOS compatible micromachining
vertical growth in this section. An additional effect is a resulting mechanical tension between the deposited oxide layer and the TEOS-oxide underneath because of different deposition temperatures of LPCVD (750°C) and PECVD (300°C) [4]. As it is illustrated in Fig. 5 the TEOS-spikes are pulled up and expedite the closing mechanism of the trenches.
Fig. 3: SEM cross section showing the coverage of a 1.5 pm oxide layer deposited by PECVD
Fig. 4: Cross section of SF 6 underetched TEOS-spikes
3. Results
A pressure sensor consisting of a hallow space covered by an oxide membrane is integrated. The reference pressure in the hallow space is determined by the deposition pressure during PECVD. Any change of pressure in the environment of the sensor results in membrane bending, as it is wellknown in common sensors. Due to oxide membrane it is obvious to use piezoresistors or optical devices for sensing the bending, but the technology of integrated optics is more suitable. The oxide membrane needs a passivation layer against H 2diffusion, which decreases the reliability of the membrane. Therefore a SiON-layer is deposited by LPCVD or PECVD and covered by silicon oxide which is delineated by RIE [5]. The optical waveguides are structured to form interferometers [6] for read-out coupled via photodetectors to VLSI circuits for signal processing [7]. A concept of the whole micro system is illustrated in Fig. 6.
SiOv I~.
waveguidesAluminiumPoly-Si
space
J CMOS
I siliconsubstrste
Fig. 5: Closing the holes by PECVD supported by TEOS-spikes
circuit
Fig. 6: Concept of a completely integrated system
194
S. Adams et al. / CMOS compatible micromachining
All process steps are compatible to standard CMOS fabrication. Even more the combined integration of CMOS devices and mechanical components in the same area is faciliated. In trenches performed up to a depth of 8/am the TEOS-spikes serve as a passivation. After SF 6plasma etching silicon substrate will remain at the surface. The integration of CMOS circuits for analyzing mechanical effects may now be placed on the membrane itself to increase the package density and to use MOS-transistors for sensing. E.g. the electron mobility in the channel of the transistor placed at the edge of the membrane is influenced as a result of membrane bending.
4. Conclusions
In our first approach we have integrated pressure membranes in silicon substrate applying dry etching techniques. All process steps are feasible to monolithic integration technology. Dry etching techniques provide a wide field of application for micro systems on one chip consisting of electrical, optical and mechanical devices. Not only pressure sensors but also cantilever beams or resonators are under investigation. The major advantage is the CMOScompatibility and therefore the variety of read-out using interferometer, piezo-resistors or transistors.
Acknowledgement
The authors thank the BMVI" (Bundesministerium ffir Forschung und Technologie) for financial support and M. Obst, M. Kremer and A. Wiggershaus for processing the wafers.
References
4 5
6
H. Seidel, R. Voss, "Anisotropic Silicon-Etching Techniques", Micro System Technology 91, Ed.: R. Krahn, H. Reichl, Berlin 1991, p. 291-301 H. Bezzaoui, A. Baus, E. Voges, "Integrated Optics and Micromechanics on Silicon for Sensor Applications", Micro System Technology 91, Ed.: R. Krahn, H. Reichl, Berlin 1991, p. 482-487 K. Fischer, R. Hoffmann, J. Mfiller, "Design and fabrication of a mircomechanical interated optical pressure sensor", Micro System Technology 91, Ed.: R. Krahn, H. Reichl, Berlin 1991, p. 472-481 G. Schumicki, P. Segebrecht, "Prozegtechnologie", Springer Verlag, 1991 U. Hilleringmann, K. Knospe, C. Heite, K. Schumacher, K. Goser, "A Silicon Based Technology for Monolithic Integration of Waveguides and VLSI CMOS Circuits", Proceedings ESSDERC 91, Elsevier 1991, p. 289-292 D. Peters, K. Fischer, J. Mtiller, "Integrated Optics Based on Silicon Oxynitride Thin Film Deposited on Silicon Substrates for Sensor Applications", Sensors and Actuators, 1991, p. 425-431 U. Hilleringmann, K. Goser, "Results of Monolithic Integration of Optical Waveguides, Photodiodes and CMOS Circuits on Silicon", this issue