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CMOS–MEMS integration today and tomorrow
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Scripta Materialia 59 (2008) 945–949 www.elsevier.com/locate/scriptamat
Viewpoint Paper
CMOS–MEMS integration today and tomorrow Ann Witvrouw* IMEC, PT/IPSI, Kapeldreef 75, 3001 Leuven, Belgium Received 15 November 2007; revised 17 June 2008; accepted 17 June 2008 Available online 6 July 2008
Abstract—The integration of complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS) can improve the performance of the MEMS, allows for smaller packages and leads to a lower packaging and instrumentation cost. Polycrystalline silicon–germanium (poly-SiGe) has already shown its potential for integrating MEMS and CMOS in a MEMS-last approach. The current state-of-the-art for poly-SiGe MEMS integration and the needs for the future will be addressed in this article. Market trends are translated into a roadmap for MEMS integration. Ó 2008 Acta Materialia Inc. Published by Elsevier Ltd. All rights reserved. Keywords: Compound semiconductors; Crystallization; Electrical properties; Mechanical properties
1. Introduction This paper discusses first the reasons for choosing complementary metal oxide semiconductor (CMOS)– microelectromechanical systems (MEMS) integration, in particular integration by polycrystalline silicon–germanium (poly-SiGe) processing above CMOS. In the next section, the achievements obtained using poly-SiGe post-processing will be presented. Then in the final section, the market is analyzed and the findings are translated into an envisioned roadmap for MEMS integration using poly-SiGe. 2. CMOS–MEMS integration Integration of the MEMS device with the integrated circuit has become increasingly important with regard to compactness and performance [1–4]. About half of the current MEMS market [31], however, still uses a hybrid approach (Fig. 1). Such an approach is modular and, as a consequence, has a much shorter development time as compared to the monolithic approach. It also allows for independent optimization of the integrated circuit (IC) and the MEMS technology. On the other hand, the assembly and packaging costs are higher in comparison to the monolithic approach. Consequently, once volumes become large enough, the longer development time needed for the monolithic approach is most likely * Tel.: +32 16 281 832; fax: +32 16 281 576; e-mail: [email protected]
to be paid back by the reduced assembly and packaging costs. Monolithic integration can also be chosen in cases where many interconnections between the MEMS and the CMOS need to be made (e.g. imagers), if miniaturization is important or if an increase in system performance is required. When separate chips for the MEMS and the IC are used, performance-limiting parasitics are present due to the interconnections between the MEMS and logic chip [4]. These parasitics result mainly from the size of the bond pads and from the long bonding wires, and would be reduced substantially by on-chip integration. Cost is also, of course, an important consideration. If the MEMS device is a lot larger than the CMOS circuit, monolithic integration might become too expensive. Ideally, their sizes are matched, certainly in the post-processing approach (see further), where identical sizes will not increase the CMOS die size. Integrating MEMS devices in state-of-the-art CMOS processes, yielding a miniature monolithic system solution, can be done in various ways. We can distinguish three major principles: (1) processing microsystems first and integrated circuits last, typically next to the sensors [5]; (2) interleaving the fabrication of both [6]; and (3) processing the integrated circuit first and the microsystem last [7,8], typically on top of the circuitry. This third method is, in our view, the most promising way to do smart microsystem processing, as it allows the use of standard CMOS processes and fairly independent optimization of the CMOS and MEMS. In addition, a
1359-6462/$ - see front matter Ó 2008 Acta Materialia Inc. Published by Elsevier Ltd. All rights reserved. doi:10.1016/j.scriptamat.2008.06.043
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Figure 1. Hybrid approach (left) vs. monolithic integration of MEMS and CMOS (right) [2].
new generation of circuitry can easily replace the older one without affecting the MEMS on top of it. Moreover, post-processing provides the most compact form of putting MEMS and CMOS together as the CMOS circuitry can potentially be situated underneath the MEMS structures. However, post-processing limits the thermal budget for MEMS processing. Poly-SiGe provides the necessary mechanical properties and reliability required for MEMS applications at a significantly lower temperature compared to conventional poly-Si (i.e. depositing temperatures of 6450 °C instead of P800 °C) [7–9]. This makes the poly-SiGe technology very well suited for post-CMOS integration of MEMS. 3. SiGe MEMS achievements 3.1. Materials A multitude of processes have already been developed for poly-SiGe MEMS [7–13], and the main tendencies have been to reduce the processing temperature [10–12] or increase the deposition rate at the same temperature [9,13]. By using a multilayer process (Fig. 2) that combines plasma-enhanced chemical vapor deposition (PECVD) and CVD, high-quality films can be obtained at low temperature (6450 °C) with very high deposition rates (100 nm min 1) [9]. This is the ideal process for the deposition of thick SiGe layers (e.g. for capacitive sensing applications) on top of standard CMOS. A low resistivity of 1.45 mX cm, a tensile residual stress of 35 MPa and a very low strain gradient of 3.6 10 6 lm 1 have been achieved for 10-lm-thick films using a top Si-rich stress compensation layer [14]. The contact between Al and SiGe was found to be ohmic, as required for CMOS integration [15].
For more advanced CMOS, the maximum post-processing temperature might need to be lower than 450 °C. For example, in the literature [16] a maximum thermal budget of 6 h at 425 °C was allowed for an 0.25 lm CMOS process as otherwise more than 10% degradation in the via resistance was observed. Therefore, special processes are developed to allow poly-SiGe deposition at the lowest possible temperature. 1. PECVD deposition of microcrystalline silicon–germanium (lc-SiGe:H) at temperatures equal to or below 400 °C has been studied. The material was originally developed for solar cells [17], however its use as a MEMS structural layer is innovative. PECVD deposition of microcrystalline SiGe uses a high hydrogen dilution, and the deposition rate (12–23 nm min 1) is therefore lower than the rates of the multilayer process described above. On the other hand, crystalline films are obtained at much lower temperatures (300–400 °C). Electrical resistivities down to 75 mX cm and 7 mX cm were measured for layers deposited at substrate temperatures of 300 and 400 °C, respectively [9,11], and a tensile residual stress and a strain gradient of 1.5 10 4 lm 1 could be obtained for a film deposited at 400 °C [14]. 2. Besides the use of the microcrystalline deposition, crystallization of SiGe can also be enhanced by the use of thin metal seeding layers. Also this technique has been used in the past for growing solar cell layers or CMOS gates at reduced temperature [18]. PECVD SixGe1 x (29% < x < 42%) films have been deposited at temperatures varying from 300 to 370 °C on top of 50 nm of either AlSi or Ti. SiGe films deposited on top of AlSi are more crystalline than those on top of Ti. Moreover, stacking Ti/Si1 xGex/Al/Si1 xGex noticeably improves the texture and at the same time results in a relatively low mean tensile residual stress (70 MPa) and stress gradient [2,19]. 3. By treating PECVD silicon–germanium (SixGe1 x), thin films deposited at low temperatures with a pulsed excimer laser good MEMS structural layers could be obtained, as demonstrated in Refs. [20,21]. In this work, the SiGe deposition temperature, which is the highest temperature the substrate feels, could be reduced down to 210 °C. Therefore, in addition to being used for CMOS integration, these low-temperature SiGe-based MEMS can also be integrated onto more exotic substrates, such as polymer films. 3.2. Integrated gyroscope
Figure 2. Cross-section of the PECVD/CVD poly-SiGe multilayer [9].
Integrated gyroscopes are already commercially available (e.g. using the integrated MEMS (iMEMS) process [6,22]), though not in a post-processed version. Instead, an interleaved approach is used, making the gyroscope in poly-Si with the CMOS circuitry next to it. For the same gyroscope design, this leads to an overall larger footprint compared to the post-processing case, and also has the disadvantage of modifying both the CMOS and the MEMS process. A standard CMOS process cannot be used and the MEMS structural layer thickness is limited (2–4 lm for iMEMS [6]). Using poly-SiGe, integrated xz-gyro-
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scopes above fully functioning CMOS for low-noise, high-resolution applications were realized [23] (Figs. 3 and 4). As a functional structure, a 10-lm thick SiGe layer is processed above a standard high voltage (20 V), 0.35 lm CMOS-ASIC from Philips (now NXP) with five wiring levels and standard passivation. The sacrificial layer is a thick undoped Si-oxide layer, which is planarized by the use of CMP. The SiGe structural layer is deposited by the combined CVD and PECVD process described above. The release is done using wet processing with HF and CO2 super-critical drying. The drive and sense of the in-plane double wing gyroscope is fully capacitive. Measurement of movement is also done fully capacitively in continuous-time baseband sensing. For characterization, the gyroscope chip is mounted on a breadboard with auxiliary circuits. A noise floor of 0.01° s 1 sqrt(Hz) 1/2 for operation at 3 mBar is achieved, corresponding to a minimal resolution of 0.07° s 1 for a 50-Hz bandwidth system.
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3.3. Flat and reliable micromirrors Monolithic integrated micromirror arrays are already well-established devices in applications such as video projection, adaptive optics and mask writers. The majority of current integrated micromirrors are Albased, often giving rise to reliability problems such as the hinge memory effect. Replacing Al by Si solves the problem, but integrating the Si mirrors with the CMOS driving circuitry can only be accomplished by a waferbonding technique. Similar to the case of the gyroscope, SiGe can replace Si in case above CMOS processing of the MEMS devices is needed. The SiGe structural layer developed for the micromirrors at IMEC is a microcrystalline SiGe layer (lc-SiGe:H), which can be deposited at even lower temperatures (300–400 °C) than the thick SiGe (450 °C) used for the gyroscopes. Moreover, the small SiGe grains (maximum 100 nm diameter) ensure uniform and reproducible mechanical properties of the submicron hinges. Using lc-SiGe:H, micro-mirrors were produced [24] with sizes between 7.5 7.5 and 16 16 lm2 and submicron hinges ranging from 250 to 400 nm (Fig. 5). The thermal budget of the process flow was kept below a CMOS-compatible 420 °C. The very flat mirrors (3–4 nm cupping, 0.3 nm surface roughness) showed no hinge creep over 20 days and no fatigue damage after 5 1010 cycles. The devices are a very promising alternative for the current Al-based micromirrors and are a good candidate to meet all flatness, uniformity and reliability specifications for future demanding micromirror applications. 3.4. Thin film packaging
Figure 3. Schematic cross-section of the integrated gyroscope.
Figure 4. Optical microscope picture of free standing SiGe gyroscope processed above CMOS [23].
Zero-level packaging of MEMS is done to prevent damage to the fragile MEMS device during dicing and assembly and to ensure a good operation and lifetime. Zero-level packaging is traditionally accomplished by bonding capping dies or a capping wafer to the wafer with the MEMS structures. Alternatively, surface micromachining can be used to process a thin film membrane above the MEMS device. After sacrificial etching of the sacrificial layer under and above the device, the membrane is sealed to enclose the required pressure and atmosphere in the cavity. The advantage of this approach is a reduced thickness and area of the packaged device compared to the traditional approach. This
Figure 5. SEM top view of a 16 16 lm2 lc-SiGe:H micromirror suspended on 2-lm-long torsional hinges.
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technique was developed using 20-lm-thick poly-Si membranes to package an accelerometer [25,26]. The membrane was strong enough to withstand a plasticmolded first level package. A special reflow sealing technique was developed to ensure the encapsulation of the MEMS device at a well-defined pressure and atmosphere [27]. While this older work used a poly-Si [25,26] or a poly-SiGe cap layer deposited at 550 or 590 °C [13], similar processing can be done at CMOScompatible temperatures, using the CVD + PECVD deposition process described in 3.1. Therefore, similar processing as used for the gyroscope can be used to fabricate thin film caps above MEMS devices, forming an area-saving integrated 0-level package.
an example of the single integrated devices. While this gyroscope has been demonstrated in a research project, the first production of integrated SiGe devices is expected by the start-up company SiClocks [32]. Putting devices in an array clearly decreases the area per device, as addressing of the individual devices is enabled by the CMOS below and common bondpads can be used. The micromirrors shown in Section 3.3 can easily be put in an array. Thin film packaging further decreases the area per device and thus also the cost (as explained in Section 3.4).
3.5. poly-SiGe: more than a mechanical material
In conclusion, poly-SiGe post-processing has the potential to become a generic technology in which different MEMS devices can be processed (together) on top of standard CMOS. Moreover, similar processing can be used to fabricate thin-film caps above MEMS devices, forming an area-saving MEMS-device-scale 0-level package [13]. Therefore this process might ultimately enable the creation of highly integrated miniature systems with multiple packaged sensors and actuators post-processed on a single chip. This is also shown as the final stage in the envisioned SiGe roadmap. Extensions to this roadmap could come by the addition of other materials, such as metals (e.g. for coils) or polymers (e.g. for temporary packaging or for low stiffness requirements). This is being investigated in the long-term Flemish research project, Gemini [33].
As shown above, poly-SiGe has excellent electrical and mechanical properties for MEMS applications. However, poly-SiGe is more than just a good mechanical material. Recently the optical [28] and piezoresistive [29] properties of SiGe were investigated. The absorption curve of lc-SiGe:H was found to shift to higher wavelengths with increasing Ge concentration. The available wavelength region for possible optical applications is estimated to be between 750 and 1500 nm, and can thus be tuned by the Ge concentration in the SiGe film [28]. In addition, a clear piezoresistive effect was seen in lc-SiGe:H. The determined piezoresistive coefficients were lower than the ones of poly-Si, but the use of monolithic integration might offset this drawback. Sensitivities of approximately 1 mV/V-bar are predicted for a possible pressure sensor application [29]. 4. Roadmap based on market evaluation For the automotive market it is predicted that the number of MEMS devices per vehicle will increase from the current 40 to 60 in 2011 [30]. In order not to increase the size or the price of the cars, it is expected that more integration and a lower cost per device will be needed. Also, a larger increase in the integrated MEMS market compared to the overall increase in the MEMS market has been predicted [31]. This clear market trend towards increased functionality per unit area and lower cost per device is translated into a roadmap for MEMS integration (Fig. 6). The integrated gyroscope of 3.2 is clearly
Figure 6. Envisioned roadmap for MEMS post-processing based on poly-SiGe.
5. Conclusions
Acknowledgements The author acknowledges the many IMEC colleagues who have contributed to the development of the SiGe MEMS technology. The European project partners within the IST projects SUMICAP and SiGeM are also greatly acknowledged.
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[9] A. Mehta, M. Gromova, C. Rusu, K. Baert, C. Van Hoof and A. Witvrouw, in: Proc. IEEE MEMS ’04, 2004, pp. 721–724. [10] T.J. King et al., in: Proc. IEDM, 2002, pp. 199–202. [11] M. Gromova, K. Baert, C. Van Hoof, A. Mehta, A. Witvrouw, Microelectron. Eng. 76 (2004) 266–271. [12] S. Sedky, M. Gromova, T. van der Donck, J.P. Celis, A. Witvrouw, Sensors Actuators A 127 (2) (2006) 316–323. [13] C. Rusu, S. Sedky, B. Parmentier, A. Verbist, O. Richard, B. Brijs, L. Geenen, A. Witvrouw, F. La¨rmer, F. Fischer, S. Kronmu¨ller, V. Leca, B. Otter, J. MEMS 12 (6) (2003) 816–825. [14] A. Mehta, M. Gromova, P. Czarnecki, K. Baert, A. Witvrouw, in: Proceedings of 13th International Conference on Solid State Sensors, Actuators and Microsystems, vol. 2, 2005, pp. 1326–1329. [15] A. Witvrouw, A. Mehta, A. Verbist, B. Du Bois, S. Van Aerde, J. Ramos-Martos, J. Ceballos, A. Ragel, J.M. Mora, M.A. Lagos, A. Arias, J.M. Hinojosa, J. Spengler, C. Leinenbach, T. Fuchs, S. Kronmu¨ller, in: Proc. ISSCC 2005, 2005, pp. 88–89. [16] H. Takeuchi, A. Wung, X. Sun, R.T. Howe, T.-J. King, IEEE Trans Electron. Dev. 52 (9) (2005) 2081–2086. [17] J.K. Rath et al., Solar Energy Mater. Solar Cells 74 (2002) 553–560. [18] S. Muramatsu et al., Solar Energy Mater. Solar Cells 74 (1–4) (2002) 275–281. [19] S. Sedky, K. Baert, C. Van Hoof, Y. Wang, O. Van Der Biest, A. Witvrouw, in: Proc. MRS Spring Conf. 2004, vol. 808, p. A4.19. [20] S. Sedky, A. Witvrouw, in: Proc. MEMS 2005, pp. 487490. [21] Sherif Sedky, Ahmed Bayoumy, Ahmed Alaa, Ahmed Nagy, Ann Witvrouw, JMEMS 16 (3) (2007) 581–588.
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[22] Available at:. [23] A. Schreurle, T. Fuchs, K. Kehr, C. Leinenbach, S. Kronmu¨ller, A. Arias, J. Ceballos, M.A. Lagos, J.M. Mora, J.M. Mun˜oz, A. Ragel, J. Ramos, S. Van Aerde, J. Spengler, A. Mehta, A. Verbist, B. Du Bois, A. Witvrouw, in: Proc. IEEE MEMS 07, pp. 39–42. [24] M.Gromova, L. Haspeslagh, A.Verbist, B. Du Bois, R. Van Hoof, B. Eyckens, B. Sijmus, I. De Wolf, V. Simons, Ph. Muller, T. Lauwagie, M. Willegems, S. Locorotondo, W. Boullart, K. Baert, A. Witvrouw, in: Proc. IEEE MEMS 2007, pp. 759–762. [25] H. Stahl, A. Hoechst, F. Fischer, L. Metzger, R. Reichenbach, F. Laermer, S. Kronmueller, K. Breitschwerdt, R. Gunn, S. Watcham, C. Rusu, A. Witvrouw, Proc. Transducers (2003) 1899. [26] A. Hoechst, R. Scheuerer, H. Stahl, F. Fischer, L. Metzger, R. Reichenbach, F. Laermer, S. Kronmueller, K. Breitschwerdt, R. Gunn, S. Watcham, C. Rusu, A. Witvrouw, Sensors Actuators 114 (2–3) (2004) 355–361. [27] C. Rusu, H. Jansen, R. Gunn, A. Witvrouw, Microsyst. Technol. 10 (2004) 364–371. [28] M. Gromova, K. Verheyen, P. Fiorini and A. Witvrouw, in: Proc. Eurosensors 2006, pp. 236–237. [29] S. Lenci, P. Gonzalez, K. De Meyer, R, Van Hoof, D. Frederickx, A. Witvrouw, in: Proc. IEEE MEMS 2008, pp. 427–430. [30] Solid State Technology Online, September 12, 2007. [31] MEMSentry, The Exclusive Yole Bulletin on MEMS, issue 2, January ‘06, p. 2. [32] Available at:
Scripta Materialia 59 (2008) 945–949 www.elsevier.com/locate/scriptamat
Viewpoint Paper
CMOS–MEMS integration today and tomorrow Ann Witvrouw* IMEC, PT/IPSI, Kapeldreef 75, 3001 Leuven, Belgium Received 15 November 2007; revised 17 June 2008; accepted 17 June 2008 Available online 6 July 2008
Abstract—The integration of complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS) can improve the performance of the MEMS, allows for smaller packages and leads to a lower packaging and instrumentation cost. Polycrystalline silicon–germanium (poly-SiGe) has already shown its potential for integrating MEMS and CMOS in a MEMS-last approach. The current state-of-the-art for poly-SiGe MEMS integration and the needs for the future will be addressed in this article. Market trends are translated into a roadmap for MEMS integration. Ó 2008 Acta Materialia Inc. Published by Elsevier Ltd. All rights reserved. Keywords: Compound semiconductors; Crystallization; Electrical properties; Mechanical properties
1. Introduction This paper discusses first the reasons for choosing complementary metal oxide semiconductor (CMOS)– microelectromechanical systems (MEMS) integration, in particular integration by polycrystalline silicon–germanium (poly-SiGe) processing above CMOS. In the next section, the achievements obtained using poly-SiGe post-processing will be presented. Then in the final section, the market is analyzed and the findings are translated into an envisioned roadmap for MEMS integration using poly-SiGe. 2. CMOS–MEMS integration Integration of the MEMS device with the integrated circuit has become increasingly important with regard to compactness and performance [1–4]. About half of the current MEMS market [31], however, still uses a hybrid approach (Fig. 1). Such an approach is modular and, as a consequence, has a much shorter development time as compared to the monolithic approach. It also allows for independent optimization of the integrated circuit (IC) and the MEMS technology. On the other hand, the assembly and packaging costs are higher in comparison to the monolithic approach. Consequently, once volumes become large enough, the longer development time needed for the monolithic approach is most likely * Tel.: +32 16 281 832; fax: +32 16 281 576; e-mail: [email protected]
to be paid back by the reduced assembly and packaging costs. Monolithic integration can also be chosen in cases where many interconnections between the MEMS and the CMOS need to be made (e.g. imagers), if miniaturization is important or if an increase in system performance is required. When separate chips for the MEMS and the IC are used, performance-limiting parasitics are present due to the interconnections between the MEMS and logic chip [4]. These parasitics result mainly from the size of the bond pads and from the long bonding wires, and would be reduced substantially by on-chip integration. Cost is also, of course, an important consideration. If the MEMS device is a lot larger than the CMOS circuit, monolithic integration might become too expensive. Ideally, their sizes are matched, certainly in the post-processing approach (see further), where identical sizes will not increase the CMOS die size. Integrating MEMS devices in state-of-the-art CMOS processes, yielding a miniature monolithic system solution, can be done in various ways. We can distinguish three major principles: (1) processing microsystems first and integrated circuits last, typically next to the sensors [5]; (2) interleaving the fabrication of both [6]; and (3) processing the integrated circuit first and the microsystem last [7,8], typically on top of the circuitry. This third method is, in our view, the most promising way to do smart microsystem processing, as it allows the use of standard CMOS processes and fairly independent optimization of the CMOS and MEMS. In addition, a
1359-6462/$ - see front matter Ó 2008 Acta Materialia Inc. Published by Elsevier Ltd. All rights reserved. doi:10.1016/j.scriptamat.2008.06.043
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Figure 1. Hybrid approach (left) vs. monolithic integration of MEMS and CMOS (right) [2].
new generation of circuitry can easily replace the older one without affecting the MEMS on top of it. Moreover, post-processing provides the most compact form of putting MEMS and CMOS together as the CMOS circuitry can potentially be situated underneath the MEMS structures. However, post-processing limits the thermal budget for MEMS processing. Poly-SiGe provides the necessary mechanical properties and reliability required for MEMS applications at a significantly lower temperature compared to conventional poly-Si (i.e. depositing temperatures of 6450 °C instead of P800 °C) [7–9]. This makes the poly-SiGe technology very well suited for post-CMOS integration of MEMS. 3. SiGe MEMS achievements 3.1. Materials A multitude of processes have already been developed for poly-SiGe MEMS [7–13], and the main tendencies have been to reduce the processing temperature [10–12] or increase the deposition rate at the same temperature [9,13]. By using a multilayer process (Fig. 2) that combines plasma-enhanced chemical vapor deposition (PECVD) and CVD, high-quality films can be obtained at low temperature (6450 °C) with very high deposition rates (100 nm min 1) [9]. This is the ideal process for the deposition of thick SiGe layers (e.g. for capacitive sensing applications) on top of standard CMOS. A low resistivity of 1.45 mX cm, a tensile residual stress of 35 MPa and a very low strain gradient of 3.6 10 6 lm 1 have been achieved for 10-lm-thick films using a top Si-rich stress compensation layer [14]. The contact between Al and SiGe was found to be ohmic, as required for CMOS integration [15].
For more advanced CMOS, the maximum post-processing temperature might need to be lower than 450 °C. For example, in the literature [16] a maximum thermal budget of 6 h at 425 °C was allowed for an 0.25 lm CMOS process as otherwise more than 10% degradation in the via resistance was observed. Therefore, special processes are developed to allow poly-SiGe deposition at the lowest possible temperature. 1. PECVD deposition of microcrystalline silicon–germanium (lc-SiGe:H) at temperatures equal to or below 400 °C has been studied. The material was originally developed for solar cells [17], however its use as a MEMS structural layer is innovative. PECVD deposition of microcrystalline SiGe uses a high hydrogen dilution, and the deposition rate (12–23 nm min 1) is therefore lower than the rates of the multilayer process described above. On the other hand, crystalline films are obtained at much lower temperatures (300–400 °C). Electrical resistivities down to 75 mX cm and 7 mX cm were measured for layers deposited at substrate temperatures of 300 and 400 °C, respectively [9,11], and a tensile residual stress and a strain gradient of 1.5 10 4 lm 1 could be obtained for a film deposited at 400 °C [14]. 2. Besides the use of the microcrystalline deposition, crystallization of SiGe can also be enhanced by the use of thin metal seeding layers. Also this technique has been used in the past for growing solar cell layers or CMOS gates at reduced temperature [18]. PECVD SixGe1 x (29% < x < 42%) films have been deposited at temperatures varying from 300 to 370 °C on top of 50 nm of either AlSi or Ti. SiGe films deposited on top of AlSi are more crystalline than those on top of Ti. Moreover, stacking Ti/Si1 xGex/Al/Si1 xGex noticeably improves the texture and at the same time results in a relatively low mean tensile residual stress (70 MPa) and stress gradient [2,19]. 3. By treating PECVD silicon–germanium (SixGe1 x), thin films deposited at low temperatures with a pulsed excimer laser good MEMS structural layers could be obtained, as demonstrated in Refs. [20,21]. In this work, the SiGe deposition temperature, which is the highest temperature the substrate feels, could be reduced down to 210 °C. Therefore, in addition to being used for CMOS integration, these low-temperature SiGe-based MEMS can also be integrated onto more exotic substrates, such as polymer films. 3.2. Integrated gyroscope
Figure 2. Cross-section of the PECVD/CVD poly-SiGe multilayer [9].
Integrated gyroscopes are already commercially available (e.g. using the integrated MEMS (iMEMS) process [6,22]), though not in a post-processed version. Instead, an interleaved approach is used, making the gyroscope in poly-Si with the CMOS circuitry next to it. For the same gyroscope design, this leads to an overall larger footprint compared to the post-processing case, and also has the disadvantage of modifying both the CMOS and the MEMS process. A standard CMOS process cannot be used and the MEMS structural layer thickness is limited (2–4 lm for iMEMS [6]). Using poly-SiGe, integrated xz-gyro-
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scopes above fully functioning CMOS for low-noise, high-resolution applications were realized [23] (Figs. 3 and 4). As a functional structure, a 10-lm thick SiGe layer is processed above a standard high voltage (20 V), 0.35 lm CMOS-ASIC from Philips (now NXP) with five wiring levels and standard passivation. The sacrificial layer is a thick undoped Si-oxide layer, which is planarized by the use of CMP. The SiGe structural layer is deposited by the combined CVD and PECVD process described above. The release is done using wet processing with HF and CO2 super-critical drying. The drive and sense of the in-plane double wing gyroscope is fully capacitive. Measurement of movement is also done fully capacitively in continuous-time baseband sensing. For characterization, the gyroscope chip is mounted on a breadboard with auxiliary circuits. A noise floor of 0.01° s 1 sqrt(Hz) 1/2 for operation at 3 mBar is achieved, corresponding to a minimal resolution of 0.07° s 1 for a 50-Hz bandwidth system.
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3.3. Flat and reliable micromirrors Monolithic integrated micromirror arrays are already well-established devices in applications such as video projection, adaptive optics and mask writers. The majority of current integrated micromirrors are Albased, often giving rise to reliability problems such as the hinge memory effect. Replacing Al by Si solves the problem, but integrating the Si mirrors with the CMOS driving circuitry can only be accomplished by a waferbonding technique. Similar to the case of the gyroscope, SiGe can replace Si in case above CMOS processing of the MEMS devices is needed. The SiGe structural layer developed for the micromirrors at IMEC is a microcrystalline SiGe layer (lc-SiGe:H), which can be deposited at even lower temperatures (300–400 °C) than the thick SiGe (450 °C) used for the gyroscopes. Moreover, the small SiGe grains (maximum 100 nm diameter) ensure uniform and reproducible mechanical properties of the submicron hinges. Using lc-SiGe:H, micro-mirrors were produced [24] with sizes between 7.5 7.5 and 16 16 lm2 and submicron hinges ranging from 250 to 400 nm (Fig. 5). The thermal budget of the process flow was kept below a CMOS-compatible 420 °C. The very flat mirrors (3–4 nm cupping, 0.3 nm surface roughness) showed no hinge creep over 20 days and no fatigue damage after 5 1010 cycles. The devices are a very promising alternative for the current Al-based micromirrors and are a good candidate to meet all flatness, uniformity and reliability specifications for future demanding micromirror applications. 3.4. Thin film packaging
Figure 3. Schematic cross-section of the integrated gyroscope.
Figure 4. Optical microscope picture of free standing SiGe gyroscope processed above CMOS [23].
Zero-level packaging of MEMS is done to prevent damage to the fragile MEMS device during dicing and assembly and to ensure a good operation and lifetime. Zero-level packaging is traditionally accomplished by bonding capping dies or a capping wafer to the wafer with the MEMS structures. Alternatively, surface micromachining can be used to process a thin film membrane above the MEMS device. After sacrificial etching of the sacrificial layer under and above the device, the membrane is sealed to enclose the required pressure and atmosphere in the cavity. The advantage of this approach is a reduced thickness and area of the packaged device compared to the traditional approach. This
Figure 5. SEM top view of a 16 16 lm2 lc-SiGe:H micromirror suspended on 2-lm-long torsional hinges.
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technique was developed using 20-lm-thick poly-Si membranes to package an accelerometer [25,26]. The membrane was strong enough to withstand a plasticmolded first level package. A special reflow sealing technique was developed to ensure the encapsulation of the MEMS device at a well-defined pressure and atmosphere [27]. While this older work used a poly-Si [25,26] or a poly-SiGe cap layer deposited at 550 or 590 °C [13], similar processing can be done at CMOScompatible temperatures, using the CVD + PECVD deposition process described in 3.1. Therefore, similar processing as used for the gyroscope can be used to fabricate thin film caps above MEMS devices, forming an area-saving integrated 0-level package.
an example of the single integrated devices. While this gyroscope has been demonstrated in a research project, the first production of integrated SiGe devices is expected by the start-up company SiClocks [32]. Putting devices in an array clearly decreases the area per device, as addressing of the individual devices is enabled by the CMOS below and common bondpads can be used. The micromirrors shown in Section 3.3 can easily be put in an array. Thin film packaging further decreases the area per device and thus also the cost (as explained in Section 3.4).
3.5. poly-SiGe: more than a mechanical material
In conclusion, poly-SiGe post-processing has the potential to become a generic technology in which different MEMS devices can be processed (together) on top of standard CMOS. Moreover, similar processing can be used to fabricate thin-film caps above MEMS devices, forming an area-saving MEMS-device-scale 0-level package [13]. Therefore this process might ultimately enable the creation of highly integrated miniature systems with multiple packaged sensors and actuators post-processed on a single chip. This is also shown as the final stage in the envisioned SiGe roadmap. Extensions to this roadmap could come by the addition of other materials, such as metals (e.g. for coils) or polymers (e.g. for temporary packaging or for low stiffness requirements). This is being investigated in the long-term Flemish research project, Gemini [33].
As shown above, poly-SiGe has excellent electrical and mechanical properties for MEMS applications. However, poly-SiGe is more than just a good mechanical material. Recently the optical [28] and piezoresistive [29] properties of SiGe were investigated. The absorption curve of lc-SiGe:H was found to shift to higher wavelengths with increasing Ge concentration. The available wavelength region for possible optical applications is estimated to be between 750 and 1500 nm, and can thus be tuned by the Ge concentration in the SiGe film [28]. In addition, a clear piezoresistive effect was seen in lc-SiGe:H. The determined piezoresistive coefficients were lower than the ones of poly-Si, but the use of monolithic integration might offset this drawback. Sensitivities of approximately 1 mV/V-bar are predicted for a possible pressure sensor application [29]. 4. Roadmap based on market evaluation For the automotive market it is predicted that the number of MEMS devices per vehicle will increase from the current 40 to 60 in 2011 [30]. In order not to increase the size or the price of the cars, it is expected that more integration and a lower cost per device will be needed. Also, a larger increase in the integrated MEMS market compared to the overall increase in the MEMS market has been predicted [31]. This clear market trend towards increased functionality per unit area and lower cost per device is translated into a roadmap for MEMS integration (Fig. 6). The integrated gyroscope of 3.2 is clearly
Figure 6. Envisioned roadmap for MEMS post-processing based on poly-SiGe.
5. Conclusions
Acknowledgements The author acknowledges the many IMEC colleagues who have contributed to the development of the SiGe MEMS technology. The European project partners within the IST projects SUMICAP and SiGeM are also greatly acknowledged.
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