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Comment on “Efficient approaches for designing reversible Binary Coded Decimal adders”
ARTICLE IN PRESS Microelectronics Journal 41 (2010) 308–310
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Comment on ‘‘Efficient approaches for designing reversible Binary Coded Decimal adders’’ Rigui Zhou a,b, Yang Shi a,n, Jian Cao a, Hui’an Wang a a b
College of Information Engineering, East China Jiao Tong University, Nanchang, Jiangxi 330013, China Key Laboratory of Intelligent Computing & Information Processing of Ministry of Education, Xiangtan University, Xiangtan, Hunan 411105, China
a r t i c l e in f o
a b s t r a c t
Article history: Received 2 February 2010 Received in revised form 8 March 2010 Accepted 16 March 2010 Available online 18 April 2010
This paper is an exploratory behaviour of research errors in ‘‘Efficient approaches for designing reversible Binary Coded Decimal adders’’.
Keywords: Exploratory behaviour Research errors
In the article ‘‘Efficient approaches for designing reversible Binary Coded Decimal adders’’ [1], Ashis Kumer Biswas et al. claimed that the quantum cost of the TSG gate was 13 in the Example 3.7 which was shown in Fig. 13 on the page of 1696 in the 39th issue of Microelectronics Journal in the year of 2008. But we think there is something wrong with this quantum cost which is achieved from Fig. 13 in [1] according to Definition 3.1 of this paper, and a series of conclusion in the remaining parts of this paper can be wrong because of that error. Actually, the proper quantum cost of TSG is 22 in our opinion. To facilitate the presentation, we copy Fig. 13 in [1] in Fig. 1. On the one hand, it can be learnt from Definition 3.1 of this paper that the quantum cost can be calculated as a total sum of 2 2 gates used (To be exact, the authors of [1] used a paper published in 1996 (Ref. [22] in [1]) to calculate the cost which was obsolete at the time of paper submission (27 November 2007 as stated in the original manuscript), we can easily know that the quantum cost of a 1 1 gate is 1 in accordance with the latest standard in [2]). Fig. 2 redraws the left side of the TSG gate, so the quantum cost of the left side of the TSG designed in [1] is 12 according to Definition 3.1 in [1], but the quantum cost of the dashed frame in Fig. 2 is actually 1. That is to say, quantum cost of this part is only 11. On the other hand, according to Fig. 2 in ‘‘Synthesis of Reversible Logic Circuits’’ [3] (This paper appears in: IEEE Transactions on
n
DOI of original article: 10.1016/j.mejo.2008.04.003 Corresponding author: Tel./fax: + 86 7917046285. E-mail address: [email protected] (Y. Shi).
0026-2692/$ - see front matter doi:10.1016/j.mejo.2010.03.007
Computer-Aided Design of Integrated Circuits and Systems), and Fig. 3 in ‘‘Evolutionary Approach to Quantum and Reversible Circuits Synthesis’’ [4] (This paper appears in: Artificial Intelligence Review), the crossing in a circuit stands for a SWAP circuit whose quantum cost is 3 in the view of quantum computation. The above two figures are culled in the Figs. 3 and 4. Thereby, the crossings in the right side of TSG designed in [1] just stand for three SWAP circuits according to the above conclusion. But the authors wrongly assume that these crossings could relatively easily be used without regard to quantum cost. So altogether, the total quantum cost of TSG gate is 22 because there are two extra FG gates in the lower right corner. Just because of the effect of this error, Tables 1 and 2 of this paper all have defects. So we update these two tables according to the correct quantum cost of TSG, as shown in Tables 1 and 2. In addition, we strongly believe that the circuit of TSG in [1] cannot get the correct output as Ashis Kumer Biswas et al. mentioned. When passing through the last crossing in the circuit of Fig. 13 in [1], the fourth output will swap its result with the third output, that is, A¯C¯B¯DC, rather than (A¯C¯B¯)DABC in Fig. 13 in [1]. This result does not match the fourth output they provided. Here we rebuild the TSG gate audaciously according to our current understanding to reversible logic design, which is shown in Fig. 5. just stands for the Toffoli gate. So the The dashed frame upper two inputs will be given to the outputs directly, and the third input will be changed into ABC. When this output passes which also essentially means the through the dashed frame
ARTICLE IN PRESS R. Zhou et al. / Microelectronics Journal 41 (2010) 308–310
A
A B C
309
V V
AC ⊕ B
V+
V V
V
( AC ⊕ B ) ⊕ D ( AC ⊕ B ) D ⊕ AB ⊕ C
D Fig. 1. Equivalent quantum representation of TSG gate.
Fig. 2. The left side of the TSG designed in [1].
Fig. 3. Fig. 2 in [3].
Fig. 4. Fig. 3 in [4].
Table 1 Comparison of different reversible BCD adders.
Number of gates Number of garbage outputs Delay Quantum cost
Circuit in [6]
Circuit in [5]
Circuit in [1]
11 22 10 209a
23 22 21b 139
10 10 10 50c
a In the original table, the quantum cost is 137. However, if in consideration of the correct quantum cost of TSG, we strongly think that the quantum cost of the circuit in [6] is 209. b In the original table, the delay is 13. But according to our observations, the delay should be 21 in strict accordance with the definition of delay. c In the original table, the quantum cost is 55. There are five MTSG gates(its quantum cost is 6),two FRG gates(its quantum cost is 5),one FG gate(its quantum cost is 1), one TG gate(its quantum cost is 5) and one Peres gate (its quantum cost is 4) in Fig. 19 in [1]. So the quantum cost is 50 in total.
Table 2 Comparison of different Carry Skip reversible BCD adders.
a
Circuit in [6] with fan-out Circuit in [6] without fan-out Circuit in [1] without fan-out a
a a
Number of gates
Number of garbage outputs
Delay
Quantum cost
15 21 15
27 27 27
10 12 10
209 215 71
Fan-outs in reversible design are forbidden, but as it was found in literature [6], the numbers are shown here only.
Toffoli gate, the following operations will take effect: B AðC ABÞ ¼ B AðCAB þ CABÞ ¼ B AðCAB þ AC þ BCÞ ¼ B ðAC þ ABCÞ ¼ B AC From the above mention transformations, it is easy to get the which is the same second output of the TSG gate. At last, in
in essence, the third output can be got with the dashed frame finally. The rightmost FG gate can realize the XOR between the current output of the second line and the fourth line, the result is the fourth output of the TSG gate. And, above all, the quantum cost of TSG in Fig. 5 is 21 which is less than the real quantum cost of TSG designed in [1].
ARTICLE IN PRESS 310
R. Zhou et al. / Microelectronics Journal 41 (2010) 308–310
A
V
1 B C
V V
V
V+
V
A
X
2 V
V+
V
AC ⊕ B
3 X
V
V
V+
( AC ⊕ B ) D ⊕ AB ⊕ C
( AC ⊕ B ) ⊕ D
D Fig. 5. Equivalent quantum representation of TSG gate.
Thus we strongly suggest that these parts of this paper should be discussed through peer review. Acknowledgement The authors would like to thank the anonymous referees for their helpful comments and suggestions to improve the presentation of this paper. This work is supported by the National Natural Science Foundation of China under Grant no. 60873069, China Postdoctoral Science Foundation funded project under Grant no. 20080440401, the Natural Science Foundation of Jiangxi Province under Grant no. 2009GZS0013 and the Open Project Program of Key Laboratory of Intelligent Computing & Information Processing of Ministry of Education, Xiangtan University, China (no. 2009ICIP04).
References [1] Ashis Kumer Biswas, Md.Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu, Efficient approaches for designing reversible Binary Coded Decimal adders, Microelectronics Journal 39 (2008) 1693–1703. [2] http://webhome.cs.uvic.ca/ dmaslov/. [3] Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes, Synthesis of Reversible Logic Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22 (2003) 710–722. [4] Martin Lukac, Marek Perkowski, Hilton Goi, Mkhail Pivtoraiko, Chung Hyo Yu, Kyusik Chung, Hyunkoo Jee, Byung-guk Kim, Yong-Duk Kim, Evolutionary approach to Quantum Reversible Circuits Synthesis, Artificial Intelligence Review 20 (2003) 361–417. [5] H.M.H. Babu, A.R. Chowdhury, Design of a compact reversible Binary Coded Decimal adder circuit, Elsevier Journal of Systems Architecture 52 (5) (2006) 272–282. [6] H. Thapliyal, S. Kotiyal, M.B. Srinivas, Novel BCD adders and their reversible logic implementation for IEEE 754r format, VLSI Design India (2006) 387–392.
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Comment on ‘‘Efficient approaches for designing reversible Binary Coded Decimal adders’’ Rigui Zhou a,b, Yang Shi a,n, Jian Cao a, Hui’an Wang a a b
College of Information Engineering, East China Jiao Tong University, Nanchang, Jiangxi 330013, China Key Laboratory of Intelligent Computing & Information Processing of Ministry of Education, Xiangtan University, Xiangtan, Hunan 411105, China
a r t i c l e in f o
a b s t r a c t
Article history: Received 2 February 2010 Received in revised form 8 March 2010 Accepted 16 March 2010 Available online 18 April 2010
This paper is an exploratory behaviour of research errors in ‘‘Efficient approaches for designing reversible Binary Coded Decimal adders’’.
Keywords: Exploratory behaviour Research errors
In the article ‘‘Efficient approaches for designing reversible Binary Coded Decimal adders’’ [1], Ashis Kumer Biswas et al. claimed that the quantum cost of the TSG gate was 13 in the Example 3.7 which was shown in Fig. 13 on the page of 1696 in the 39th issue of Microelectronics Journal in the year of 2008. But we think there is something wrong with this quantum cost which is achieved from Fig. 13 in [1] according to Definition 3.1 of this paper, and a series of conclusion in the remaining parts of this paper can be wrong because of that error. Actually, the proper quantum cost of TSG is 22 in our opinion. To facilitate the presentation, we copy Fig. 13 in [1] in Fig. 1. On the one hand, it can be learnt from Definition 3.1 of this paper that the quantum cost can be calculated as a total sum of 2 2 gates used (To be exact, the authors of [1] used a paper published in 1996 (Ref. [22] in [1]) to calculate the cost which was obsolete at the time of paper submission (27 November 2007 as stated in the original manuscript), we can easily know that the quantum cost of a 1 1 gate is 1 in accordance with the latest standard in [2]). Fig. 2 redraws the left side of the TSG gate, so the quantum cost of the left side of the TSG designed in [1] is 12 according to Definition 3.1 in [1], but the quantum cost of the dashed frame in Fig. 2 is actually 1. That is to say, quantum cost of this part is only 11. On the other hand, according to Fig. 2 in ‘‘Synthesis of Reversible Logic Circuits’’ [3] (This paper appears in: IEEE Transactions on
n
DOI of original article: 10.1016/j.mejo.2008.04.003 Corresponding author: Tel./fax: + 86 7917046285. E-mail address: [email protected] (Y. Shi).
0026-2692/$ - see front matter doi:10.1016/j.mejo.2010.03.007
Computer-Aided Design of Integrated Circuits and Systems), and Fig. 3 in ‘‘Evolutionary Approach to Quantum and Reversible Circuits Synthesis’’ [4] (This paper appears in: Artificial Intelligence Review), the crossing in a circuit stands for a SWAP circuit whose quantum cost is 3 in the view of quantum computation. The above two figures are culled in the Figs. 3 and 4. Thereby, the crossings in the right side of TSG designed in [1] just stand for three SWAP circuits according to the above conclusion. But the authors wrongly assume that these crossings could relatively easily be used without regard to quantum cost. So altogether, the total quantum cost of TSG gate is 22 because there are two extra FG gates in the lower right corner. Just because of the effect of this error, Tables 1 and 2 of this paper all have defects. So we update these two tables according to the correct quantum cost of TSG, as shown in Tables 1 and 2. In addition, we strongly believe that the circuit of TSG in [1] cannot get the correct output as Ashis Kumer Biswas et al. mentioned. When passing through the last crossing in the circuit of Fig. 13 in [1], the fourth output will swap its result with the third output, that is, A¯C¯B¯DC, rather than (A¯C¯B¯)DABC in Fig. 13 in [1]. This result does not match the fourth output they provided. Here we rebuild the TSG gate audaciously according to our current understanding to reversible logic design, which is shown in Fig. 5. just stands for the Toffoli gate. So the The dashed frame upper two inputs will be given to the outputs directly, and the third input will be changed into ABC. When this output passes which also essentially means the through the dashed frame
ARTICLE IN PRESS R. Zhou et al. / Microelectronics Journal 41 (2010) 308–310
A
A B C
309
V V
AC ⊕ B
V+
V V
V
( AC ⊕ B ) ⊕ D ( AC ⊕ B ) D ⊕ AB ⊕ C
D Fig. 1. Equivalent quantum representation of TSG gate.
Fig. 2. The left side of the TSG designed in [1].
Fig. 3. Fig. 2 in [3].
Fig. 4. Fig. 3 in [4].
Table 1 Comparison of different reversible BCD adders.
Number of gates Number of garbage outputs Delay Quantum cost
Circuit in [6]
Circuit in [5]
Circuit in [1]
11 22 10 209a
23 22 21b 139
10 10 10 50c
a In the original table, the quantum cost is 137. However, if in consideration of the correct quantum cost of TSG, we strongly think that the quantum cost of the circuit in [6] is 209. b In the original table, the delay is 13. But according to our observations, the delay should be 21 in strict accordance with the definition of delay. c In the original table, the quantum cost is 55. There are five MTSG gates(its quantum cost is 6),two FRG gates(its quantum cost is 5),one FG gate(its quantum cost is 1), one TG gate(its quantum cost is 5) and one Peres gate (its quantum cost is 4) in Fig. 19 in [1]. So the quantum cost is 50 in total.
Table 2 Comparison of different Carry Skip reversible BCD adders.
a
Circuit in [6] with fan-out Circuit in [6] without fan-out Circuit in [1] without fan-out a
a a
Number of gates
Number of garbage outputs
Delay
Quantum cost
15 21 15
27 27 27
10 12 10
209 215 71
Fan-outs in reversible design are forbidden, but as it was found in literature [6], the numbers are shown here only.
Toffoli gate, the following operations will take effect: B AðC ABÞ ¼ B AðCAB þ CABÞ ¼ B AðCAB þ AC þ BCÞ ¼ B ðAC þ ABCÞ ¼ B AC From the above mention transformations, it is easy to get the which is the same second output of the TSG gate. At last, in
in essence, the third output can be got with the dashed frame finally. The rightmost FG gate can realize the XOR between the current output of the second line and the fourth line, the result is the fourth output of the TSG gate. And, above all, the quantum cost of TSG in Fig. 5 is 21 which is less than the real quantum cost of TSG designed in [1].
ARTICLE IN PRESS 310
R. Zhou et al. / Microelectronics Journal 41 (2010) 308–310
A
V
1 B C
V V
V
V+
V
A
X
2 V
V+
V
AC ⊕ B
3 X
V
V
V+
( AC ⊕ B ) D ⊕ AB ⊕ C
( AC ⊕ B ) ⊕ D
D Fig. 5. Equivalent quantum representation of TSG gate.
Thus we strongly suggest that these parts of this paper should be discussed through peer review. Acknowledgement The authors would like to thank the anonymous referees for their helpful comments and suggestions to improve the presentation of this paper. This work is supported by the National Natural Science Foundation of China under Grant no. 60873069, China Postdoctoral Science Foundation funded project under Grant no. 20080440401, the Natural Science Foundation of Jiangxi Province under Grant no. 2009GZS0013 and the Open Project Program of Key Laboratory of Intelligent Computing & Information Processing of Ministry of Education, Xiangtan University, China (no. 2009ICIP04).
References [1] Ashis Kumer Biswas, Md.Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu, Efficient approaches for designing reversible Binary Coded Decimal adders, Microelectronics Journal 39 (2008) 1693–1703. [2] http://webhome.cs.uvic.ca/ dmaslov/. [3] Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes, Synthesis of Reversible Logic Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22 (2003) 710–722. [4] Martin Lukac, Marek Perkowski, Hilton Goi, Mkhail Pivtoraiko, Chung Hyo Yu, Kyusik Chung, Hyunkoo Jee, Byung-guk Kim, Yong-Duk Kim, Evolutionary approach to Quantum Reversible Circuits Synthesis, Artificial Intelligence Review 20 (2003) 361–417. [5] H.M.H. Babu, A.R. Chowdhury, Design of a compact reversible Binary Coded Decimal adder circuit, Elsevier Journal of Systems Architecture 52 (5) (2006) 272–282. [6] H. Thapliyal, S. Kotiyal, M.B. Srinivas, Novel BCD adders and their reversible logic implementation for IEEE 754r format, VLSI Design India (2006) 387–392.