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Comments on ‘Fast algorithms and implementation of 2-D discrete cosine transform’
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Engineering Information Abstracts (Part I)
Publication Year: 1998 Abstract: A simple, lossless audio codec, called AudioPaK, which uses only small number of integer arithmetic operations on both the coder and the decoder side, is designed. The main operations of this codec are polynomial prediction and Golomb-Rice coding, and are done on a frame basis. Studies show that the coder performs well, or even better than most lossless audio codecs. In English 1 Refs. EI Order Number: 98054184003 Keywords: Algorithms; Signal encoding; Digital signal processing; Image coding; Image compression; Computer networks; Image quality; Polynomials Title: COMMENTS ON ’FAST ALGORITHMS AND IMPLEMENTATION OF 2-D DISCRETE COSINE TRANSFORM’ Author(s): Wu, H.R.; Man, Zh. Source: IEEE Transactions on Circuits and Systems for Video Technology v 8 n 2 Apr 1998. IEEE Piscataway NJ USA. p 128-129 ISSN: 1051-8215 CODEN: ITCTEM Publication Year: 1998 Abstract: This letter shows that using the Loeffler’s one-dimensional Ž1-D. 8-point discrete cosine transform ŽDCT. algorithm w4x in Cho and Lee’s two-dimensional Ž2-D. 8 W 8-point DCT algorithm in the above paper will result in an optimal algorithm in the sense of multiplicative complexity theory. In English ŽAuthor abstract . 12 Refs. EI Order Number: 98044177564 Keywords: Video signal processing; Algorithms; Mathematical transformations; Computational complexity; Digital signal processing; Optimization Title: EFFICIENT RESIDUE TO WEIGHTED CONVERTER FOR A NEW RESIDUE NUMBER SYSTEM Author(s): Skavantzos, Alexander Source: Proceedings of the 1998 8th Great Lakes Symposium on VLSI Feb 19-21 1998 Lafayette, LA, USA. IEEE Comp Soc Los Alamitos CA USA. p 185-191 ISSN: 1066-1395 CODEN: PGVLEB Abstract: The Residue Number System ŽRNS. is an integer system appropriate for implementing fast digital signal processors since it can support parallel, carry-free, high-speed arithmetic. In this paper a new RNS system and an efficient implementation of its residue-to-weighted converter are presented. The new RNS is a balanced 5-moduli system appropriate for large dynamic ranges. The new residue-to-binary converter is very fast and hardware-efficient and is based on a 1’s complement multioperand adder adding operands of size only 80% of the size of the system’s dynamic range. In English ŽAuthor abstract . 28 Refs. EI Order Number: 98044166972 Publication Year: 1998 Keywords: Logic circuits; Carry logic; Parallel processing systems; Digital signal processing; Adders; Number theory; Computational complexity Title: MPEG-2 VIDEO DECODER FOR DVD Author(s): Wang, Nien-Tsu; Shih, Chen-Wei; Wong-Ho, Duan Juat; Ling, Nam
Source: Proceedings of the 1998 8th Great Lakes Symposium on VLSI Feb 19-21 1998 Lafayette, LA, USA. IEEE Comp Soc Los Alamitos CA USA. p 157-160 ISSN: 1066-1395 CODEN: PGVLEB Publication Year: 1998 Abstract: A video decoder with an efficient controller scheme and a sub-picture decoder for DVD application is presented in this paper. Most of the reported architecture for MPEG2 video decoding uses a 64 bit bus and a complex bus arbitration scheme. Our design uses synchronous DRAMs instead of standard EDO DRAMs and involves a novel controller scheme that allocates bus space for DRAM access efficiently. This efficient allocation allows us to reduce bus width from 64 bits to 32 bits, without significantly increasing embedded buffer sizes, and still meeting the requirements for MPEG2 MP@ML decoding. The bus arbitration algorithm is also simple allowing for a less complex controller design. Our main strategy is to impose a certain order in the DRAM access by the various processes instead of allowing any process to request for bus access arbitrarily. We also take advantage of the restricted GOP Žgroup of picture. sequence in the DVD format to allow a longer decoding time for B frames. The sub-picture pixel data are run-length compressed bitmaps that are overlayed on top of the MPEG reconstruction video. The architecture for sub-picture decoding is simple and easy to implement. In English ŽAuthor abstract . 6 Refs. EI Order Number: 98044166967 Keywords: Image compression; Decoding; Random access storage; Video signal processing; Algorithms; Image reconstruction; Standards; Storage allocation Žcomputer. Title: TWO-LEVEL PIPELINED SYSTOLIC ARRAYS FOR MATRIX-VECTOR MULTIPLICATION Author(s): Milentijevic, Ivan Z.; Milovanovic, Igor Z.; Milovanovic, Emina I.; Tosic, Milorad B.; Stojcev, Mile K. Source: Journal of Systems Architecture v 44 n 5 Feb 1998. Elsevier Sci B.V. Amsterdam Netherlands. p 383-387 ISSN: 1383-7621 CODEN: JSARFB Publication Year: 1998 Abstract: Novel two-level pipelined linear systolic arrays for matrix-vector multiplication are proposed. The number of processing elements in the proposed arrays is reduced to half of the number of processing elements in the existing arrays. An area-time ŽAT. criteria is used to compare the proposed arrays with the fastest existing one. In English ŽAuthor abstract. 4 Refs. EI Order Number: 98044164678 Keywords: Systolic arrays; Matrix algebra; Vectors; Calculations; Digital signal processing Title: HANDHELD DIGITAL VIDEO CODE DISTRIBUTOR USING EDGE-EMITTING LED’s AND SINGLE MODE OPTICAL FIBERS Author(s): Asada, Hideyuki; Rabou, Nabil Abd; Ikeda, Hiroaki; Shimodaira, Yoshifumi; Yoshida, Hirofumi Source: IEEE Transactions on Consumer Electronics v 44 n 1 Feb 1998 IEEE Piscataway NJ USA. p 155-162 ISSN: 00983063 CODEN: ITCEDA
Engineering Information Abstracts (Part I)
Publication Year: 1998 Abstract: A simple, lossless audio codec, called AudioPaK, which uses only small number of integer arithmetic operations on both the coder and the decoder side, is designed. The main operations of this codec are polynomial prediction and Golomb-Rice coding, and are done on a frame basis. Studies show that the coder performs well, or even better than most lossless audio codecs. In English 1 Refs. EI Order Number: 98054184003 Keywords: Algorithms; Signal encoding; Digital signal processing; Image coding; Image compression; Computer networks; Image quality; Polynomials Title: COMMENTS ON ’FAST ALGORITHMS AND IMPLEMENTATION OF 2-D DISCRETE COSINE TRANSFORM’ Author(s): Wu, H.R.; Man, Zh. Source: IEEE Transactions on Circuits and Systems for Video Technology v 8 n 2 Apr 1998. IEEE Piscataway NJ USA. p 128-129 ISSN: 1051-8215 CODEN: ITCTEM Publication Year: 1998 Abstract: This letter shows that using the Loeffler’s one-dimensional Ž1-D. 8-point discrete cosine transform ŽDCT. algorithm w4x in Cho and Lee’s two-dimensional Ž2-D. 8 W 8-point DCT algorithm in the above paper will result in an optimal algorithm in the sense of multiplicative complexity theory. In English ŽAuthor abstract . 12 Refs. EI Order Number: 98044177564 Keywords: Video signal processing; Algorithms; Mathematical transformations; Computational complexity; Digital signal processing; Optimization Title: EFFICIENT RESIDUE TO WEIGHTED CONVERTER FOR A NEW RESIDUE NUMBER SYSTEM Author(s): Skavantzos, Alexander Source: Proceedings of the 1998 8th Great Lakes Symposium on VLSI Feb 19-21 1998 Lafayette, LA, USA. IEEE Comp Soc Los Alamitos CA USA. p 185-191 ISSN: 1066-1395 CODEN: PGVLEB Abstract: The Residue Number System ŽRNS. is an integer system appropriate for implementing fast digital signal processors since it can support parallel, carry-free, high-speed arithmetic. In this paper a new RNS system and an efficient implementation of its residue-to-weighted converter are presented. The new RNS is a balanced 5-moduli system appropriate for large dynamic ranges. The new residue-to-binary converter is very fast and hardware-efficient and is based on a 1’s complement multioperand adder adding operands of size only 80% of the size of the system’s dynamic range. In English ŽAuthor abstract . 28 Refs. EI Order Number: 98044166972 Publication Year: 1998 Keywords: Logic circuits; Carry logic; Parallel processing systems; Digital signal processing; Adders; Number theory; Computational complexity Title: MPEG-2 VIDEO DECODER FOR DVD Author(s): Wang, Nien-Tsu; Shih, Chen-Wei; Wong-Ho, Duan Juat; Ling, Nam
Source: Proceedings of the 1998 8th Great Lakes Symposium on VLSI Feb 19-21 1998 Lafayette, LA, USA. IEEE Comp Soc Los Alamitos CA USA. p 157-160 ISSN: 1066-1395 CODEN: PGVLEB Publication Year: 1998 Abstract: A video decoder with an efficient controller scheme and a sub-picture decoder for DVD application is presented in this paper. Most of the reported architecture for MPEG2 video decoding uses a 64 bit bus and a complex bus arbitration scheme. Our design uses synchronous DRAMs instead of standard EDO DRAMs and involves a novel controller scheme that allocates bus space for DRAM access efficiently. This efficient allocation allows us to reduce bus width from 64 bits to 32 bits, without significantly increasing embedded buffer sizes, and still meeting the requirements for MPEG2 MP@ML decoding. The bus arbitration algorithm is also simple allowing for a less complex controller design. Our main strategy is to impose a certain order in the DRAM access by the various processes instead of allowing any process to request for bus access arbitrarily. We also take advantage of the restricted GOP Žgroup of picture. sequence in the DVD format to allow a longer decoding time for B frames. The sub-picture pixel data are run-length compressed bitmaps that are overlayed on top of the MPEG reconstruction video. The architecture for sub-picture decoding is simple and easy to implement. In English ŽAuthor abstract . 6 Refs. EI Order Number: 98044166967 Keywords: Image compression; Decoding; Random access storage; Video signal processing; Algorithms; Image reconstruction; Standards; Storage allocation Žcomputer. Title: TWO-LEVEL PIPELINED SYSTOLIC ARRAYS FOR MATRIX-VECTOR MULTIPLICATION Author(s): Milentijevic, Ivan Z.; Milovanovic, Igor Z.; Milovanovic, Emina I.; Tosic, Milorad B.; Stojcev, Mile K. Source: Journal of Systems Architecture v 44 n 5 Feb 1998. Elsevier Sci B.V. Amsterdam Netherlands. p 383-387 ISSN: 1383-7621 CODEN: JSARFB Publication Year: 1998 Abstract: Novel two-level pipelined linear systolic arrays for matrix-vector multiplication are proposed. The number of processing elements in the proposed arrays is reduced to half of the number of processing elements in the existing arrays. An area-time ŽAT. criteria is used to compare the proposed arrays with the fastest existing one. In English ŽAuthor abstract. 4 Refs. EI Order Number: 98044164678 Keywords: Systolic arrays; Matrix algebra; Vectors; Calculations; Digital signal processing Title: HANDHELD DIGITAL VIDEO CODE DISTRIBUTOR USING EDGE-EMITTING LED’s AND SINGLE MODE OPTICAL FIBERS Author(s): Asada, Hideyuki; Rabou, Nabil Abd; Ikeda, Hiroaki; Shimodaira, Yoshifumi; Yoshida, Hirofumi Source: IEEE Transactions on Consumer Electronics v 44 n 1 Feb 1998 IEEE Piscataway NJ USA. p 155-162 ISSN: 00983063 CODEN: ITCEDA