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Common instruction mnemonics for microprocessors
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COMMONINSTRUCTIONMNEMONICSFOR MICROPROCESSORS
J.D. Nicoud Mini and Microcomputer Laboratory Swiss Federal I n s t i t u t e Lausanne,
of Technology
Switzerland
Abstract New, more consistent mnemonics are proposed for microprocessors. Explicit mnemonics and simple addressing rules make it much easier to read assembly programs. All the data transfer instructions have the general form "LOAD destination, source". Arithmetic instructions are "OP destination, source" (destination get destination OP source) and jump instructions "JUMP, test destination" or "CALL, test destination". Up to now, reference cards have been prepared for the Intel 8080 and Motorola 6800; they a r e oconvenient to use and allow occasional hand-assembling. Cross-assemblers on PDP-11 and NOVA minicomputers are available.
I. I n t r o d u c t i o n Microprocessors are becoming a common tool for the electronics engineer: more than lO different onechip microprocessors w i l l be available by the end of 1975, each one requiring different hardware and software. The choice problem w i l l not be easy; hardware c r i t e r i a such as cost, speed and system complex i t y are f a i r y easy to size-up; scanning the instruction set gives a rough idea of the possibilities of the microprocessor. But in order to really compare two microprocessors, i t is necessary to design a complete system with both machine, and write precise benchmarks, which may lead to various hardware/software trade-offs depending on the processor. This is d i f f i c u l t to do e f f i c i e n t l y now because of the rather considerable work implied in getting familiar with any of the new microprocessors: documentation is scarce, application notes nonexistent or incomplete, and mnemonics are very confusing. Hence most of the users l i m i t themselves to only one microprocessor and are just waiting for the promised software support and the announced new chips. I t is possible that in a few years a limited number of microprocessors w i l l have won the race, but until then i t w i l l be very d i f f i c u l t to find one's way in the microprocessor jungle, as far as efficiency and optimization are concerned. Hardware and software standards are needed, and this paper proposes to standardize the basic description of the instruction set, in terms of the assembly language mnemonics.
Two i n i t i a l motivations have triggered a search for more consistent mnemonics. The f i r s t one has been that the Intel 8080 mnemonics are very bad: many users (at least four to my knowledge) have modified these 8080 mnemonics on different ways when writing their own cross-assemblers. A lot of time is necessary to get familiar with these mnemonics, primarily because of the poor documentation and the lack of a quick reference card. The other motivation has been that various processors, for instance the Intel 8080, Motorola 6800, RCA COSMAC, Signetics 2650, Fairchild F8, etc. are designed for the same category of applications. Benchmarks for these processors should be written in a minimum amount of time by the same engineers concentrating on the particularities of the processors and not on t r i v i a l notation problems. This requires that the same mnemonics are used for the same functions. I t is evident that the use of standardized mnemonics is only a part of the need. Commonhigh level languages are also required, leaving the user with the l i b e r t y of choosing the best language for his application. 2. General c h a r a c t e r i s t i c s of mnemo-nics A microprocessor is characterized by i t s register organization and i t s instruction set, plus many p a r t i c u l a r i t i e s . Most of the notations can be standardized and the following notations seem to be very convenient for the most recent 8-bit microprocessors. Registers are named by simple letters A(accumul a t o r ) , B, C, ... or by l e t t e r R and a subscript i f there are more than few registers. Register pairs are designated by two letters AB, CD, SP (stack pointer), IX (index register) or by l e t t e r P and a subscript. Addressing schemes are named: - Absolute i f f u l l address is a part of the instruc tion (ex: LOADA, ADR) - Indexed i f address is relocated by an index register, with a possible displacement (ex: LOAD A,(IX)+DISP)
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- Relative i f the instruction gives the difference between the address desired and the present program counter value (ex: LOADA,.+lO) - Deferred i f the memory location reached f i r s t contains the desired address(ex: LOADA,~INDAD) Immediate i f instruction contains the data i t s e l f (ex: LOADA,# DATA). Usually, the programmer w i l l not e x p l i c i t e l y use relative addressing: the assembler i t s e l f w i l l decide which is the best way to reach the wanted location. This may cause some problems because of the usual limited range for relative addressing. As usual , a sometimes confusing i d e n t i f i c a t i o n is made between a register or memory location and i t s contents. Parentheses denote that the contents of a register are used as an address to point to a memory location (or i t s contents). Symbol of i n d i rection ~ has basically the same meaning as parentheses and is d i f f e r e n t because i t can be combined with them. ?(IX) means deferred indexed addressing. The instruction set may be divided in four categories: a) Data transfers between registers and memory b) Arithmetic c) Jump d) Misceleanous. a) The mnen~onic "LOAD" is mainly used in the f i r s t category, followed by destination and source registers or memory locations: LOADd,s. This unique notation has been preferred to the very often used "MOVE" for various reasons. The f i r s t one is that the "destination gets source" notation is widely used in mathematics and high level programming languages. The other is that in arithmetic operations also, the order destination-source is more natural. The store instruction is not used: no major d i f ference exists between registers, memories, and for some processors, peripherals; the old load/ store concept is of a limited interest with the new multiregister architectures. Exchange (EX) of registers, PUSH and POP on stack instructions are in the same category. Figure l gives a few examples of data transfer mnemo-nics for the Intel 8080 and allow comparison with the original 8080 mnemonics.
b)
Arithmetic instructions have the general structure "OP d,s", which means "destination device (register or location) gets the result of the operation between d and s". Almost every processor has the two-operand instructions ADD, ADDC (add with carry), SUB~ SUBC, AND, OR XOR, COMP (compare) and the one-operand instructions INC, DEC, CPL (Is-complement), NEG (negate, 2s-complement), RR (rotate r i g h t ) , RRC (rotate r i g h t with carry), RL (rotate l e f t ) , RLC, CL (clear) SET, TEST (update flags). The operand can be aregister or a memory location, or a single b i t of a status register; in that case, the b i t - l e t t e r is concatenated to the mnemonic to avoid confusion (ex: CPL A: complement register A, CPLC: complement b i t C). Jump instructions can be classified in three major categories: - Jump unconditionally and branch on condition - Call subroutine with or without condition - Return from subroutine with or without condition. Various notations for the corresponding mnemonics have been experimented. For instance, a jump to label ADDRi f previous result is positive can be written JP ADDR ( I n t e l ) ; BPL ADDR (Motorola); JPL ADDR; JUMP ADDR,PL; BRANADDR,PL; JMPPLADDR; JUMP/PL ADDR; JUMP,PLADDR; etc. Experienced programmers have an immediate preference, depending on the machine they are used to program. Novices prefer the most e x p l i c i t instructions, and since mnemo-nics are mainly intented for engineers without programming s k i l l s , the notation JUMP,PL ADDRhas been chosen.An other ad. vantage is that overall l e g i b i l i t y of the program is improved because the 7-1etter mnemo-nics of these important instructions make them appear clearly in a l i s t i n g ( f i g . 2). The objection that these mnemo-nics are longer to type and to p r i n t is valid, but the increase in time is negligible, specially i f compared to the time usually lost because of misunderstanding or confusing mnemonics. For instance, i t may seem that JPL is as clear and shorter than JUMP,PL.But the use of JPL implies the use of CPL in.place of CALL,PL, which in turn obliges the use of a less evident mnemonic for complement instruction. The use of jump
; E ~ I _ E OF INSTRUCTIONS: SEE INTEL BOOKLE[ "FR17~iCFIJ TO SF.#:TWAG~E", PAGE 17 ; Mi~NICS LO~I A,B
I N TEL
LOAD LOAD
A,#23. ;MVI A,4098. ;LDA
A,B A,23 4098.
LOAD LOAD LOAD
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A,M B
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POP EX JLW'IF'
AI-" ;POF' (SF') ,HL ;X'THL (I-IL; ; F'CFL
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;LOAD A WITH REGISTER B ;LOAD A WITH DATA IM~I)IATE 23 DECIMAL ;LOAD A WITH CDN[£NT OF MEMORYLOCATIO~I4098 ~LOAIJ A USIN~ PAIR HI_ AS AI)I~ES~ ;LOAD A USING FAIR BC AS ADDRESS ;LOAD A... ;..USING LOC 4098 [ECIMAL ;LOAD A AND FLAGS FROMSTACK ; E X C ~ T(]F' OF" STACKWITH HL ;LOAD PC WITH HI_ (JLIHP TO LOC AI)Br~ES~:~EII BY Hi.)
Fig. l. Comparison between m n e m o - n i c s and Intel mnemonics for some data transfer instructions.
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d) Misceleaneous instructions include mainly INP (input), OUT (output), ION (interrupt on), IOF (interrupt o f f ) , TRAP (software interrupt), NOP (no op, idle), WAIT (halt, wait for interrupt). Input and output instructions are in fact data transfer instructions, and they will appear as LOAD instructions in many microprocessors.However, i f the I/O transfer concerns only one accumulator, input and output instructions are convenient.
40210 40010 40310 40010
.LOC 37700 REAII:
TEST SKB JL~,SC R'EAD LOAD A,K~ AND A,#177 COil' A,#140 JU~',CS F~INT SUB A,#40 PRINT: TEST STT 3UtIP,SC PRINT LOAD TT,A
;TEST KEYBORD FLAG ;TEST AGAIN IF BUFFER MOT FULL ;READ KEYBOARD ;STRIPPARITY BIT ;TEST BIT FOR LOWER CASE ;JUMPIF ASCII COIE LO~-R THAN 140 ;CHA~. LO~ER TO UFI:~ZR CASE ;TEST F'RINTER FLAG ;TEST AGAIN IF NOT READY ;PRINT
RET .£N~
Fig. 2.
Sample source p r o g r a m for the Motorola
6800.
i n s t r u c t i o n , which looks d i f f e r e n t from other i n s t r u c t i o n s , has appeared to be very convenient. The mnemonic JUMP has been chosen f o r a branch i n s t r u c t i o n f o r two reasons: the same mnemonic CALL is used f o r " c a l l always" and " c a l l condit i o n a l " , hence i t is not consistent to have two d i f f e r e n t mnemonics f o r "jump ~lways)" and "branch (on c o n d i t i o n s ) " ; jump is preferable to branch because i t does not have to be abbreviated confusions and typing errors w i l l be less f r e quent. Hence, the mnemo-nics f o r the jump i n s t r u c t i o n s have one of the f o l l o w i n g forms: JUMP JUMP,XX CALL CALL,XX RET RET,XX
ADDR ADDR ADDR ADDR
Jump u n c o n d i t i o n a l l y to ADDR Jump i f t e s t XX true to ADDR Call routine ADDR Call i f t e s t XX true routine ADDR Return from subroutine Return i f t e s t XX true.
Various addressing schemes can be used, depending on the processor. Mnemo-nics f o r tests are preferably t w o - l e t t e r s , u s u a l l y giving a clear enough abbreviation ("VC" overflow b i t cleared, "GE" ~reater or equal, etc.#. These tests depend usually only on The values of the f l a g r e g i s t e r s which are not loaded at every i n s t r u c t i o n . I t is imPortant to think in terms of these f l a g s , which are often used f o r non-arithmetic operat i o n s : "SC" (sign b i t c l e a r ) is often used f o r t e s t i n g i f a peripheraT is ready and is equival e n t to "PL" (plus ( p o s i t i v e ) r e s u l t ) , which can a l t e r n a t i v e l y be used, and is preferable only i f the t e s t concerns a signed number. I t is necessary to be careful with the mnemonics of the a r i t h m e t i c tests f o l l o w i n g a compare or subtract i n s t r u c t i o n : " L T " (less than) applies to two signed numbers in 2s-complementary form (7 b i t s plus s i g n ) , "CS" (~arry ~et) m~ans also lower than, but f o r two 8 - b i t p o s i t i v e integers.
In each group other more special i n s t r u c t i o n s e x i s t , depending on the processor. The notation f o r these additional mnemo-nics is e i t h e r inspired from the mnemo-nics used f o r s i m i l a r i n s t r u c t i o n s or is ident i c a l to the o r i g i n a l manufacturer's mnemonics. Numerical values f o r addresses, i n s t r u c t i o n s and data can be w r i t t e n e i t h e r in octal or in hexadecimal. I f no habit p r e - e x i s t s , octal should be p r e f e r red f o r several reasons: i n s t r u c t i o n coding (handassembling) is more easy (see example in -~ 4); confusions between numbers and labels are avoided i f numbers do not include l e t t e r s ; octal numbers are also more easy to read and to type on a keyboard. The only drawback is the sometimes necessary conversion in two bytes, very easy to learn (see the acompanying I n t e l mnemonic reference card). 3.
Software
support
for
mnemo-nics
Changing the manufacturer's notations implies to w r i t e a new assembler, which may seem a considerable waste of time. However, software support provided by the microprocessor manufacturers is up to now very weak, not cheaply a p p l i c a b l e , and very often not adapted to user's need. I f the user wants to change from one processor to another , not only the mnemonics change, but also the assembler, e d i t o r and debugger r u l e s , and a new microcomputer may have to be bought. Some standardization is necessary at a l l these l e v e l s . 010763 010703 010704 010705 010706 01070,9 010707 010710 0i0?10 Q16711 010712 010712 010713
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Sample of program for the Intel 8080, assembled with the PDPI1 (compare with fig. 2).
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When debugging a program, changes or replacements of instructions can often be made directly in the memory, reducing the number of consecutive assemblings, and saving time. Instruction l i s t in numerical order ( f i g . 5 and 7 ) is very useful when checking memory contents. Examples of figure 8 show more samples of programs, written for the Motorola and the Intel 8080. The ease of reading an assembly program written with mnemo-nics is evident and allows the programmer to use more significant comments and make the program more easy to understand.
The use of the macroassembler of a minicomputer allows to write rather easily a cross-assembler for a microprocessor. Few of the symbols chosen for the mnemo-nics may seem d i f f i c u l t to be recognized by a given macroassembler. I t is however always possible, by using a more complex analysis of the instruction: the convenience of a l l the users of the assembler is more important than some saving of time of the programmer writing once the assembler. Intel
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the two devices. The conventions for the stack, restart and interrupt procedures are also summarized in order to quickly remove all the hesitations which may suddenly appear, especially i f one has formerly studied many processors.
The Mini and Microcomputer Laboratory of the I n s t i tute of Technology of Lausanne is working in that direction. The mnemo-nics have been used for several months and they have proved to be very easy to learn and convenient to use. Up to now, Intel 8080 and Motorola 6800 instruction sets have been converted in mnemo-nics and cross-assemblers have been written for both, using both the macroassembler of the RT-II (or DOS) on a PDP l l / 4 0 and the macroassembler on a Nova. Figure 3 gives an example of an assembly l i s t i n g typed by the cross-assembler running on PDP I I . Later this year, resident assemblers w i l l also run on the microprocessor i t s e l f . Similar work w i l l be done for the RCA COSMAC, Signetics PIP, Intel 4040, etc., as soon as these processors w i l l be available to us.
4.
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5. Conclusion Multiplication of equipments and users implies some standardization. This has (more or less) been done for integrated c i r c u i t s , peripherals and high level languages. I t has s t i l l to be done for assembly languages. Even i f i t may take some time before the manufacturers commit themselves to any standard, i t w i l l happen because the users w i l l have to get familiar with various microprocessors and they need to have their work done simpler, faster and more efficiently.
8080 and Motorola 6800 mnemo-nics
The i n s t r u c t i o n reference card f o r I n t e l 8080 ( f i g . 4 ) and Motorola 6800 ( f i g . 6 ) microprocessors are primar i l y machine i n s t r u c t i o n reference cards. They cont a i n a l l the necessary i n f o r m a t i o n about the processor, to the programmer's point of view, with of
The attempt presented in this paper has widely benefited from the work done by Rick Merrill from Digital Equipment (Maynard, Mass.) and Mike Lindheim~r from Analog Devices (Westwood, Mass.). The author is also very grateful to G~rard Gris and Ren6 Sommer from the Swiss Institute of Technology (Lausanne) for their expert work in writing the software support for the mnemo-nics.
course a l o t of evident definitions and conventions not e x p l i c i t e l y mentioned. Register organization, with symbols used for registers, register pairs and status bits are the f i r s t things to get familiar with. Instructions themselves are easy to understand. For the detailed effect of some instructions (e.g. test, s h i f t ) , i t may be necessary to check the manufacturer's complete description.
Hand assembling and disassembling is very easy, espe- ~ ;HO~STHEUIFFE~HC~S ~ T ~ - ~ N I ~ 4 ~ T ~ A ~ : . M 4 ~ N I ~ c i a l l y in octal. For instance: S.'~,L(~ ~,,ST~C~ ;LBS #ST~ ;L(W~ &F WIIll ION LOAJ) LO(4J JUttP, EO LOAb COf~ J U t ~ M; C~. INC LO#4# AD[W~ JLk~, HI ~JB
INTEL 8080 LOAD A,(HL) = 100+70+6 = 176
One byte i n s t r :
Load A with content o f l o c a t i o n a d d r e s s e d by HL
MOTOROLA 6800 LOAD A,(IX)+8 = 206+0+40=246
Two-byte i n s t r :
Load A with the c o n t e n t o f l o c a t i o n a d d r e s s e d by I X (indexed by I X w i t h o u t d i s p l a c e m e n t )
Two-byte i n s t r :
S u b t r a c t to A n u m b e r 31
MOTOROLA 6800 SUB B,#31 = 200+I00+0 = 300 Two byte instr: S u b t r a c t to B n u m b e r 31.
The sequence for the low order and high order byte of a 16-bit word stored in the memory appears clearly on the programming sheet: i t is different for
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ISPHL
0D6 7 ~o6 10
MVI r MVI M
ivIOV rl. r: 1DS MOV r.M 1D6 MOV M.r 16S
ORIGINAL MNEMONICS
~57
~el
166
363
373
323
333
~7
¢77
g47
4
4
(71
4
4
10
10
4
4
~
~
~
~
~ ' ~
~
~
~
~
[ T ~
~
4
4
[T~]
~
~
4
4
4
L
¢. . . . .
j f
J
J 250+J L. . . . .
ADDC. A ~ I
ADD= A~r
ADDAHL~o
DEC, p
Subtract with carry (S.Z.X,P, C can change)
Subtract (S, Z, X. P. C can change)
Add with ¢w'rv (S. Z, X, P. C can chenge)
OR
OR.A..
NOP
WAJT
IOF
ION
OUTAn
INP~R
SETC
OPLC
D/UIL
RRCAA
RR=A
RLCAA
RL=A
CPLAA
P
E H
SP
HL
OE
8(:
6e (HL) 711 A
I~" L
~" 4e
B C
$
8
I~m.~"..)
,m
7 A
H L
,HLI
~ ~
1 c
2" O 3 E
;
NO operation
Wait for interTOpt (halt)
Inte'rupt off
Intcvrupt on
Output tO periphesel n
I nl:lUt to acc. f fore pii'iphecel n
Setc, erry ( C = 1 )
Complement the cirry (C = (~)
Decimel adjt.~t i¢¢.(S, Z. X. P. C can change)
Rotate right Icc. with carry (C = A I )
Rotete right ecc. (without cacry) (C = AID)
Rotate left acc. with carry (C = AT)
Rotate left acc (without carry) (C m AT)
Complemem the acc.
h
( Z = I if A = s , C = 1 if A < s , S . X. Pcan change)
Compare (A - s )
(C = (D. S, Z, p can change)
Exclusive 0 R (C = (~. S. Z. p can chlmge)
(C = 0, S, Z. P can chenge) XOR= A65
COMPs A~a
I
; ;
d
el te
m
Add to Accumulator register, location Or numb~ = (S, Z. X. P. C con change)
Add to HL the pairp (S. Z, X. P do not change)
Decrement pairp (S. Z. X. P. C do not change)
Increment pair p (S, Z, X. P, C do not change)
Decrement d (S, Z, X, P can change)
Increment reQister Of location d (S. Z. X, P can checRe)
AND.A. And
SUBC.A,#
I SUBAAa$ J
i
~ I . .L. . - J
~--~ L. . . . .
~
i
~
[ ~
INC=p
DEC=d
INC~d
MNEMONICS
Can be reproduced with a,Jthoriz~uon of LCD EPFL. Bellw~ve16. CH 1007 Ll~wnne
NOP
HLT
DI
El
OUT
IN
STC
CMC
DAA
~137
¢17
RRC
~7
027
RAR
4
7
2iS 216 316 7 22S ,,4. 226 ' 4 326 4 23S 236336 4 7 24S 246 346 7 25S 2r~6 356 7 2~ 266 366 7 27S 276 376 7
20S 206
RAL
RLC
CMA
ANA r ANA M ANI XRAr SRAM XRI ORAr DRAM ORI CMP CMPM CPI
AOC r AOCM ACI SUB r SUB M SUI sen r ~l~lBM
ADD r ADD M ADI
~)03 ¢23 943 OB3 913 e33 ~53 1~73 I)lt (~31 (~51 @71
~O5 ~65
DCR r INRM INX S INX O INX H INX SP OCXB DCX D DCX H OCX SP OAOB DAD O OAO H OAOSP
~D4 e164
INR t INR M
ORIGINAL80~0 MNEMONICS
I
o~
I
- 27MICROCOHPb'TF.R LAIk"NRATORY
MINI
SHISS FEDERAL INSTITUTE OF TFO-INOI.O6Y
INTEL
8080
MNEMO-NICS
(LCD EPFL) ¢ " 0 )NOP 1i 41 i l O l A IZ l LOAD BC,~m ILOAD (BCI,A 42 102 B 43 103 c 3 ~ : INC BC 44 104 D ¢ INC B 45 1p5 E { DEC B 46 ] 0 6 l F n ',LOAD B,~n 47 Ip7 G e IRL A 48 49
ADD HL,BC }, LOAD A,(BC) I~ !iDEC BC u iINC C DEC C LOAD C,,~n w RR
12 13 14 15 1B 17
4A 4B 4C 4D 4E 4F
A
50 51
p o LOADDE,~ 22 LOAD (DE),A 23 u INC DE 24 INC D 25 X. DEC D 26 i LOADD,~n 27 = RLC A
e8 210 '~ i ADOC A,B 89 211 F: 'iAOOC A,C 8A 212 X )ADDC A,D
120 P LOADD,B 121 0 LOADD,C 122 R LOADD,D !.123 S LOADD,E 1124 T LOADD,H 125 U LOADD,L 126 v LOADD,(HL) W LOADD,A
220 ~ SUB A,B 221 ~ SUI3 A,C 222 -r SUB A,D
DEC DE INC E DEC E LOADE~n RRC A
i LOAD m,HL
NC HL
INC H DEC H & LOADH,=~n ' DAA ( ADD HL,HL LOAD HL,m DEC HL INC L DEC L LOAD L,#n CPL A
3O 31 32 33 34 35 36 37
3B
3A 3B 3C 3D
it k Z m n o
6¢ LOAD SP,#m 2 2 LOADm,A 3 3 INC SP 4 4 IRC (HL)
r
5 5 DEC (HL) 6 6 LOAD (HL),~n 7 7 SETC
4
5 6
7
Octal
t
7A 7B
< INC A
II17c
DEC A ; LOAD A,#n ? CPLC ,
i
~[uemo-nio
Fig. 5.
:
172 73 174 75
7E 176 F 177
z { I }
311
r.) RST
0
:Z ) RET
CB 313 ~ i
cc co CE CF
314 CALL,EQ 315 i CALL 316 I~ AODC 317. U RST
m in A,,~n
1@
DO 320 RET,CC D1 321 POP DE 02 .~ JUMP,CC m D3 OUT n ) CALL,CC m I U PUSH DE
224 ~ SUB A,H 225 ~ SUB A,L 226 ~ SUB A,(HL)I 227 ~ SUB A,A 2361 231 232 233 234 235 236 237
~ I POP BC 1i i JUMP,NE m d i JUMP m Q~ CALL,NE m ~ I PUSH BC P:! ADD A,,n
CA 312 J() JUMP,EQ m
ADDC A,E ac 214 v ADDC A,H SO 215 ADDC A,L i BE 216 -~ ADDCA,(HL). 217 W ADDCA,A
223 u SUB A,E
RET,NE
(,
)~. SUB A,+n k~ RST 20 RET,CS
~ SUBCA,B
~ SUBC A,C "
SUBCA,D SUBC A,E ; SUBC A,H t~ SUBC A,L E SUBCA,(HL: ~- SUBCA,A
JUMP,CS m ;INP
n
IS CALL,CS m . ! RST
A,*n 30
i~
m
SUBC I
LOADtI,B
LOAD H,C
LOAD L,B LOADL,C LOAD L,D LOADL,E LOADL,H LOADL,L LOADL,(HL) LOADL,A
LOAD (HL),D LOAD (HL),E LOAD (HL),H LOAD (HL),L WAIT LOAD (HL),A
~8 1 9 ADD HL,SP 2 z LOADA,m 3 ~ DEC SP
J)O
RET,EQ C9
BB 213
LOADE,B LOADE,C LOADE,D LOADE,E )LOAD E,H LOADE,L LOAD E,(HL) LOAD E,A
p LOAD(HL),B' q LOAD(HL),C
61
I
i cl ; c2 ) c3 l C4 ! c5
240 i :AND A,B 241 ~ AND A,C LOAD H,D 242 "~ :AND A,D c LOADH,E 243 :~ AND A,E d LOADH,H 244 AND A,H e LOADH,L 245 ~ AND A,L •f LOADH,(HL) 246 & AND A,(HL) LOAD H,A A7 247 ' AND A,A
i
iLOAD HL,Om ~
l e l | ?O1 ~ ADD A,C B2i202 y ADD A,D 83)203 ADD A,E 841204 ¢ . ADD A,H
H I J K L
x Y Z [ \ ]
,
301 302 LOADB,D 303 LOAD B,E 304 LOAD B,H 85:205 ADD A,L 305 LOAD.B,L LOADB,(HL) 86 206 fi ADD A,(HL)I c6 306 87 207 o !ADD A,A C7 307 LOADB,A
LOADB,C
LOADC,B LOADC,C LOADC,D LOADC,E LOADC,H LOAD C,L N LOADC,(HL)I 0 LOADC,A
llO 111 ll2 If3 ll4 I15 If6 I17
,/~ADD HL,DE + ', LOAD A, (DE) ÷ + £
,
l
A8 A9
AC AD AE AF BO B1 B2 R3 B4 BS B6 B7
LOAD A,B LOAD A,C B9 LOADA,D LOADA,E LOADA,H BC LOADA,L LOAD A,(HL) RE
I LOAD A,A
MCM6571 Character ~enerator
250 (
251 :): 252 ~r 253 254 , 255 ~ 256 ~ 257
i
(sP) ,HL g f~
°:
f
XOR A,B XOR ..A,C XOR A,D XOR A,E XOR A,H XOR A,L XOR A,(HL) XOR A,A
)
HL A,4n
,,
RET,PE (HL) l JUMP,PE m
,t
m
356 ~ XOR
357
RST
370 371
RET,MI
A,+-n
5¢ 36~L ~ RET,PL 361 POP AF 362 JUMP,PL m 363 IOF 364 EI CALL,PL m 365 PUSH AF 366 OR A,..~n 367 RST 60
A,B z6~ ~I: i OR A,C 262 .~ fOR A,D 263 _3 i OR A,E 264 4 i OR A,H A,L 265 ~)OR 266 ~ OR A,(HL) 267 Z OR A,A 260 g. OR
270 ~ COMPA,B 27] .~ COMPA,C 272 -'. i COMPA,D
273 ~ COMPA,E ~ COMPA,H - COMPA,L > I COMP A,(HL) ~ COMPA,A
373 374 375 376 377
274[ 275 i 276j 277
~I
Hexadecimal
Intel 8080 mnemo-nic instruction list.
LOAD ST,HL JUMP,MI m ION CALL,MI m CONP
A,+n
RST
7e
e
17.2.75
-
MINI AND MICROCOMPUTER LABORATORY SWISS FEDERAL INSTITUTE OF TECHNOLOGY OF LAUSANNE (LCD EPFL)
MICROPROCESSOR REFERENCE CARD
Low byte
~oXl,l
316
L---J L---J
tab or comma)
t LSB[
m
......
I
I .........
v= ~,L[4-E []'x
~
16-bit number
....
T o p m e m o r y asslgnmenI
LOAD~d~s
(sz.
t I
I nt~'rupt : IDF General save on stack. load of interrupt address
~E~[]~ li~
Octal
~ L_--J L_--J
ii,llX,l,Slz,v,c
INSTRUCTIONS (MNEMO-NICS)
! Deviations with 6800A
2 Hexa
REGISTER O R G A N I Z A T I O N
a~,~,hawJr,v
. . . . . .
MPUCycles(~' I ~zsfcycle) $ U)*AdO~ LD~AIX~ ~DAeI=P
-
MOTOROLA MPU 6800B
F=q ........ I ~DAA~e~
28
:?,.~: .....
r--. . . . .F. IL
B
~-
~
k- -{---A
F,~,
~
AL, B
INTERRUPT
177770
....
171777 HIxa
STAA~m S~AAIe, ST~X~
[L -•- - J' 7 ~•
L___
L___J
S~S~m
LOAID~d~; -I
L---J
withs (sz, v
= 0)
026
[BA
021
rAP
~6
[
FPA
~7
I]'~
~
~
]
,×~
065
~
DEC~SP~IX
Load SP with IX and decrement
16bits
]-SX
0e~
~
INCaIX~SP
Load IX with SP and increment
F~JRA PSRB
~66 ~B7
[ ~ [ ' 0 " ~
PUSHed
Pushd . . . . . . k
[T3"~ ~6"-~
POP~d
Pupal on stack ~ - -
~ [[~] [ ] , x [[~]i ~ ; ]
~. . . . . . indexed
II~ 6 Ill~'~'~ I
TAB
..i,.,0,.~,l L g IGI~ ~,*teod,,0~
n~
~OAOo.oA
LoadBwithA {SZ.V =0)
~
LOAO~A~8
Load A with B (S,Z, V = 0)
~
LOAD~F~A
Load status reg F with A
1"0~
LOADaAaF
Load A with status reg F
~
ADD~d~s
Oc~l
Add d with $, result in d (XSZVC. . . . hange)
sP
PULA PULB
SEC
0t5
:LC
014
~EV
013
~LV
~
~c.m
su.:o,,o,
'
'1
SETC
Set carry bit (C = I) !
CLRC
Clear carry bit (C = ~}
~
SETV
Set overflow b,t {V
012
[]'~-[]
~
CLRV
CI . . . . . . .
BCC
044
~
~
JDMPACC~.+." Jump if carry clear (C = 0) (jump if greater or equal *}
# m l l XSP)
3CS
045
~
~
'DMP.CS..+n' Jump ff carry set (C = 1)
8 b~is{d,r~t I
~LS
043
~
~
JUMP. LS..+tr Jump if I. . . . . . . . . .
~HI
042
~
~
JUMP~HI. +n Jump if higher (C + Z = @)
~NE
046
~
~
JUMP~NE~.+n' Jump if not equal . . . . (Z = @) JUMP~ZC~ +n' Ilump if zero bil clear)
BEQ
047
~
~
JUMP^EO~ .+n' Jump if equal (Z = 1) JUMP^ZS ~.+n' (jump if zero bit set)
.' ,sa 2............ d~pl~emenl ( 176to ~201)
BPL
052
g2 A~2 ~
JUMP.Pt.,+n, Jump if plus (S = , ) JUMP~SC~.+tr (jump if sign bit clear)
............
BMI
053
~
JUMP~MI^.+n' Jump if . . . . . (S=11 JUMP~,SS~.+n" (jump if sign bit set)
BGT
~56
BGE
054
BLE
057
8LT
055
BVC
05~
Bvs
051
A
~
ORBm
~
ANDodo*
And (SZ, V
OR~d~s'
O,
$
= ~)
{SZ, V = (~) (SZ, V = 0 )
(e~lended) ~t-~[]
2 Q~5* c*x.,
~
Bit test (d and s) (SZ. V = 0)
~
~
COMP~IX~x
CompareIndexreg wrth S (IX s) (16 bits} (SZVC)
ADD~A~B
AddAandB(A~A+B)
ABA
033
SBA
020
CBA
021
OAA
031
INX
~10
II ~ e I] I ~ ~ ~ I ,.co,x
, ........ ,o0~:~ reg ~
DEX
011
o .......
INS
061
II e~ I11~ ~ I DE~o,x [I 3~ IIN6" 1 'NC~SP
o .......
II~ellle~l,u,oA~ ~
DAA
(XSZVC)
su~..... Aaod~A~A-~,~ZVC~ Decimal adjust ACC A (SZVC)
,
064
II 3 4 l] l e 6 4
117 137 177 t57
114 F'I] l i i 7"J C, Ro~ L:zzd ~:::d
C,e.rd(S=e.Z = f . V = e . C = ~ )
COMA
103
II 4 3"111 i ~]'1 c,,,,
~omp, . . . . . . .
.L._. _. ._.J. . . .
L__-
NEGA
1~ L-----J
L------J
DECA
112
114 A'[I I~ ~ 2"1 o z c ~
INCA
t14 I
If4 cfll Ill 4"1 ,NC~#
~___J
J
[I 4 9"1] I ~ 1 1"1 RLC.d
I11
.......... 106
I146"11
I
ASL
ne I
ASR "
107
kSn
104
TST
115
t:::d
fi~6:/RR¢~, r_: : : .
JUMP,GE ..+n' Jump ,f greater or equal *" (S + V = (~)
Jumpd,...... ~
~
JUMP~ LTr '+n' Jump z e f o " (dS I. .+. . V. =hart ') ~
JUMP.VC . + n ' Jcr,:rp(,vf o:e(~;Iow
,UMP vs .umpdoorfow set (V = I)
(SZ.V = @.C = ~)
~]~O~J~
B
BRA
~4~
I ~
~
JUJPn.+n'
Jurnp relative (displa(enlerll n bytes)
(SZ.C = I i f d = ~ V = 1 d d = 2~(~}
~
mar~lule
BSR
2~5
~
~
CALLA.,n'
b .r .o. u.on C .t i nsta{k) e(pc
~........
'T~ ~
JMP(EI JMP(I)
176 156
JSR(EI JSRN)
275 255
~
~
CALLt,/
Call subroutine (PC on stack)
,......... (SZ, V = l d d =
I
(extendedl
........ /
177.)
R..... ,el, with ..... (s~c. v : s + c~
~
P
~
~1
. i ~ [ ]
(e.t eacled) ......
,ndexed
RTS
e71
~
nET
RTI
073
~
RTI
SWI
077
[ [ ~
~
TRAP
WAI
076
I]'~ E ~
~
WAIT
CLI
016
~-]]
~
ION
Return from subroutine (PC from stack) Return from interrupl (F, 8, A. IX. PC from stack) Sol . . . . . . . . . . . . pt (trap, (PC, I X. A, B, F on sti~ck, l = l ) Walt for i . . . . . . pt (halt) (no DMA, registers already on stack) I . . . . . . pt ON (I = 0)
(SZ, C = g , V = S + C]
SEI
017
Test d (load S and Z . . . . d,ng tod) (sz, c = (~. v = @)
NOP
6'~2
~
NOP
N o operation
. . . . . . . . g. . . . . h . . . . .
{szc. v =s + o
Arithmeticshdl left (SZC. v = S + C)
I 114 D ' I I / ' ]'~)+"=J TEST." I ~ -. - -. d . . . t -.- - - ~
~
A
~--:~
~--Z :~
~
~he, COMPor SUE{,nslru{hun * * 2scomplement UbliS nun,~rs i 7 b,ts + Sl#,/) abe, CC)MPor SUB ............
i,~Tj L~J
1
I148fll I' ! ~'1 ~o" 1 ~~.1 ASR~d [IL - 4- _ 7*_ ~I][L_----~
I
Stack p . . . . . .
L-----~
~-_-_-~ E - : Z
JUMP~G Ta .+n' Jump if greater • * (Z + (S + V) = (~)
equal**(Z + (S + V) = 1)
I .......... Stack p . . . . . .
DES
J
~
index ,eg (Z) '
CLRA CLR8 CLR(E CLR(I:
1 o~c.sP
*(C+Z=,)
., .~. d. .~. . .
¢.P~m
nORA
= I)
flow bit (V = 0)
(SZVC)
z~
ROLA
B
[ ~
o '
sub.~tw.b .....
sPd
~
d ~II~] [ ]
(SZVC)
/
.
[]~']]
s.0 . . . . ( . . ,
su~.m
~. -.- -.
[~-~-~-O
Arithmetic shift right (SZC. V = S + C}
q~
February t975
Can be reproduced with authonzat,on of LCO EPF L, Bellerive I6. CH 1007 Lau~nne
Fig. 6.
Motorola
6800 m n e m o - n i c reference card.
-
MINI
AND
29-
MICROCOMPUTER LABORATORY
r,INEMO-N I CS
MOTOROLA 6800
SWISS FEDERAL INSTITUTE OF TECHNOLOGY (LCD EPFI.) 0 I
B
2 3
y
4
£
NOP
5
6 7
n e
LOAD LOAD
F,A A,F
I0 11 12 13 14 15 16 17
I INC K DEC CLRV p SETV v CLRX SETC 0 IOF ION
IX IX
20 21 22 23 24 25 26 27
p o
A,B A,B
30 31 32 33 34 35 36 37
SUB COMP
T
¢ LOAD w LOAD
B,A A,B
~ AA ÷
ADD
18 ~.9 ~A IB ~D ~E ~F
U
X
IO ;1 12 t3 14 ~5 ~,6 ~7
A,B
÷
EG A
PL A SR A RC A .SR A ,SL A :LC A ~EC A NC A EST A :LR A
50 51 52 53 54 55 56 57
IEG B
58 59 5A 5B 5C 5D 5E 5F
kSL B {LC B )EC B
~EG (IX)+n
',PL B .SR B ~RC B ~SR B
[NC B FEST B "LR B
4O 41 42 43 44 45 46 47
JUMP,HI .+n' JUMP,LS .+n' $ JUMP,CC .+n % JUMP,CS .+n JUMP,NE .+n JUMP,EQ .+n
GO 61 62 63 64 65 66 67
50 51 52 53 54 55 56 57
JUMP,VC JUMP,VS JUMP,PL JUMP,MI JUMP,GE JUMP,LZ JUMP,GT JUMP,LE
.+n .+n .+n .+n .+n .+n .+n .÷n'
68 69 6A 65 6C 6D 6E ,SF
%SL (IX)+n ~LC (IX)+n )EC (IX)+n
60 61 62 63 64 65 66 67
INC INC POP POP DEC DEC PUSH PUSH
IX,SP SP A B SP SP,IX A B
70 71 72 73 74 75 76
IEG m
70 71 72 73
JUMP
.+n'
"
78 79 7A 76 7C 70 7E 7F
RET RTI
74 75 76 77 Octal
77
WAIT TRAP ~nemo-nlc
Fig. 7.
:PL .SR
(IX)+n (IX)+n
~RC (IX)+n ~SR (IX)+n
[NC (IX)+n rEST (IX)+n ;LR
(IX)+n
691211 BA I 212 8B I 213 Bc I 214 BD 1 215 BE I 216 8F 1 217 901220 91 t221
921222 931223 941224 951225 951226 971227 981230 99 J 231 9A I 232
98 1233 9c I 234 9D1235 9E1236 9F1237
XOR B,~n ADDC B,~n OR B,~ n ADD B,~n
SUB A,n COMP A,n SUBC A,n
DO DS D2 D3 D4 D5 D6 D7
SUB B,n COMP B,n SUBC B,n
D8 D9 DA DB OC DD DE DF
XOR B,n ADDC B,n OR B,n ADD B,n
EO El E2 E3 E4 E5 E6 E7
SUB B,(IX)+n COMP B,(IX)+n SUBC B,(IX)+n
E8 E9 EA EB EC ED EE EF
XOR B,(IX)+n ADDC B,(IX)+n OR B,(]X)+n ADD B,(IX)+n
FO F1 F2 F3 F4 F5 F6 F7
SUB B,m COMP B,m SUBC B,m
F8 F9 FA FB FC FD FE FF
XOR B,m ADDC B,m OR B,m
AND A,n BIT A,n LOAD A,n LOAD n,A XOR A,n ADDC A,n OR A,n ADD A,n COMP IX,n LOAD SP,n LOAD n,SP SUB A,(IX)+n COMP A,(IX)+n SUBC A,(IX)+n
A8 A9 AA AB AC
250 251 252 253 254
XOR A,(IX)+n ADDC A,(IX)+n OR A,(IX)+n ADD A,(IX)+n COMP IX,(IX)+n
AD AE AF
255 256 257
LOAD SP,(IX)+n LOAD (IX)+n,SP
BO 61
26C 261
B2 63 64 65 B7
~SL m RLC m DEC m
68 69 BA BB BC BD BE BF
27C 271 27~ 273 274 275 27E 27)
MCM 6571 Character generator
ca c9 CA CB CC CO CE CF
AND A,#n BIT A,.in LOAD A,~.n
A01240 AI1241 AZl 242 A3! 243 A4! 244 A51245 A6 246 A7 247
86
CLR m
XOR AJn ADDC A,~-n OR A,~n ADD A,~n COMP IX,Im CALL .+n' LOAD SP,Im
B8 1 210
RRC m ASR m
INC m TEST m
SUB B,,#n COMP B,~n SUBC B,|n
SUB A,~n COMP A,+n SUBC A,-~n
262 263 264 265 266 26;
tPL m LSR m
CO CI c2 c3 c4 c5 c6 c7
~O I 200 ~i I 201 ~2 1202 63 I 203 ~4 t 204 65 I 205 66 I 206 ~7 I 207
AND A,(IX)+n BIT A,(IX)+n LOAD A,(IX)+n LOAD (IX)+n,A
SUB A,m COMP A,m SUBC A,m AND A,m BIT A,m LOAD A,m LOAD m,A XOR A,m
ADDC A,m OR A,m ADD A,m COMP IX,m
LOAD SP,m LOAD m,SO
AND B,~n BIT B,~n LOAD B,,n
LOAD IXdm
AND B,n BIT B,n LOAD B,n LOAD n,B
LOAD IX,n LOAD n,IX
AND B,(IX)+n BIT B,(IX)+n LOAD B,(IX)+n LOAD (IX)+n,B
LOAD IX,(IX)+n LOAD (IX)+n,IX
AND B,m BIT B,m LOAD B,m LOAD m,B
ADD B,m LOAD IX,m LOAD m,IX
t
Hexadecimal
Motorola 68oo mnemo-nic instruction list.
17.2.75
22
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COMMONINSTRUCTIONMNEMONICSFOR MICROPROCESSORS
J.D. Nicoud Mini and Microcomputer Laboratory Swiss Federal I n s t i t u t e Lausanne,
of Technology
Switzerland
Abstract New, more consistent mnemonics are proposed for microprocessors. Explicit mnemonics and simple addressing rules make it much easier to read assembly programs. All the data transfer instructions have the general form "LOAD destination, source". Arithmetic instructions are "OP destination, source" (destination get destination OP source) and jump instructions "JUMP, test destination" or "CALL, test destination". Up to now, reference cards have been prepared for the Intel 8080 and Motorola 6800; they a r e oconvenient to use and allow occasional hand-assembling. Cross-assemblers on PDP-11 and NOVA minicomputers are available.
I. I n t r o d u c t i o n Microprocessors are becoming a common tool for the electronics engineer: more than lO different onechip microprocessors w i l l be available by the end of 1975, each one requiring different hardware and software. The choice problem w i l l not be easy; hardware c r i t e r i a such as cost, speed and system complex i t y are f a i r y easy to size-up; scanning the instruction set gives a rough idea of the possibilities of the microprocessor. But in order to really compare two microprocessors, i t is necessary to design a complete system with both machine, and write precise benchmarks, which may lead to various hardware/software trade-offs depending on the processor. This is d i f f i c u l t to do e f f i c i e n t l y now because of the rather considerable work implied in getting familiar with any of the new microprocessors: documentation is scarce, application notes nonexistent or incomplete, and mnemonics are very confusing. Hence most of the users l i m i t themselves to only one microprocessor and are just waiting for the promised software support and the announced new chips. I t is possible that in a few years a limited number of microprocessors w i l l have won the race, but until then i t w i l l be very d i f f i c u l t to find one's way in the microprocessor jungle, as far as efficiency and optimization are concerned. Hardware and software standards are needed, and this paper proposes to standardize the basic description of the instruction set, in terms of the assembly language mnemonics.
Two i n i t i a l motivations have triggered a search for more consistent mnemonics. The f i r s t one has been that the Intel 8080 mnemonics are very bad: many users (at least four to my knowledge) have modified these 8080 mnemonics on different ways when writing their own cross-assemblers. A lot of time is necessary to get familiar with these mnemonics, primarily because of the poor documentation and the lack of a quick reference card. The other motivation has been that various processors, for instance the Intel 8080, Motorola 6800, RCA COSMAC, Signetics 2650, Fairchild F8, etc. are designed for the same category of applications. Benchmarks for these processors should be written in a minimum amount of time by the same engineers concentrating on the particularities of the processors and not on t r i v i a l notation problems. This requires that the same mnemonics are used for the same functions. I t is evident that the use of standardized mnemonics is only a part of the need. Commonhigh level languages are also required, leaving the user with the l i b e r t y of choosing the best language for his application. 2. General c h a r a c t e r i s t i c s of mnemo-nics A microprocessor is characterized by i t s register organization and i t s instruction set, plus many p a r t i c u l a r i t i e s . Most of the notations can be standardized and the following notations seem to be very convenient for the most recent 8-bit microprocessors. Registers are named by simple letters A(accumul a t o r ) , B, C, ... or by l e t t e r R and a subscript i f there are more than few registers. Register pairs are designated by two letters AB, CD, SP (stack pointer), IX (index register) or by l e t t e r P and a subscript. Addressing schemes are named: - Absolute i f f u l l address is a part of the instruc tion (ex: LOADA, ADR) - Indexed i f address is relocated by an index register, with a possible displacement (ex: LOAD A,(IX)+DISP)
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23-
- Relative i f the instruction gives the difference between the address desired and the present program counter value (ex: LOADA,.+lO) - Deferred i f the memory location reached f i r s t contains the desired address(ex: LOADA,~INDAD) Immediate i f instruction contains the data i t s e l f (ex: LOADA,# DATA). Usually, the programmer w i l l not e x p l i c i t e l y use relative addressing: the assembler i t s e l f w i l l decide which is the best way to reach the wanted location. This may cause some problems because of the usual limited range for relative addressing. As usual , a sometimes confusing i d e n t i f i c a t i o n is made between a register or memory location and i t s contents. Parentheses denote that the contents of a register are used as an address to point to a memory location (or i t s contents). Symbol of i n d i rection ~ has basically the same meaning as parentheses and is d i f f e r e n t because i t can be combined with them. ?(IX) means deferred indexed addressing. The instruction set may be divided in four categories: a) Data transfers between registers and memory b) Arithmetic c) Jump d) Misceleanous. a) The mnen~onic "LOAD" is mainly used in the f i r s t category, followed by destination and source registers or memory locations: LOADd,s. This unique notation has been preferred to the very often used "MOVE" for various reasons. The f i r s t one is that the "destination gets source" notation is widely used in mathematics and high level programming languages. The other is that in arithmetic operations also, the order destination-source is more natural. The store instruction is not used: no major d i f ference exists between registers, memories, and for some processors, peripherals; the old load/ store concept is of a limited interest with the new multiregister architectures. Exchange (EX) of registers, PUSH and POP on stack instructions are in the same category. Figure l gives a few examples of data transfer mnemo-nics for the Intel 8080 and allow comparison with the original 8080 mnemonics.
b)
Arithmetic instructions have the general structure "OP d,s", which means "destination device (register or location) gets the result of the operation between d and s". Almost every processor has the two-operand instructions ADD, ADDC (add with carry), SUB~ SUBC, AND, OR XOR, COMP (compare) and the one-operand instructions INC, DEC, CPL (Is-complement), NEG (negate, 2s-complement), RR (rotate r i g h t ) , RRC (rotate r i g h t with carry), RL (rotate l e f t ) , RLC, CL (clear) SET, TEST (update flags). The operand can be aregister or a memory location, or a single b i t of a status register; in that case, the b i t - l e t t e r is concatenated to the mnemonic to avoid confusion (ex: CPL A: complement register A, CPLC: complement b i t C). Jump instructions can be classified in three major categories: - Jump unconditionally and branch on condition - Call subroutine with or without condition - Return from subroutine with or without condition. Various notations for the corresponding mnemonics have been experimented. For instance, a jump to label ADDRi f previous result is positive can be written JP ADDR ( I n t e l ) ; BPL ADDR (Motorola); JPL ADDR; JUMP ADDR,PL; BRANADDR,PL; JMPPLADDR; JUMP/PL ADDR; JUMP,PLADDR; etc. Experienced programmers have an immediate preference, depending on the machine they are used to program. Novices prefer the most e x p l i c i t instructions, and since mnemo-nics are mainly intented for engineers without programming s k i l l s , the notation JUMP,PL ADDRhas been chosen.An other ad. vantage is that overall l e g i b i l i t y of the program is improved because the 7-1etter mnemo-nics of these important instructions make them appear clearly in a l i s t i n g ( f i g . 2). The objection that these mnemo-nics are longer to type and to p r i n t is valid, but the increase in time is negligible, specially i f compared to the time usually lost because of misunderstanding or confusing mnemonics. For instance, i t may seem that JPL is as clear and shorter than JUMP,PL.But the use of JPL implies the use of CPL in.place of CALL,PL, which in turn obliges the use of a less evident mnemonic for complement instruction. The use of jump
; E ~ I _ E OF INSTRUCTIONS: SEE INTEL BOOKLE[ "FR17~iCFIJ TO SF.#:TWAG~E", PAGE 17 ; Mi~NICS LO~I A,B
I N TEL
LOAD LOAD
A,#23. ;MVI A,4098. ;LDA
A,B A,23 4098.
LOAD LOAD LOAD
A, KkL) ;NOV A,(I-~t) ;Ll)~e~(
A,M B
;MOV
LOA~[m
HL,4098.;LXIH 4098. A , ( H L ) ;NOV A,M
POP EX JLW'IF'
AI-" ;POF' (SF') ,HL ;X'THL (I-IL; ; F'CFL
A
;LOAD A WITH REGISTER B ;LOAD A WITH DATA IM~I)IATE 23 DECIMAL ;LOAD A WITH CDN[£NT OF MEMORYLOCATIO~I4098 ~LOAIJ A USIN~ PAIR HI_ AS AI)I~ES~ ;LOAD A USING FAIR BC AS ADDRESS ;LOAD A... ;..USING LOC 4098 [ECIMAL ;LOAD A AND FLAGS FROMSTACK ; E X C ~ T(]F' OF" STACKWITH HL ;LOAD PC WITH HI_ (JLIHP TO LOC AI)Br~ES~:~EII BY Hi.)
Fig. l. Comparison between m n e m o - n i c s and Intel mnemonics for some data transfer instructions.
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JQBN 20.1.75/6.2.75
.TITLE RPR68
;CALL R£AI': ; REAP AND ECHOCH~
24
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d) Misceleaneous instructions include mainly INP (input), OUT (output), ION (interrupt on), IOF (interrupt o f f ) , TRAP (software interrupt), NOP (no op, idle), WAIT (halt, wait for interrupt). Input and output instructions are in fact data transfer instructions, and they will appear as LOAD instructions in many microprocessors.However, i f the I/O transfer concerns only one accumulator, input and output instructions are convenient.
40210 40010 40310 40010
.LOC 37700 REAII:
TEST SKB JL~,SC R'EAD LOAD A,K~ AND A,#177 COil' A,#140 JU~',CS F~INT SUB A,#40 PRINT: TEST STT 3UtIP,SC PRINT LOAD TT,A
;TEST KEYBORD FLAG ;TEST AGAIN IF BUFFER MOT FULL ;READ KEYBOARD ;STRIPPARITY BIT ;TEST BIT FOR LOWER CASE ;JUMPIF ASCII COIE LO~-R THAN 140 ;CHA~. LO~ER TO UFI:~ZR CASE ;TEST F'RINTER FLAG ;TEST AGAIN IF NOT READY ;PRINT
RET .£N~
Fig. 2.
Sample source p r o g r a m for the Motorola
6800.
i n s t r u c t i o n , which looks d i f f e r e n t from other i n s t r u c t i o n s , has appeared to be very convenient. The mnemonic JUMP has been chosen f o r a branch i n s t r u c t i o n f o r two reasons: the same mnemonic CALL is used f o r " c a l l always" and " c a l l condit i o n a l " , hence i t is not consistent to have two d i f f e r e n t mnemonics f o r "jump ~lways)" and "branch (on c o n d i t i o n s ) " ; jump is preferable to branch because i t does not have to be abbreviated confusions and typing errors w i l l be less f r e quent. Hence, the mnemo-nics f o r the jump i n s t r u c t i o n s have one of the f o l l o w i n g forms: JUMP JUMP,XX CALL CALL,XX RET RET,XX
ADDR ADDR ADDR ADDR
Jump u n c o n d i t i o n a l l y to ADDR Jump i f t e s t XX true to ADDR Call routine ADDR Call i f t e s t XX true routine ADDR Return from subroutine Return i f t e s t XX true.
Various addressing schemes can be used, depending on the processor. Mnemo-nics f o r tests are preferably t w o - l e t t e r s , u s u a l l y giving a clear enough abbreviation ("VC" overflow b i t cleared, "GE" ~reater or equal, etc.#. These tests depend usually only on The values of the f l a g r e g i s t e r s which are not loaded at every i n s t r u c t i o n . I t is imPortant to think in terms of these f l a g s , which are often used f o r non-arithmetic operat i o n s : "SC" (sign b i t c l e a r ) is often used f o r t e s t i n g i f a peripheraT is ready and is equival e n t to "PL" (plus ( p o s i t i v e ) r e s u l t ) , which can a l t e r n a t i v e l y be used, and is preferable only i f the t e s t concerns a signed number. I t is necessary to be careful with the mnemonics of the a r i t h m e t i c tests f o l l o w i n g a compare or subtract i n s t r u c t i o n : " L T " (less than) applies to two signed numbers in 2s-complementary form (7 b i t s plus s i g n ) , "CS" (~arry ~et) m~ans also lower than, but f o r two 8 - b i t p o s i t i v e integers.
In each group other more special i n s t r u c t i o n s e x i s t , depending on the processor. The notation f o r these additional mnemo-nics is e i t h e r inspired from the mnemo-nics used f o r s i m i l a r i n s t r u c t i o n s or is ident i c a l to the o r i g i n a l manufacturer's mnemonics. Numerical values f o r addresses, i n s t r u c t i o n s and data can be w r i t t e n e i t h e r in octal or in hexadecimal. I f no habit p r e - e x i s t s , octal should be p r e f e r red f o r several reasons: i n s t r u c t i o n coding (handassembling) is more easy (see example in -~ 4); confusions between numbers and labels are avoided i f numbers do not include l e t t e r s ; octal numbers are also more easy to read and to type on a keyboard. The only drawback is the sometimes necessary conversion in two bytes, very easy to learn (see the acompanying I n t e l mnemonic reference card). 3.
Software
support
for
mnemo-nics
Changing the manufacturer's notations implies to w r i t e a new assembler, which may seem a considerable waste of time. However, software support provided by the microprocessor manufacturers is up to now very weak, not cheaply a p p l i c a b l e , and very often not adapted to user's need. I f the user wants to change from one processor to another , not only the mnemonics change, but also the assembler, e d i t o r and debugger r u l e s , and a new microcomputer may have to be bought. Some standardization is necessary at a l l these l e v e l s . 010763 010703 010704 010705 010706 01070,9 010707 010710 0i0?10 Q16711 010712 010712 010713
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010721 010721
365
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Sample of program for the Intel 8080, assembled with the PDPI1 (compare with fig. 2).
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When debugging a program, changes or replacements of instructions can often be made directly in the memory, reducing the number of consecutive assemblings, and saving time. Instruction l i s t in numerical order ( f i g . 5 and 7 ) is very useful when checking memory contents. Examples of figure 8 show more samples of programs, written for the Motorola and the Intel 8080. The ease of reading an assembly program written with mnemo-nics is evident and allows the programmer to use more significant comments and make the program more easy to understand.
The use of the macroassembler of a minicomputer allows to write rather easily a cross-assembler for a microprocessor. Few of the symbols chosen for the mnemo-nics may seem d i f f i c u l t to be recognized by a given macroassembler. I t is however always possible, by using a more complex analysis of the instruction: the convenience of a l l the users of the assembler is more important than some saving of time of the programmer writing once the assembler. Intel
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the two devices. The conventions for the stack, restart and interrupt procedures are also summarized in order to quickly remove all the hesitations which may suddenly appear, especially i f one has formerly studied many processors.
The Mini and Microcomputer Laboratory of the I n s t i tute of Technology of Lausanne is working in that direction. The mnemo-nics have been used for several months and they have proved to be very easy to learn and convenient to use. Up to now, Intel 8080 and Motorola 6800 instruction sets have been converted in mnemo-nics and cross-assemblers have been written for both, using both the macroassembler of the RT-II (or DOS) on a PDP l l / 4 0 and the macroassembler on a Nova. Figure 3 gives an example of an assembly l i s t i n g typed by the cross-assembler running on PDP I I . Later this year, resident assemblers w i l l also run on the microprocessor i t s e l f . Similar work w i l l be done for the RCA COSMAC, Signetics PIP, Intel 4040, etc., as soon as these processors w i l l be available to us.
4.
25
5. Conclusion Multiplication of equipments and users implies some standardization. This has (more or less) been done for integrated c i r c u i t s , peripherals and high level languages. I t has s t i l l to be done for assembly languages. Even i f i t may take some time before the manufacturers commit themselves to any standard, i t w i l l happen because the users w i l l have to get familiar with various microprocessors and they need to have their work done simpler, faster and more efficiently.
8080 and Motorola 6800 mnemo-nics
The i n s t r u c t i o n reference card f o r I n t e l 8080 ( f i g . 4 ) and Motorola 6800 ( f i g . 6 ) microprocessors are primar i l y machine i n s t r u c t i o n reference cards. They cont a i n a l l the necessary i n f o r m a t i o n about the processor, to the programmer's point of view, with of
The attempt presented in this paper has widely benefited from the work done by Rick Merrill from Digital Equipment (Maynard, Mass.) and Mike Lindheim~r from Analog Devices (Westwood, Mass.). The author is also very grateful to G~rard Gris and Ren6 Sommer from the Swiss Institute of Technology (Lausanne) for their expert work in writing the software support for the mnemo-nics.
course a l o t of evident definitions and conventions not e x p l i c i t e l y mentioned. Register organization, with symbols used for registers, register pairs and status bits are the f i r s t things to get familiar with. Instructions themselves are easy to understand. For the detailed effect of some instructions (e.g. test, s h i f t ) , i t may be necessary to check the manufacturer's complete description.
Hand assembling and disassembling is very easy, espe- ~ ;HO~STHEUIFFE~HC~S ~ T ~ - ~ N I ~ 4 ~ T ~ A ~ : . M 4 ~ N I ~ c i a l l y in octal. For instance: S.'~,L(~ ~,,ST~C~ ;LBS #ST~ ;L(W~ &F WIIll ION LOAJ) LO(4J JUttP, EO LOAb COf~ J U t ~ M; C~. INC LO#4# AD[W~ JLk~, HI ~JB
INTEL 8080 LOAD A,(HL) = 100+70+6 = 176
One byte i n s t r :
Load A with content o f l o c a t i o n a d d r e s s e d by HL
MOTOROLA 6800 LOAD A,(IX)+8 = 206+0+40=246
Two-byte i n s t r :
Load A with the c o n t e n t o f l o c a t i o n a d d r e s s e d by I X (indexed by I X w i t h o u t d i s p l a c e m e n t )
Two-byte i n s t r :
S u b t r a c t to A n u m b e r 31
MOTOROLA 6800 SUB B,#31 = 200+I00+0 = 300 Two byte instr: S u b t r a c t to B n u m b e r 31.
The sequence for the low order and high order byte of a 16-bit word stored in the memory appears clearly on the programming sheet: i t is different for
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Return if t true (Address from stack : PC ~ (SP) (SP + 1). SP ~ SP + 2)
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MNEMONICS
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LXI S LXI O l LXI H LXI SP
ISPHL
0D6 7 ~o6 10
MVI r MVI M
ivIOV rl. r: 1DS MOV r.M 1D6 MOV M.r 16S
ORIGINAL MNEMONICS
~57
~el
166
363
373
323
333
~7
¢77
g47
4
4
(71
4
4
10
10
4
4
~
~
~
~
~ ' ~
~
~
~
~
[ T ~
~
4
4
[T~]
~
~
4
4
4
L
¢. . . . .
j f
J
J 250+J L. . . . .
ADDC. A ~ I
ADD= A~r
ADDAHL~o
DEC, p
Subtract with carry (S.Z.X,P, C can change)
Subtract (S, Z, X. P. C can change)
Add with ¢w'rv (S. Z, X, P. C can chenge)
OR
OR.A..
NOP
WAJT
IOF
ION
OUTAn
INP~R
SETC
OPLC
D/UIL
RRCAA
RR=A
RLCAA
RL=A
CPLAA
P
E H
SP
HL
OE
8(:
6e (HL) 711 A
I~" L
~" 4e
B C
$
8
I~m.~"..)
,m
7 A
H L
,HLI
~ ~
1 c
2" O 3 E
;
NO operation
Wait for interTOpt (halt)
Inte'rupt off
Intcvrupt on
Output tO periphesel n
I nl:lUt to acc. f fore pii'iphecel n
Setc, erry ( C = 1 )
Complement the cirry (C = (~)
Decimel adjt.~t i¢¢.(S, Z. X. P. C can change)
Rotate right Icc. with carry (C = A I )
Rotete right ecc. (without cacry) (C = AID)
Rotate left acc. with carry (C = AT)
Rotate left acc (without carry) (C m AT)
Complemem the acc.
h
( Z = I if A = s , C = 1 if A < s , S . X. Pcan change)
Compare (A - s )
(C = (D. S, Z, p can change)
Exclusive 0 R (C = (~. S. Z. p can chlmge)
(C = 0, S, Z. P can chenge) XOR= A65
COMPs A~a
I
; ;
d
el te
m
Add to Accumulator register, location Or numb~ = (S, Z. X. P. C con change)
Add to HL the pairp (S. Z, X. P do not change)
Decrement pairp (S. Z. X. P. C do not change)
Increment pair p (S, Z, X. P, C do not change)
Decrement d (S, Z, X, P can change)
Increment reQister Of location d (S. Z. X, P can checRe)
AND.A. And
SUBC.A,#
I SUBAAa$ J
i
~ I . .L. . - J
~--~ L. . . . .
~
i
~
[ ~
INC=p
DEC=d
INC~d
MNEMONICS
Can be reproduced with a,Jthoriz~uon of LCD EPFL. Bellw~ve16. CH 1007 Ll~wnne
NOP
HLT
DI
El
OUT
IN
STC
CMC
DAA
~137
¢17
RRC
~7
027
RAR
4
7
2iS 216 316 7 22S ,,4. 226 ' 4 326 4 23S 236336 4 7 24S 246 346 7 25S 2r~6 356 7 2~ 266 366 7 27S 276 376 7
20S 206
RAL
RLC
CMA
ANA r ANA M ANI XRAr SRAM XRI ORAr DRAM ORI CMP CMPM CPI
AOC r AOCM ACI SUB r SUB M SUI sen r ~l~lBM
ADD r ADD M ADI
~)03 ¢23 943 OB3 913 e33 ~53 1~73 I)lt (~31 (~51 @71
~O5 ~65
DCR r INRM INX S INX O INX H INX SP OCXB DCX D DCX H OCX SP OAOB DAD O OAO H OAOSP
~D4 e164
INR t INR M
ORIGINAL80~0 MNEMONICS
I
o~
I
- 27MICROCOHPb'TF.R LAIk"NRATORY
MINI
SHISS FEDERAL INSTITUTE OF TFO-INOI.O6Y
INTEL
8080
MNEMO-NICS
(LCD EPFL) ¢ " 0 )NOP 1i 41 i l O l A IZ l LOAD BC,~m ILOAD (BCI,A 42 102 B 43 103 c 3 ~ : INC BC 44 104 D ¢ INC B 45 1p5 E { DEC B 46 ] 0 6 l F n ',LOAD B,~n 47 Ip7 G e IRL A 48 49
ADD HL,BC }, LOAD A,(BC) I~ !iDEC BC u iINC C DEC C LOAD C,,~n w RR
12 13 14 15 1B 17
4A 4B 4C 4D 4E 4F
A
50 51
p o LOADDE,~ 22 LOAD (DE),A 23 u INC DE 24 INC D 25 X. DEC D 26 i LOADD,~n 27 = RLC A
e8 210 '~ i ADOC A,B 89 211 F: 'iAOOC A,C 8A 212 X )ADDC A,D
120 P LOADD,B 121 0 LOADD,C 122 R LOADD,D !.123 S LOADD,E 1124 T LOADD,H 125 U LOADD,L 126 v LOADD,(HL) W LOADD,A
220 ~ SUB A,B 221 ~ SUI3 A,C 222 -r SUB A,D
DEC DE INC E DEC E LOADE~n RRC A
i LOAD m,HL
NC HL
INC H DEC H & LOADH,=~n ' DAA ( ADD HL,HL LOAD HL,m DEC HL INC L DEC L LOAD L,#n CPL A
3O 31 32 33 34 35 36 37
3B
3A 3B 3C 3D
it k Z m n o
6¢ LOAD SP,#m 2 2 LOADm,A 3 3 INC SP 4 4 IRC (HL)
r
5 5 DEC (HL) 6 6 LOAD (HL),~n 7 7 SETC
4
5 6
7
Octal
t
7A 7B
< INC A
II17c
DEC A ; LOAD A,#n ? CPLC ,
i
~[uemo-nio
Fig. 5.
:
172 73 174 75
7E 176 F 177
z { I }
311
r.) RST
0
:Z ) RET
CB 313 ~ i
cc co CE CF
314 CALL,EQ 315 i CALL 316 I~ AODC 317. U RST
m in A,,~n
1@
DO 320 RET,CC D1 321 POP DE 02 .~ JUMP,CC m D3 OUT n ) CALL,CC m I U PUSH DE
224 ~ SUB A,H 225 ~ SUB A,L 226 ~ SUB A,(HL)I 227 ~ SUB A,A 2361 231 232 233 234 235 236 237
~ I POP BC 1i i JUMP,NE m d i JUMP m Q~ CALL,NE m ~ I PUSH BC P:! ADD A,,n
CA 312 J() JUMP,EQ m
ADDC A,E ac 214 v ADDC A,H SO 215 ADDC A,L i BE 216 -~ ADDCA,(HL). 217 W ADDCA,A
223 u SUB A,E
RET,NE
(,
)~. SUB A,+n k~ RST 20 RET,CS
~ SUBCA,B
~ SUBC A,C "
SUBCA,D SUBC A,E ; SUBC A,H t~ SUBC A,L E SUBCA,(HL: ~- SUBCA,A
JUMP,CS m ;INP
n
IS CALL,CS m . ! RST
A,*n 30
i~
m
SUBC I
LOADtI,B
LOAD H,C
LOAD L,B LOADL,C LOAD L,D LOADL,E LOADL,H LOADL,L LOADL,(HL) LOADL,A
LOAD (HL),D LOAD (HL),E LOAD (HL),H LOAD (HL),L WAIT LOAD (HL),A
~8 1 9 ADD HL,SP 2 z LOADA,m 3 ~ DEC SP
J)O
RET,EQ C9
BB 213
LOADE,B LOADE,C LOADE,D LOADE,E )LOAD E,H LOADE,L LOAD E,(HL) LOAD E,A
p LOAD(HL),B' q LOAD(HL),C
61
I
i cl ; c2 ) c3 l C4 ! c5
240 i :AND A,B 241 ~ AND A,C LOAD H,D 242 "~ :AND A,D c LOADH,E 243 :~ AND A,E d LOADH,H 244 AND A,H e LOADH,L 245 ~ AND A,L •f LOADH,(HL) 246 & AND A,(HL) LOAD H,A A7 247 ' AND A,A
i
iLOAD HL,Om ~
l e l | ?O1 ~ ADD A,C B2i202 y ADD A,D 83)203 ADD A,E 841204 ¢ . ADD A,H
H I J K L
x Y Z [ \ ]
,
301 302 LOADB,D 303 LOAD B,E 304 LOAD B,H 85:205 ADD A,L 305 LOAD.B,L LOADB,(HL) 86 206 fi ADD A,(HL)I c6 306 87 207 o !ADD A,A C7 307 LOADB,A
LOADB,C
LOADC,B LOADC,C LOADC,D LOADC,E LOADC,H LOAD C,L N LOADC,(HL)I 0 LOADC,A
llO 111 ll2 If3 ll4 I15 If6 I17
,/~ADD HL,DE + ', LOAD A, (DE) ÷ + £
,
l
A8 A9
AC AD AE AF BO B1 B2 R3 B4 BS B6 B7
LOAD A,B LOAD A,C B9 LOADA,D LOADA,E LOADA,H BC LOADA,L LOAD A,(HL) RE
I LOAD A,A
MCM6571 Character ~enerator
250 (
251 :): 252 ~r 253 254 , 255 ~ 256 ~ 257
i
(sP) ,HL g f~
°:
f
XOR A,B XOR ..A,C XOR A,D XOR A,E XOR A,H XOR A,L XOR A,(HL) XOR A,A
)
HL A,4n
,,
RET,PE (HL) l JUMP,PE m
,t
m
356 ~ XOR
357
RST
370 371
RET,MI
A,+-n
5¢ 36~L ~ RET,PL 361 POP AF 362 JUMP,PL m 363 IOF 364 EI CALL,PL m 365 PUSH AF 366 OR A,..~n 367 RST 60
A,B z6~ ~I: i OR A,C 262 .~ fOR A,D 263 _3 i OR A,E 264 4 i OR A,H A,L 265 ~)OR 266 ~ OR A,(HL) 267 Z OR A,A 260 g. OR
270 ~ COMPA,B 27] .~ COMPA,C 272 -'. i COMPA,D
273 ~ COMPA,E ~ COMPA,H - COMPA,L > I COMP A,(HL) ~ COMPA,A
373 374 375 376 377
274[ 275 i 276j 277
~I
Hexadecimal
Intel 8080 mnemo-nic instruction list.
LOAD ST,HL JUMP,MI m ION CALL,MI m CONP
A,+n
RST
7e
e
17.2.75
-
MINI AND MICROCOMPUTER LABORATORY SWISS FEDERAL INSTITUTE OF TECHNOLOGY OF LAUSANNE (LCD EPFL)
MICROPROCESSOR REFERENCE CARD
Low byte
~oXl,l
316
L---J L---J
tab or comma)
t LSB[
m
......
I
I .........
v= ~,L[4-E []'x
~
16-bit number
....
T o p m e m o r y asslgnmenI
LOAD~d~s
(sz.
t I
I nt~'rupt : IDF General save on stack. load of interrupt address
~E~[]~ li~
Octal
~ L_--J L_--J
ii,llX,l,Slz,v,c
INSTRUCTIONS (MNEMO-NICS)
! Deviations with 6800A
2 Hexa
REGISTER O R G A N I Z A T I O N
a~,~,hawJr,v
. . . . . .
MPUCycles(~' I ~zsfcycle) $ U)*AdO~ LD~AIX~ ~DAeI=P
-
MOTOROLA MPU 6800B
F=q ........ I ~DAA~e~
28
:?,.~: .....
r--. . . . .F. IL
B
~-
~
k- -{---A
F,~,
~
AL, B
INTERRUPT
177770
....
171777 HIxa
STAA~m S~AAIe, ST~X~
[L -•- - J' 7 ~•
L___
L___J
S~S~m
LOAID~d~; -I
L---J
withs (sz, v
= 0)
026
[BA
021
rAP
~6
[
FPA
~7
I]'~
~
~
]
,×~
065
~
DEC~SP~IX
Load SP with IX and decrement
16bits
]-SX
0e~
~
INCaIX~SP
Load IX with SP and increment
F~JRA PSRB
~66 ~B7
[ ~ [ ' 0 " ~
PUSHed
Pushd . . . . . . k
[T3"~ ~6"-~
POP~d
Pupal on stack ~ - -
~ [[~] [ ] , x [[~]i ~ ; ]
~. . . . . . indexed
II~ 6 Ill~'~'~ I
TAB
..i,.,0,.~,l L g IGI~ ~,*teod,,0~
n~
~OAOo.oA
LoadBwithA {SZ.V =0)
~
LOAO~A~8
Load A with B (S,Z, V = 0)
~
LOAD~F~A
Load status reg F with A
1"0~
LOADaAaF
Load A with status reg F
~
ADD~d~s
Oc~l
Add d with $, result in d (XSZVC. . . . hange)
sP
PULA PULB
SEC
0t5
:LC
014
~EV
013
~LV
~
~c.m
su.:o,,o,
'
'1
SETC
Set carry bit (C = I) !
CLRC
Clear carry bit (C = ~}
~
SETV
Set overflow b,t {V
012
[]'~-[]
~
CLRV
CI . . . . . . .
BCC
044
~
~
JDMPACC~.+." Jump if carry clear (C = 0) (jump if greater or equal *}
# m l l XSP)
3CS
045
~
~
'DMP.CS..+n' Jump ff carry set (C = 1)
8 b~is{d,r~t I
~LS
043
~
~
JUMP. LS..+tr Jump if I. . . . . . . . . .
~HI
042
~
~
JUMP~HI. +n Jump if higher (C + Z = @)
~NE
046
~
~
JUMP~NE~.+n' Jump if not equal . . . . (Z = @) JUMP~ZC~ +n' Ilump if zero bil clear)
BEQ
047
~
~
JUMP^EO~ .+n' Jump if equal (Z = 1) JUMP^ZS ~.+n' (jump if zero bit set)
.' ,sa 2............ d~pl~emenl ( 176to ~201)
BPL
052
g2 A~2 ~
JUMP.Pt.,+n, Jump if plus (S = , ) JUMP~SC~.+tr (jump if sign bit clear)
............
BMI
053
~
JUMP~MI^.+n' Jump if . . . . . (S=11 JUMP~,SS~.+n" (jump if sign bit set)
BGT
~56
BGE
054
BLE
057
8LT
055
BVC
05~
Bvs
051
A
~
ORBm
~
ANDodo*
And (SZ, V
OR~d~s'
O,
$
= ~)
{SZ, V = (~) (SZ, V = 0 )
(e~lended) ~t-~[]
2 Q~5* c*x.,
~
Bit test (d and s) (SZ. V = 0)
~
~
COMP~IX~x
CompareIndexreg wrth S (IX s) (16 bits} (SZVC)
ADD~A~B
AddAandB(A~A+B)
ABA
033
SBA
020
CBA
021
OAA
031
INX
~10
II ~ e I] I ~ ~ ~ I ,.co,x
, ........ ,o0~:~ reg ~
DEX
011
o .......
INS
061
II e~ I11~ ~ I DE~o,x [I 3~ IIN6" 1 'NC~SP
o .......
II~ellle~l,u,oA~ ~
DAA
(XSZVC)
su~..... Aaod~A~A-~,~ZVC~ Decimal adjust ACC A (SZVC)
,
064
II 3 4 l] l e 6 4
117 137 177 t57
114 F'I] l i i 7"J C, Ro~ L:zzd ~:::d
C,e.rd(S=e.Z = f . V = e . C = ~ )
COMA
103
II 4 3"111 i ~]'1 c,,,,
~omp, . . . . . . .
.L._. _. ._.J. . . .
L__-
NEGA
1~ L-----J
L------J
DECA
112
114 A'[I I~ ~ 2"1 o z c ~
INCA
t14 I
If4 cfll Ill 4"1 ,NC~#
~___J
J
[I 4 9"1] I ~ 1 1"1 RLC.d
I11
.......... 106
I146"11
I
ASL
ne I
ASR "
107
kSn
104
TST
115
t:::d
fi~6:/RR¢~, r_: : : .
JUMP,GE ..+n' Jump ,f greater or equal *" (S + V = (~)
Jumpd,...... ~
~
JUMP~ LTr '+n' Jump z e f o " (dS I. .+. . V. =hart ') ~
JUMP.VC . + n ' Jcr,:rp(,vf o:e(~;Iow
,UMP vs .umpdoorfow set (V = I)
(SZ.V = @.C = ~)
~]~O~J~
B
BRA
~4~
I ~
~
JUJPn.+n'
Jurnp relative (displa(enlerll n bytes)
(SZ.C = I i f d = ~ V = 1 d d = 2~(~}
~
mar~lule
BSR
2~5
~
~
CALLA.,n'
b .r .o. u.on C .t i nsta{k) e(pc
~........
'T~ ~
JMP(EI JMP(I)
176 156
JSR(EI JSRN)
275 255
~
~
CALLt,/
Call subroutine (PC on stack)
,......... (SZ, V = l d d =
I
(extendedl
........ /
177.)
R..... ,el, with ..... (s~c. v : s + c~
~
P
~
~1
. i ~ [ ]
(e.t eacled) ......
,ndexed
RTS
e71
~
nET
RTI
073
~
RTI
SWI
077
[ [ ~
~
TRAP
WAI
076
I]'~ E ~
~
WAIT
CLI
016
~-]]
~
ION
Return from subroutine (PC from stack) Return from interrupl (F, 8, A. IX. PC from stack) Sol . . . . . . . . . . . . pt (trap, (PC, I X. A, B, F on sti~ck, l = l ) Walt for i . . . . . . pt (halt) (no DMA, registers already on stack) I . . . . . . pt ON (I = 0)
(SZ, C = g , V = S + C]
SEI
017
Test d (load S and Z . . . . d,ng tod) (sz, c = (~. v = @)
NOP
6'~2
~
NOP
N o operation
. . . . . . . . g. . . . . h . . . . .
{szc. v =s + o
Arithmeticshdl left (SZC. v = S + C)
I 114 D ' I I / ' ]'~)+"=J TEST." I ~ -. - -. d . . . t -.- - - ~
~
A
~--:~
~--Z :~
~
~he, COMPor SUE{,nslru{hun * * 2scomplement UbliS nun,~rs i 7 b,ts + Sl#,/) abe, CC)MPor SUB ............
i,~Tj L~J
1
I148fll I' ! ~'1 ~o" 1 ~~.1 ASR~d [IL - 4- _ 7*_ ~I][L_----~
I
Stack p . . . . . .
L-----~
~-_-_-~ E - : Z
JUMP~G Ta .+n' Jump if greater • * (Z + (S + V) = (~)
equal**(Z + (S + V) = 1)
I .......... Stack p . . . . . .
DES
J
~
index ,eg (Z) '
CLRA CLR8 CLR(E CLR(I:
1 o~c.sP
*(C+Z=,)
., .~. d. .~. . .
¢.P~m
nORA
= I)
flow bit (V = 0)
(SZVC)
z~
ROLA
B
[ ~
o '
sub.~tw.b .....
sPd
~
d ~II~] [ ]
(SZVC)
/
.
[]~']]
s.0 . . . . ( . . ,
su~.m
~. -.- -.
[~-~-~-O
Arithmetic shift right (SZC. V = S + C}
q~
February t975
Can be reproduced with authonzat,on of LCO EPF L, Bellerive I6. CH 1007 Lau~nne
Fig. 6.
Motorola
6800 m n e m o - n i c reference card.
-
MINI
AND
29-
MICROCOMPUTER LABORATORY
r,INEMO-N I CS
MOTOROLA 6800
SWISS FEDERAL INSTITUTE OF TECHNOLOGY (LCD EPFI.) 0 I
B
2 3
y
4
£
NOP
5
6 7
n e
LOAD LOAD
F,A A,F
I0 11 12 13 14 15 16 17
I INC K DEC CLRV p SETV v CLRX SETC 0 IOF ION
IX IX
20 21 22 23 24 25 26 27
p o
A,B A,B
30 31 32 33 34 35 36 37
SUB COMP
T
¢ LOAD w LOAD
B,A A,B
~ AA ÷
ADD
18 ~.9 ~A IB ~D ~E ~F
U
X
IO ;1 12 t3 14 ~5 ~,6 ~7
A,B
÷
EG A
PL A SR A RC A .SR A ,SL A :LC A ~EC A NC A EST A :LR A
50 51 52 53 54 55 56 57
IEG B
58 59 5A 5B 5C 5D 5E 5F
kSL B {LC B )EC B
~EG (IX)+n
',PL B .SR B ~RC B ~SR B
[NC B FEST B "LR B
4O 41 42 43 44 45 46 47
JUMP,HI .+n' JUMP,LS .+n' $ JUMP,CC .+n % JUMP,CS .+n JUMP,NE .+n JUMP,EQ .+n
GO 61 62 63 64 65 66 67
50 51 52 53 54 55 56 57
JUMP,VC JUMP,VS JUMP,PL JUMP,MI JUMP,GE JUMP,LZ JUMP,GT JUMP,LE
.+n .+n .+n .+n .+n .+n .+n .÷n'
68 69 6A 65 6C 6D 6E ,SF
%SL (IX)+n ~LC (IX)+n )EC (IX)+n
60 61 62 63 64 65 66 67
INC INC POP POP DEC DEC PUSH PUSH
IX,SP SP A B SP SP,IX A B
70 71 72 73 74 75 76
IEG m
70 71 72 73
JUMP
.+n'
"
78 79 7A 76 7C 70 7E 7F
RET RTI
74 75 76 77 Octal
77
WAIT TRAP ~nemo-nlc
Fig. 7.
:PL .SR
(IX)+n (IX)+n
~RC (IX)+n ~SR (IX)+n
[NC (IX)+n rEST (IX)+n ;LR
(IX)+n
691211 BA I 212 8B I 213 Bc I 214 BD 1 215 BE I 216 8F 1 217 901220 91 t221
921222 931223 941224 951225 951226 971227 981230 99 J 231 9A I 232
98 1233 9c I 234 9D1235 9E1236 9F1237
XOR B,~n ADDC B,~n OR B,~ n ADD B,~n
SUB A,n COMP A,n SUBC A,n
DO DS D2 D3 D4 D5 D6 D7
SUB B,n COMP B,n SUBC B,n
D8 D9 DA DB OC DD DE DF
XOR B,n ADDC B,n OR B,n ADD B,n
EO El E2 E3 E4 E5 E6 E7
SUB B,(IX)+n COMP B,(IX)+n SUBC B,(IX)+n
E8 E9 EA EB EC ED EE EF
XOR B,(IX)+n ADDC B,(IX)+n OR B,(]X)+n ADD B,(IX)+n
FO F1 F2 F3 F4 F5 F6 F7
SUB B,m COMP B,m SUBC B,m
F8 F9 FA FB FC FD FE FF
XOR B,m ADDC B,m OR B,m
AND A,n BIT A,n LOAD A,n LOAD n,A XOR A,n ADDC A,n OR A,n ADD A,n COMP IX,n LOAD SP,n LOAD n,SP SUB A,(IX)+n COMP A,(IX)+n SUBC A,(IX)+n
A8 A9 AA AB AC
250 251 252 253 254
XOR A,(IX)+n ADDC A,(IX)+n OR A,(IX)+n ADD A,(IX)+n COMP IX,(IX)+n
AD AE AF
255 256 257
LOAD SP,(IX)+n LOAD (IX)+n,SP
BO 61
26C 261
B2 63 64 65 B7
~SL m RLC m DEC m
68 69 BA BB BC BD BE BF
27C 271 27~ 273 274 275 27E 27)
MCM 6571 Character generator
ca c9 CA CB CC CO CE CF
AND A,#n BIT A,.in LOAD A,~.n
A01240 AI1241 AZl 242 A3! 243 A4! 244 A51245 A6 246 A7 247
86
CLR m
XOR AJn ADDC A,~-n OR A,~n ADD A,~n COMP IX,Im CALL .+n' LOAD SP,Im
B8 1 210
RRC m ASR m
INC m TEST m
SUB B,,#n COMP B,~n SUBC B,|n
SUB A,~n COMP A,+n SUBC A,-~n
262 263 264 265 266 26;
tPL m LSR m
CO CI c2 c3 c4 c5 c6 c7
~O I 200 ~i I 201 ~2 1202 63 I 203 ~4 t 204 65 I 205 66 I 206 ~7 I 207
AND A,(IX)+n BIT A,(IX)+n LOAD A,(IX)+n LOAD (IX)+n,A
SUB A,m COMP A,m SUBC A,m AND A,m BIT A,m LOAD A,m LOAD m,A XOR A,m
ADDC A,m OR A,m ADD A,m COMP IX,m
LOAD SP,m LOAD m,SO
AND B,~n BIT B,~n LOAD B,,n
LOAD IXdm
AND B,n BIT B,n LOAD B,n LOAD n,B
LOAD IX,n LOAD n,IX
AND B,(IX)+n BIT B,(IX)+n LOAD B,(IX)+n LOAD (IX)+n,B
LOAD IX,(IX)+n LOAD (IX)+n,IX
AND B,m BIT B,m LOAD B,m LOAD m,B
ADD B,m LOAD IX,m LOAD m,IX
t
Hexadecimal
Motorola 68oo mnemo-nic instruction list.
17.2.75