- Email: [email protected]
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses
Microelectronics Reliability 54 (2014) 1774–1778
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses Y. Wang a,b, Y. Zhang a, E.Y. Deng a, J.O. Klein a, L.A.B. Naviner b, W.S. Zhao a,c,⇑ a
IEF, Univ. Paris-Sud/CNRS UMR 8622, Orsay 91405, France Laboratory LTCI-CNRS, Institut TELECOM, TELECOM ParisTech, Paris 75634, France c Spintronics Interdisciplinary Center, Beihang University, Beijing 100191, China b
a r t i c l e
i n f o
Article history: Received 25 June 2014 Accepted 8 July 2014 Available online 4 August 2014 Keywords: PMAMTJ Stochastic Resistance variation Temperature evaluation Dielectric breakdown
a b s t r a c t Spin transfer torque magnetic tunnel junction (STT MTJ) is considered as a promising candidate for non-volatile memories thanks to its low power, high speed and easy integration with CMOS process. However, it has been demonstrated intrinsically stochastic. This phenomenon leads to the frequent occurrence of switching errors, which results in considerable reliability issues of hybrid CMOS/MTJ circuits. This paper proposes a compact model of MTJ with STT stochastic behavior, in which technical variations and temperature evaluation are properly integrated. Moreover, the phenomenon of dielectric breakdown of MgO barrier which determines the lifetime of MTJ is also taken into consideration. Its accurate performances allow a more realistic reliability analysis involving the influences of ambient environment and technical process. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Spin transfer torque magnetic tunnel junction (STT MTJ) is one of the excellent candidates for magnetic logic and memory applications because of its high power efficiency, speed and infinite endurance [1,5]. Recent research has found that MTJ with perpendicular magnetic anisotropy (PMA) behaves better performances in terms of thermal stability, critical current and access speed compared with that with in-plane magnetic anisotropy [2]. However, the PMA STT MTJ still suffers from considerable reliability issues [4]. Firstly, the limited fabrication precision causes uncorrected errors [7,8], due to the deviations of oxide barrier thickness (tox), free layer thickness (tsl) and TMR ratio (Fig. 1). These errors can be avoided by the appropriate choice of parameters at the time of design. Secondly, STT switching mechanism has been demonstrated intrinsically stochastic [9] due to the thermal fluctuations of magnetization [10]. Caused by this phenomenon, the switching errors occur frequently. Thirdly, as most of the STT switching operations require high currents flowing through the MTJ [3], the dielectric breakdown of oxide barrier (e.g. MgO) is an important factor to determine its feasibility and influence the reliability of MTJ-based circuits [11]. Therefore, a spice-compatible ⇑ Corresponding author at: Spintronics Interdisciplinary Center, Beihang University, Beijing 100191, China. Tel.: +86 (10) 82314875. E-mail address: [email protected] (W.S. Zhao). http://dx.doi.org/10.1016/j.microrel.2014.07.019 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
model of PMA STT MTJ involving these three reliability factors is imperative for the reliability analysis for hybrid CMOS/MTJ circuits, which can assist to find a tradeoff among the performance parameters. This paper presents a compact model of MTJ demonstrating STT stochastic behaviors. The technical variations and temperature evaluation have been considered to improve the simulation accuracy. The dielectric breakdown of MgO is also integrated to estimate the lifetime of MTJ, which offers the designers an approach to estimate the endurance of MTJ. By performing Monte-Carlo (MC) simulations, we validate its functionality in both writing and sensing processes. In addition, reliability analysis is performed to propose some assets for minimizing the impact of hard errors on circuit reliability. 2. Stochastic model of MTJ Depending on the magnitude of switching current, the stochastic behavior can also be divided into two regimes [14]: Sun model (I > Ic0) [15] and Neel-brown model (I < Ic0) [16,17]. The former is also called precessional switching which addresses fast switching (sub 3 ns) but consumes more energy with high current density. Reversely, the latter consumes less with low current density but offers a slower switching which is called thermally-assisted switching. For PMA STT MTJ, these two regimes are isolated by the critical current which can be described as follows [2,6]:
Y. Wang et al. / Microelectronics Reliability 54 (2014) 1774–1778
1775
Fig. 1. Magnetic tunnel junction (MTJ) consists of three layers: two ferromagnetic layers separated by an oxide barrier. The nanopillar resistance (RP, RAP) depends on the corresponding state of the magnetization of the two ferromagnetic layers Parallel (P) or Anti-Parallel (AP) [12]. The resistance difference is characterized by Tunnel Magnetoresistance Ratio TMR = (RAP RP)/RP [13]. With spin transfer torque mechanism, MTJ changes between two states when a bidirectional current I is higher than the critical current Ic0 [1].
Ic0 ¼ a
E¼
ce ce ðl M ÞH V ¼ 2a E lB g 0 s K lB g
l0 Ms HK V
ð1Þ
ð2Þ
2
where E is the barrier energy, HK is the effective anisotropy field, l0 is permeability of free space, Ms is the saturation magnetization, a is the magnetic damping constant, c is the gyromagnetic ratio, e is the elementary charge, lB is the Bohr magneton, V is the volume of the free layer, kffi B is the Boltzmann constant, and g ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi TMRðTMR þ 2Þ=2ðTMR þ 1Þ is the spin polarization efficiency factor. The switching duration for the two regimes can be calculated as follows [15,17]:
s ¼ s0 exp
Fig. 3. MC simulations of 1000 complete writing process with the stochastic behaviors. The switching duration is set following a normal distribution with variation of 0.02.
E I 1 ðI > Ic0 Þ kB T Ic0
" # lB Pref 1 2 ¼ ðI Ic0 Þ ðI < Ic0 Þ 2 hsi C þ lnðp4 nÞ emm ð1 þ Pref Pfree Þ
ð3Þ
ð4Þ
where E is the barrier energy, s0 is the attempt period, T is the temperature, kB is the Boltzmann constant, C 0.577 is the Euler’s constant, n = E/kBT is the thermal stability factor, mm is the magnetization moment, e is the elementary charge, P is the tunneling spin polarizations. The stochastic behaviors and technical variations are integrated in the model by using the random functions and statistical block, which are provided by Verilog-A under Cadence environment
(a)
[18]. For instance, $rdist_uniform generates a uniform distribution in a limited area and $rdist_normal generates a normal distribution with fixed mean value and standard deviation. The users are free to choose different types of statistical distributions for different parameters (tsl, tox, TMR and switching duration s). Using the circuit shown in Fig. 2(a), Monte-Carlo simulations of 1000 writing processes are performed in which the switching duration follows a normal distribution with the mean value of sp?ap or sap?p and variation of 0.02. The results (Fig. 3) demonstrate that the static switching durations (without stochastic behavior) are sp?ap = 1.4716 ns and sap?p = 2.4898 ns. As expected all the values of switching duration for parallel (P) state to antiparallel (AP) state are in the interval [0.98sp?ap, 1.02sp?ap]. It follows a normal distribution around the average switching delay time sp?ap and the variation set. On the other hand, for AP to P state, there are 98% values of switching duration in the interval [0.98sap?p, 1.02sap?p]. As the voltage is identical for both states, the current for AP state is lower than P state, which leads to a longer switching duration [9] and higher error rate of switching.
3. MTJ parameters dependent reliability analysis We did a reliability analysis based on the PCSA circuit (Fig. 2(b)) to investigate the dependence of reading error rate on area of MTJ
(b)
Fig. 2. (a) Circuit for STT writing which can generate a bidirectional current. (b) Pre-charge sense amplifier.
1776
Y. Wang et al. / Microelectronics Reliability 54 (2014) 1774–1778
Fig. 4. Dependence of reading error rate on the thickness of oxide barrier tox and area of MTJ.
and oxide barrier thickness tox. The results (see Fig. 4) show that both reducing the transistor size and enlarging the thickness of oxide barrier can sufficiently improve the reliability of hybrid CMOS/MTJ circuits. 4. Temperature evaluation model 4.1. Temperature increase due to Joule heating For the purpose of storing information for over 10 years in the high-density MRAM, the thermal stability factor (n) should exceed 60 [19]. In spite of optimization in the past several years, a large current density of several MA/cm2 is always needed for currentinduced magnetization switching [20,8], which heats up the MTJ due to Joule heating. The equations presented above (Eqs. (3) and (4)) show that thermal fluctuation affects deeply the STT dynamic behaviors of MTJ, especially the switching duration. Thus, it is essential to investigate the effects of the temperature increase during current pulses. In this model, the thermal heating of MTJ is integrated through the one-dimensional numerical calculation, which can be given as follows [21]:
V bias j
k dT ðT T 0 Þ ¼ C v thicks thickb dt
ð5Þ
Fig. 5. 100 MC simulations of writing with fixed (STATE) and variable temperature (STATE_T).
4.2. Effect of temperature increase on writing and reading of hybrid CMOS/MTJ circuits To investigate the impact of variable temperature on the dynamic of MTJ, we have performed MC simulations of 100 writing operations using the circuit shown in Fig. 2(a). The cases with and without considering Joule heating are carried out respectively. The simulation results (see Fig. 5) show a writing error rate of 20% for fixed temperature and 22% for the model of Joule heating. As the temperature increases due to Joule heating, the thermal stability degrades (n decreases) and a higher current is needed for switching the state. As a consequence, the performance and reliability of the device will get worse by considering the Joule heating [20]. Furthermore, we validate this model for the sensing operation in which the pre-charge sensing amplifier (PCSA) as shown in Fig. 2(b) is used. The MC simulation results (Fig. 6) exhibit an error rate of 20% due to either mismatch and process variations of CMOS devices or stochastic behaviors with Joule heating of MTJ. When we eliminate the influence of temperature, the error rate is then 19%. We also perform MC simulations for this circuit without stochastic behavior, which results in an error rate of 6%. By comparing these results, we find that the stochastic behavior of MTJ plays a more obvious role than Joule heating. Nevertheless, the temperature has an indubitable impact on the reliability of sensing operation, which should not be avoided in the realistic analysis.
where Vbias is the voltage across MTJ nanopillar, j is current density, k is thermal conductivity, thickb is thickness of oxide barrier, T0 is room temperature, CV is heat capacity per unit volume and thicks is total thickness of MTJ. As square current pulses are often used for logic and memory circuit design and simulation, the equation can be simplified to [22]:
sth ¼
C v thicks k=thickb
T heat ¼ T 0 þ
ð6Þ
V bias j Dheat 1 exp k=thickb sth
Dcool T cool ¼ T 0 þ ðT heat T 0 Þ exp
sth
ð7Þ
ð8Þ
where sth is the characteristic heating/cooling time, Dheat and Dcool is the heating and cooling current pulse duration, Theat and Tcool present respectively the temperatures of MTJ during heating/cooling operations.
Fig. 6. MC simulations of 100 sensing operations.
Y. Wang et al. / Microelectronics Reliability 54 (2014) 1774–1778
Fig. 7. Dependence of the maximal temperature variation on the thickness of oxide barrier tox and area of MTJ.
1777
Fig. 8. Estimated lifetime of dielectric breakdown versus applied bias voltage for optimally annealed MTJs with different values of oxide barrier and area of 40 40 nm.
4.3. MTJ parameters dependent temperature tolerance analysis Moreover, as the temperature tolerance of FPGA circuits is usually limited (218–398 K) [23] and the temperature increase of MTJ can reduce the operating temperature range of MTJ-based integrated logic circuits, the temperature should not exceed the limit (e.g. 388 K @ 90 nm) [24]. Thus, the parameters of MTJ should be carefully chosen to assure the best performance. An analysis is executed to find the dependence of the maximal increase of the temperature on the thickness of oxide barrier tox and the area of MTJ (10 10 nm2, 20 20 nm2, 40 40 nm2). From the results shown in Fig. 7, we find that tox should be small enough to guarantee the sufficient temperature tolerance of MTJ. As expected, the temperature is proportional to the power density j Vbias [21] and the area has no impact on temperature increase. From Eq. (7), the maximal increase value of the temperature can be described by 2
DT max ¼
V bias j Area R j ¼ k=thickb k=thickb
ð9Þ
where R is the magnetoresistance of MTJ [25]:
R/
FðtoxÞ Area
ð10Þ
where F(tox) is a function of tox and some constants, then
DT max /
V bias j Fðtox Þ j ¼ k=thickb k=thickb
2
ð11Þ
Compared with the result obtained in Fig. 4, there is a tradeoff between the tolerance of temperature and writing/reading reliability in term of tox. A lower reading error rate can be achieved by a higher value of tox, which thereby necessities a higher writing current. From Eq. (10), the value of resistance increases as tox increases, which results in a lower rate of erroneous writing by reading current because the current is smaller. Simultaneously, Eq. (11) shows that a higher value of tox results in a more obvious temperature increase. 5. Dielectric breakdown of MTJ Dielectric breakdown is one of the most important concerns for MTJs [26–28]. It can occur through two distinct mechanisms [27]: intrinsic breakdown and extrinsic breakdown. The former occurs due to the action of applied intense electrical field, which leads to an abrupt decrease of the electrical resistance. It forms therefore microscopic ohmic shorts in the barrier [26]. The latter is caused by
the growth of existing pinholes in the tunnel barrier due to localized heating by high current flowing along such pinholes [28]. The former mechanism is added into this model which is based on the E-model [29]:
lnðTFÞ /
DH 0 c Eox kB T
ð12Þ
where TF is the time to failure, DH0 is the enthalpy of activation (usually referred to as activation energy), Eox is the electric field in the oxide, and c is the field acceleration parameter. Fig. 8 shows the time to failure as function of the applied bias voltage. The lifetime for MTJ with 0.85 nm thick barrier can be estimated to 108.4988 s (10 years) for a typical operating voltage of 400 mV. This result is consistent with the value referred in [30]. 6. Conclusion and perspectives This paper presented a compact model of MTJ with STT stochastic behavior. The Joule heating effects, technical parameter variations and dielectric breakdown of MgO have also been taken into account to improve its simulation accuracy. We perform Monte-Carlo simulations to validate its functionality for writing and sensing processes. By using this compact model, a more realistic reliability prediction and analyses can be efficiently carried out for more complex hybrid MTJ/CMOS systems before fabrication, which will significantly benefit for realizing future non-volatile logic and memory applications. Moreover, this model has a high compatibility with different dimensions of CMOS design kit under Cadence. As an extension of this work, the impact of current pulse width on the dielectric breakdown [11] is under investigation. Acknowledgements The authors would like to acknowledge support from Nanodesign project of French Paris-Saclay Idex Program and French ANR-DIPMEM. References [1] Chappert C, Fert A, Van Dau FN. The emergence of spin electronics in data storage. Nat Mater 2007;6:813–23. [2] Ikeda S et al. A perpendicular-anisotropy CoFeB–MgO magnetic tunnel junction. Nat Mater 2010;9:721–4. [3] Slonczewski JC et al. Current-driven excitation of magnetic multilayers. J Magn Magn Mater 1996;159:L1.
1778
Y. Wang et al. / Microelectronics Reliability 54 (2014) 1774–1778
[4] Takemura R et al. High-scalable disruptive reading scheme for Gb-scale SPRAM and beyond. In: Proc in IEEE international memory workshop (IMW); 2010. p. 1–2. [5] Chen Y et al. Design margin exploration of spin-transfer torque RAM (STTRAM) in scaled technologies. IEEE Trans VLSI Syst 2010;18:12. [6] Zhang Y et al. Electrical modeling of stochastic spin transfer torque writing in magnetic tunnel junctions for memory and logic applications. IEEE Trans Magn 2013;49(7):4375–8. [7] Zhao WS et al. Failure and reliability analysis of STTMRAM. Microelectron Rel 2012;52:1848–52. [8] Xu W et al. Improving STT MRAM storage density through smaller-than-worstcase transistor sizing. In: Design automation conference; DAC’09; 2009. p. 87–90. [9] Devolder T et al. Single-shot time-resolved measurement of nanosecond-scale spin-transfer induced switching: stochastic versus deterministic aspects. Phys Rev Lett 2008;100:057206. [10] Castro MM et al. Processional spin-transfer switching in a magnetic tunnel junction with a synthetic anti-ferromagnetic perpendicular polarizer. J Appl Phys 2012;111:07C912. [11] Amara S et al. Barrier breakdown mechanisms in MgO-based magnetic tunnel junctions under pulsed conditions. In: 4th IEEE international memory workshop (IMW); 2012. [12] Julliere M et al. Tunneling between ferromagnetic films. Phys Lett A 1975;54:225–6. [13] Yuasa S et al. Giant room-temperature magnetoresistance in single-crystal Fe/ MgO/Fe magnetic tunnel junctions. Nat Mater 2004;3:868–71. [14] Tomita H et al. Unified understanding of both thermally assisted and precessional spin-transfer switching in perpendicularly magnetized giant magnetoresistive nanopillars. Appl Phys Lett 2013;102:042409. [15] Worledge DC et al. Spin torque switching of perpendicular Ta/CoFeB/MgO based magnetic tunnel junctions. Appl Phys Lett 2011;98:022501. [16] Sun JZ et al. Spin angular momentum transfer in a current-perpendicular spinvalve nanomagnet. In: Proc of SPIE vol. 5359.
[17] Heindl R et al. Validity of the thermal activation model for spin transfer torque switching in magnetic tunnel junctions. J Appl Phys 2011:109. [18] Cadence Verilog-a language reference.. [19] Hayakawa J et al. Current-induced magnetization switching in MgO barrier magnetic tunnel junctions with CoFeB based synthetic ferrimagnetic free layers. IEEE Trans Magn 2008;44:7. [20] Lee DH et al. Increase of temperature due to Joule heating during currentinduced magnetization switching of an MgO-based magnetic tunnel junction. Appl Phys Lett 2008;92:233502. [21] Sousa RC et al. Tunneling hot spots and heating in magnetic tunnel junctions. J Appl Phys 1995;95:6783–5. [22] Zhao WS et al. A compact model for magnetic tunnel junction (MTJ) switched by thermally assisted Spin transfer torque (TAS + STT). Nanoscale Res Lett 2011;6:368. [23] O’Neill K. FPGAs for space applications. Microsemi SOC Group; 2012. [24] Faber L et al. In: Proc in IEEE design & technology of integrated systems (DTIS); 2009. p. 130–5. [25] Zhang Y et al. Compact modeling of perpendicular-anisotropy CoFeB/MgO magnetic tunnel junctions. IEEE Trans Electron Dev 2012;59(3):819–26. [26] Oepts W et al. Analysis of breakdown in ferromagnetic tunnel junctions. J Appl Phys 1999;86:3863–72. [27] Oliver B et al. Two breakdown mechanisms in ultrathin alumina barrier magnetic tunnel junctions. J Appl Phys 2004;95:1315–22. [28] Oliver B et al. Dielectric breakdown in magnetic tunnel junctions having an ultrathin barrier. J Appl Phys 2002;91:4348–52. [29] McPherson JW et al. Underlying physics of the thermochemical E model in describing low-field time dependent dielectric breakdown in SiO2 thin films. J Appl Phys 1998;84:1513. [30] Min T et al. A study of write margin of spin torque transfer magnetic random access memory technology. IEEE Trans Magn 2010;46:2322.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses Y. Wang a,b, Y. Zhang a, E.Y. Deng a, J.O. Klein a, L.A.B. Naviner b, W.S. Zhao a,c,⇑ a
IEF, Univ. Paris-Sud/CNRS UMR 8622, Orsay 91405, France Laboratory LTCI-CNRS, Institut TELECOM, TELECOM ParisTech, Paris 75634, France c Spintronics Interdisciplinary Center, Beihang University, Beijing 100191, China b
a r t i c l e
i n f o
Article history: Received 25 June 2014 Accepted 8 July 2014 Available online 4 August 2014 Keywords: PMAMTJ Stochastic Resistance variation Temperature evaluation Dielectric breakdown
a b s t r a c t Spin transfer torque magnetic tunnel junction (STT MTJ) is considered as a promising candidate for non-volatile memories thanks to its low power, high speed and easy integration with CMOS process. However, it has been demonstrated intrinsically stochastic. This phenomenon leads to the frequent occurrence of switching errors, which results in considerable reliability issues of hybrid CMOS/MTJ circuits. This paper proposes a compact model of MTJ with STT stochastic behavior, in which technical variations and temperature evaluation are properly integrated. Moreover, the phenomenon of dielectric breakdown of MgO barrier which determines the lifetime of MTJ is also taken into consideration. Its accurate performances allow a more realistic reliability analysis involving the influences of ambient environment and technical process. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Spin transfer torque magnetic tunnel junction (STT MTJ) is one of the excellent candidates for magnetic logic and memory applications because of its high power efficiency, speed and infinite endurance [1,5]. Recent research has found that MTJ with perpendicular magnetic anisotropy (PMA) behaves better performances in terms of thermal stability, critical current and access speed compared with that with in-plane magnetic anisotropy [2]. However, the PMA STT MTJ still suffers from considerable reliability issues [4]. Firstly, the limited fabrication precision causes uncorrected errors [7,8], due to the deviations of oxide barrier thickness (tox), free layer thickness (tsl) and TMR ratio (Fig. 1). These errors can be avoided by the appropriate choice of parameters at the time of design. Secondly, STT switching mechanism has been demonstrated intrinsically stochastic [9] due to the thermal fluctuations of magnetization [10]. Caused by this phenomenon, the switching errors occur frequently. Thirdly, as most of the STT switching operations require high currents flowing through the MTJ [3], the dielectric breakdown of oxide barrier (e.g. MgO) is an important factor to determine its feasibility and influence the reliability of MTJ-based circuits [11]. Therefore, a spice-compatible ⇑ Corresponding author at: Spintronics Interdisciplinary Center, Beihang University, Beijing 100191, China. Tel.: +86 (10) 82314875. E-mail address: [email protected] (W.S. Zhao). http://dx.doi.org/10.1016/j.microrel.2014.07.019 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
model of PMA STT MTJ involving these three reliability factors is imperative for the reliability analysis for hybrid CMOS/MTJ circuits, which can assist to find a tradeoff among the performance parameters. This paper presents a compact model of MTJ demonstrating STT stochastic behaviors. The technical variations and temperature evaluation have been considered to improve the simulation accuracy. The dielectric breakdown of MgO is also integrated to estimate the lifetime of MTJ, which offers the designers an approach to estimate the endurance of MTJ. By performing Monte-Carlo (MC) simulations, we validate its functionality in both writing and sensing processes. In addition, reliability analysis is performed to propose some assets for minimizing the impact of hard errors on circuit reliability. 2. Stochastic model of MTJ Depending on the magnitude of switching current, the stochastic behavior can also be divided into two regimes [14]: Sun model (I > Ic0) [15] and Neel-brown model (I < Ic0) [16,17]. The former is also called precessional switching which addresses fast switching (sub 3 ns) but consumes more energy with high current density. Reversely, the latter consumes less with low current density but offers a slower switching which is called thermally-assisted switching. For PMA STT MTJ, these two regimes are isolated by the critical current which can be described as follows [2,6]:
Y. Wang et al. / Microelectronics Reliability 54 (2014) 1774–1778
1775
Fig. 1. Magnetic tunnel junction (MTJ) consists of three layers: two ferromagnetic layers separated by an oxide barrier. The nanopillar resistance (RP, RAP) depends on the corresponding state of the magnetization of the two ferromagnetic layers Parallel (P) or Anti-Parallel (AP) [12]. The resistance difference is characterized by Tunnel Magnetoresistance Ratio TMR = (RAP RP)/RP [13]. With spin transfer torque mechanism, MTJ changes between two states when a bidirectional current I is higher than the critical current Ic0 [1].
Ic0 ¼ a
E¼
ce ce ðl M ÞH V ¼ 2a E lB g 0 s K lB g
l0 Ms HK V
ð1Þ
ð2Þ
2
where E is the barrier energy, HK is the effective anisotropy field, l0 is permeability of free space, Ms is the saturation magnetization, a is the magnetic damping constant, c is the gyromagnetic ratio, e is the elementary charge, lB is the Bohr magneton, V is the volume of the free layer, kffi B is the Boltzmann constant, and g ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi TMRðTMR þ 2Þ=2ðTMR þ 1Þ is the spin polarization efficiency factor. The switching duration for the two regimes can be calculated as follows [15,17]:
s ¼ s0 exp
Fig. 3. MC simulations of 1000 complete writing process with the stochastic behaviors. The switching duration is set following a normal distribution with variation of 0.02.
E I 1 ðI > Ic0 Þ kB T Ic0
" # lB Pref 1 2 ¼ ðI Ic0 Þ ðI < Ic0 Þ 2 hsi C þ lnðp4 nÞ emm ð1 þ Pref Pfree Þ
ð3Þ
ð4Þ
where E is the barrier energy, s0 is the attempt period, T is the temperature, kB is the Boltzmann constant, C 0.577 is the Euler’s constant, n = E/kBT is the thermal stability factor, mm is the magnetization moment, e is the elementary charge, P is the tunneling spin polarizations. The stochastic behaviors and technical variations are integrated in the model by using the random functions and statistical block, which are provided by Verilog-A under Cadence environment
(a)
[18]. For instance, $rdist_uniform generates a uniform distribution in a limited area and $rdist_normal generates a normal distribution with fixed mean value and standard deviation. The users are free to choose different types of statistical distributions for different parameters (tsl, tox, TMR and switching duration s). Using the circuit shown in Fig. 2(a), Monte-Carlo simulations of 1000 writing processes are performed in which the switching duration follows a normal distribution with the mean value of sp?ap or sap?p and variation of 0.02. The results (Fig. 3) demonstrate that the static switching durations (without stochastic behavior) are sp?ap = 1.4716 ns and sap?p = 2.4898 ns. As expected all the values of switching duration for parallel (P) state to antiparallel (AP) state are in the interval [0.98sp?ap, 1.02sp?ap]. It follows a normal distribution around the average switching delay time sp?ap and the variation set. On the other hand, for AP to P state, there are 98% values of switching duration in the interval [0.98sap?p, 1.02sap?p]. As the voltage is identical for both states, the current for AP state is lower than P state, which leads to a longer switching duration [9] and higher error rate of switching.
3. MTJ parameters dependent reliability analysis We did a reliability analysis based on the PCSA circuit (Fig. 2(b)) to investigate the dependence of reading error rate on area of MTJ
(b)
Fig. 2. (a) Circuit for STT writing which can generate a bidirectional current. (b) Pre-charge sense amplifier.
1776
Y. Wang et al. / Microelectronics Reliability 54 (2014) 1774–1778
Fig. 4. Dependence of reading error rate on the thickness of oxide barrier tox and area of MTJ.
and oxide barrier thickness tox. The results (see Fig. 4) show that both reducing the transistor size and enlarging the thickness of oxide barrier can sufficiently improve the reliability of hybrid CMOS/MTJ circuits. 4. Temperature evaluation model 4.1. Temperature increase due to Joule heating For the purpose of storing information for over 10 years in the high-density MRAM, the thermal stability factor (n) should exceed 60 [19]. In spite of optimization in the past several years, a large current density of several MA/cm2 is always needed for currentinduced magnetization switching [20,8], which heats up the MTJ due to Joule heating. The equations presented above (Eqs. (3) and (4)) show that thermal fluctuation affects deeply the STT dynamic behaviors of MTJ, especially the switching duration. Thus, it is essential to investigate the effects of the temperature increase during current pulses. In this model, the thermal heating of MTJ is integrated through the one-dimensional numerical calculation, which can be given as follows [21]:
V bias j
k dT ðT T 0 Þ ¼ C v thicks thickb dt
ð5Þ
Fig. 5. 100 MC simulations of writing with fixed (STATE) and variable temperature (STATE_T).
4.2. Effect of temperature increase on writing and reading of hybrid CMOS/MTJ circuits To investigate the impact of variable temperature on the dynamic of MTJ, we have performed MC simulations of 100 writing operations using the circuit shown in Fig. 2(a). The cases with and without considering Joule heating are carried out respectively. The simulation results (see Fig. 5) show a writing error rate of 20% for fixed temperature and 22% for the model of Joule heating. As the temperature increases due to Joule heating, the thermal stability degrades (n decreases) and a higher current is needed for switching the state. As a consequence, the performance and reliability of the device will get worse by considering the Joule heating [20]. Furthermore, we validate this model for the sensing operation in which the pre-charge sensing amplifier (PCSA) as shown in Fig. 2(b) is used. The MC simulation results (Fig. 6) exhibit an error rate of 20% due to either mismatch and process variations of CMOS devices or stochastic behaviors with Joule heating of MTJ. When we eliminate the influence of temperature, the error rate is then 19%. We also perform MC simulations for this circuit without stochastic behavior, which results in an error rate of 6%. By comparing these results, we find that the stochastic behavior of MTJ plays a more obvious role than Joule heating. Nevertheless, the temperature has an indubitable impact on the reliability of sensing operation, which should not be avoided in the realistic analysis.
where Vbias is the voltage across MTJ nanopillar, j is current density, k is thermal conductivity, thickb is thickness of oxide barrier, T0 is room temperature, CV is heat capacity per unit volume and thicks is total thickness of MTJ. As square current pulses are often used for logic and memory circuit design and simulation, the equation can be simplified to [22]:
sth ¼
C v thicks k=thickb
T heat ¼ T 0 þ
ð6Þ
V bias j Dheat 1 exp k=thickb sth
Dcool T cool ¼ T 0 þ ðT heat T 0 Þ exp
sth
ð7Þ
ð8Þ
where sth is the characteristic heating/cooling time, Dheat and Dcool is the heating and cooling current pulse duration, Theat and Tcool present respectively the temperatures of MTJ during heating/cooling operations.
Fig. 6. MC simulations of 100 sensing operations.
Y. Wang et al. / Microelectronics Reliability 54 (2014) 1774–1778
Fig. 7. Dependence of the maximal temperature variation on the thickness of oxide barrier tox and area of MTJ.
1777
Fig. 8. Estimated lifetime of dielectric breakdown versus applied bias voltage for optimally annealed MTJs with different values of oxide barrier and area of 40 40 nm.
4.3. MTJ parameters dependent temperature tolerance analysis Moreover, as the temperature tolerance of FPGA circuits is usually limited (218–398 K) [23] and the temperature increase of MTJ can reduce the operating temperature range of MTJ-based integrated logic circuits, the temperature should not exceed the limit (e.g. 388 K @ 90 nm) [24]. Thus, the parameters of MTJ should be carefully chosen to assure the best performance. An analysis is executed to find the dependence of the maximal increase of the temperature on the thickness of oxide barrier tox and the area of MTJ (10 10 nm2, 20 20 nm2, 40 40 nm2). From the results shown in Fig. 7, we find that tox should be small enough to guarantee the sufficient temperature tolerance of MTJ. As expected, the temperature is proportional to the power density j Vbias [21] and the area has no impact on temperature increase. From Eq. (7), the maximal increase value of the temperature can be described by 2
DT max ¼
V bias j Area R j ¼ k=thickb k=thickb
ð9Þ
where R is the magnetoresistance of MTJ [25]:
R/
FðtoxÞ Area
ð10Þ
where F(tox) is a function of tox and some constants, then
DT max /
V bias j Fðtox Þ j ¼ k=thickb k=thickb
2
ð11Þ
Compared with the result obtained in Fig. 4, there is a tradeoff between the tolerance of temperature and writing/reading reliability in term of tox. A lower reading error rate can be achieved by a higher value of tox, which thereby necessities a higher writing current. From Eq. (10), the value of resistance increases as tox increases, which results in a lower rate of erroneous writing by reading current because the current is smaller. Simultaneously, Eq. (11) shows that a higher value of tox results in a more obvious temperature increase. 5. Dielectric breakdown of MTJ Dielectric breakdown is one of the most important concerns for MTJs [26–28]. It can occur through two distinct mechanisms [27]: intrinsic breakdown and extrinsic breakdown. The former occurs due to the action of applied intense electrical field, which leads to an abrupt decrease of the electrical resistance. It forms therefore microscopic ohmic shorts in the barrier [26]. The latter is caused by
the growth of existing pinholes in the tunnel barrier due to localized heating by high current flowing along such pinholes [28]. The former mechanism is added into this model which is based on the E-model [29]:
lnðTFÞ /
DH 0 c Eox kB T
ð12Þ
where TF is the time to failure, DH0 is the enthalpy of activation (usually referred to as activation energy), Eox is the electric field in the oxide, and c is the field acceleration parameter. Fig. 8 shows the time to failure as function of the applied bias voltage. The lifetime for MTJ with 0.85 nm thick barrier can be estimated to 108.4988 s (10 years) for a typical operating voltage of 400 mV. This result is consistent with the value referred in [30]. 6. Conclusion and perspectives This paper presented a compact model of MTJ with STT stochastic behavior. The Joule heating effects, technical parameter variations and dielectric breakdown of MgO have also been taken into account to improve its simulation accuracy. We perform Monte-Carlo simulations to validate its functionality for writing and sensing processes. By using this compact model, a more realistic reliability prediction and analyses can be efficiently carried out for more complex hybrid MTJ/CMOS systems before fabrication, which will significantly benefit for realizing future non-volatile logic and memory applications. Moreover, this model has a high compatibility with different dimensions of CMOS design kit under Cadence. As an extension of this work, the impact of current pulse width on the dielectric breakdown [11] is under investigation. Acknowledgements The authors would like to acknowledge support from Nanodesign project of French Paris-Saclay Idex Program and French ANR-DIPMEM. References [1] Chappert C, Fert A, Van Dau FN. The emergence of spin electronics in data storage. Nat Mater 2007;6:813–23. [2] Ikeda S et al. A perpendicular-anisotropy CoFeB–MgO magnetic tunnel junction. Nat Mater 2010;9:721–4. [3] Slonczewski JC et al. Current-driven excitation of magnetic multilayers. J Magn Magn Mater 1996;159:L1.
1778
Y. Wang et al. / Microelectronics Reliability 54 (2014) 1774–1778
[4] Takemura R et al. High-scalable disruptive reading scheme for Gb-scale SPRAM and beyond. In: Proc in IEEE international memory workshop (IMW); 2010. p. 1–2. [5] Chen Y et al. Design margin exploration of spin-transfer torque RAM (STTRAM) in scaled technologies. IEEE Trans VLSI Syst 2010;18:12. [6] Zhang Y et al. Electrical modeling of stochastic spin transfer torque writing in magnetic tunnel junctions for memory and logic applications. IEEE Trans Magn 2013;49(7):4375–8. [7] Zhao WS et al. Failure and reliability analysis of STTMRAM. Microelectron Rel 2012;52:1848–52. [8] Xu W et al. Improving STT MRAM storage density through smaller-than-worstcase transistor sizing. In: Design automation conference; DAC’09; 2009. p. 87–90. [9] Devolder T et al. Single-shot time-resolved measurement of nanosecond-scale spin-transfer induced switching: stochastic versus deterministic aspects. Phys Rev Lett 2008;100:057206. [10] Castro MM et al. Processional spin-transfer switching in a magnetic tunnel junction with a synthetic anti-ferromagnetic perpendicular polarizer. J Appl Phys 2012;111:07C912. [11] Amara S et al. Barrier breakdown mechanisms in MgO-based magnetic tunnel junctions under pulsed conditions. In: 4th IEEE international memory workshop (IMW); 2012. [12] Julliere M et al. Tunneling between ferromagnetic films. Phys Lett A 1975;54:225–6. [13] Yuasa S et al. Giant room-temperature magnetoresistance in single-crystal Fe/ MgO/Fe magnetic tunnel junctions. Nat Mater 2004;3:868–71. [14] Tomita H et al. Unified understanding of both thermally assisted and precessional spin-transfer switching in perpendicularly magnetized giant magnetoresistive nanopillars. Appl Phys Lett 2013;102:042409. [15] Worledge DC et al. Spin torque switching of perpendicular Ta/CoFeB/MgO based magnetic tunnel junctions. Appl Phys Lett 2011;98:022501. [16] Sun JZ et al. Spin angular momentum transfer in a current-perpendicular spinvalve nanomagnet. In: Proc of SPIE vol. 5359.
[17] Heindl R et al. Validity of the thermal activation model for spin transfer torque switching in magnetic tunnel junctions. J Appl Phys 2011:109. [18] Cadence Verilog-a language reference.