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Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON
Microelectronic Engineering 86 (2009) 268–271
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON Won-Ho Choi a, In-Shik Han a, Hyuk-Min Kwon a, Tae-Gyu Goo a, Min-Ki Na a, Ook-Sang Yoo a,b,c, Ga-Won Lee a, Chang Yong Kang c, Rino Choi d, Seung Chul Song c, Byoung Hun Lee c, Raj Jammy c,e, Yoon-Ha Jeong f, Hi-Deok Lee a,b,c,* a
Department of Electronics Engineering, Chungnam National University, Yusong-Gu, Daejeon 305-764, Republic of Korea University of Texas at Austin, USA c SEMATECH, Austin, TX 78741, USA d Inha University, Republic of Korea e IBM Assignee f Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Republic of Korea b
a r t i c l e
i n f o
Article history: Received 26 September 2007 Received in revised form 15 February 2008 Accepted 13 April 2008 Available online 12 May 2008 Keywords: High-k HfLaON HfLaSiON Device performance PBTI Hot carrier Reliability
a b s t r a c t For the first time, we present a comparative study on HfLaSiON and HfLaON gate dielectric with an equivalent oxide thickness (EOT) of 0.8 nm (Tinv = 1.2 nm). A detailed DC analysis of Ion vs. Ioff shows HfLaON performs somewhat better than HfLaSiON. However, positive bias temperature instability (PBTI) lifetime of HfLaSiON is higher than HfLaON by about 2 orders of magnitude. On the other hand, hot carrier stress lifetime for HfLaSiON was similar to that of HfLaON. From the activation energy and U-trap, we found that the cause of different threshold voltage (VT) shifts under PBT stress and detrapping was originated from stable electron traps induced by different charge trapping rates. Ó 2008 Elsevier B.V. All rights reserved.
1. Introduction High-k dielectrics have been extensively studied for their application to metal–oxide–silicon field effect transistors (MOSFETs) as an alternative gate dielectric material to SiO2 because ultra-thin SiO2 has an extremely high gate leakage current due to direct tunneling current [1]. Hafnium oxide (HfO2), however, suffers from significant charge trapping in pre-existing traps, which is the cause of VT instability, mobility degradation, and reliability degradation, as reported by Zafar [2]. Hafnium silicate, another potential candidate, though has lower dielectric constants, has better leakage characteristics, lower mobility degradation [3], and a higher crystallization temperature than the hafnium oxide [4]. Recently, it has been reported that incorporating La in HfO2 [5] and HfSiO [6,7] can tune the work function of metal gate to near the Si conduction band edge for high performance CMOS technology. Incorporating La in HfO2 and HfSiO also can improve the electrical performances of MOSFETs. However, little has been reported on * Corresponding author. Address: Department of Electronics Engineering, Chungnam National University, Yusong-Gu, Daejeon 305-764, Republic of Korea. Tel.: +82 42 821 6868; fax: +82 42 823 9544. E-mail address: [email protected] (H.-D. Lee). 0167-9317/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2008.04.008
the comparison of device performance and reliability of HfSiO and HfO2 that incorporate La under the PBT and hot carrier stress. The purpose of this work is to systematically compare MOSFETs with the HfO2 (HfLaON) and HfSiO (HfLaSiON) in terms of device and reliability characteristics.
2. Experimental details The process flow for device fabrication is summarized as follows. After shallow trench isolation and well formation, HfSiO (2 nm) and HfO2 (2 nm) films were deposited on ultra-thin SiO2 (<1 nm) using atomic layer deposition (ALD) process followed by a post deposition treatment including thermal NH3. Ultra-thin La2O3 (0.5 nm) was deposited on HfSiO and HfO2 by molecular beam deposition (MBD) process. TaN metal gate (10 nm) was deposited on the dielectric stack and capped with poly-Si. 1070 °C spike anneal was used after source/drain (S/D) implantation. Detailed process conditions can be found in [6,7]. Current–voltage (I–V) and reliability and capacitance–voltage (C–V) characteristics were measured using an Agilent 4156C semiconductor parameter analyzer and an HP4280A C-V Plotter, respectively. Periodical stress and ID–VG measurements were controlled
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by the MATLAB program to minimize the delay between the stress and ID–VG measurements. Threshold voltage was extracted using the constant current method to avoid extrapolation errors due to the fluctuation of transconductance.
4
Gate Current Density A/cm2
3. Results and discussion
2
W/L=20/20μm
10
0
10
-2
10
-4
10
HfLaSiON
-6
10
HfLaSiON HfLaON
-8
10
HfLaON
-10
10
-2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
2.0
Gate Voltage (V) Fig. 2. Gate current density vs. gate voltage for a MOSFET with W/L of 20/20 lm. Gate current density of HfLaSiON and HfLaON is 65.7 A/cm2 and 11.6 A/cm2, respectively at VG = Vfb 1 V. Inset graph shows temperature dependence of gate current.
-3
-4
Drain Current A/μm
-5
10 10
10 Filled: HfLaSiON Open: HfLaON
VD=1.2V -6
10 W=10μm L=70nm
-5
10
-7
10
-6
10
-8
-7
10
10
-9
10
-8
10 -0.6
Gate Current A/μm
a
-10
-0.4
-0.2
0.0
0.2
0.4
10 0.6
VG -VT (V)
b Ioff @ VG -VT = -0.1V A/μm
Devices with HfLaON and HfLaSiON show well-behaved C–V characteristics as in Fig. 1, and their EOTs are almost the same, about 0.8 nm (Tinv 1.2 nm), which is enough for the 45 nm CMOS node. The gate current of HfLaSiON is higher than HfLaON as shown in Fig. 2. The gate current density at Vfb 1 V is 65.7 A/ cm2 (HfLaSiON) and 11.6 A/cm2 (HfLaON), respectively. Although the gate current of HfLaSiON is higher than that of HfLaON, the leakage current level of the ultra-thin La-based HfLaON and HfLaSiON is acceptable for nano-scale CMOSFETs as shown in [7]. Temperature dependence of gate current was shown in inset of Fig. 2. As shown in inset graph of Fig. 2, the temperature dependence is insignificant, which is due to thin high-k film. Thus, leakage current is dominated by tunneling current. Both MOSFETs exhibit good ID–VG characteristics as in Fig. 3a. The higher drain current of HfLaSiON at low voltage regions is due to the higher gate leakage current. However, Ion vs. Ioff shows HfLaON performs somewhat better than HfLaSiON. Ioff is picked up at VG–VT = 0.1 V to exclude the gate current component in the drain current as shown in Fig. 3a. Fig. 4 shows the effective mobility obtained by the split C–V method for different gate lengths (Lgate = 70 nm, 1 lm). HfLaSiON exhibits a little higher mobility than HfLaON about 3%; the high field (1 MV/cm) mobility of both structures at Lgate = 1 lm is 81–84% of universal mobility. As the integration of analog and digital MOSFETs on a chip is highly necessary for system on a chip or mixed signal applications, the analog performance of the two dielectrics is also compared in Fig. 5. HfLaON has a little better analog performance or greater drain output resistance, Rout and larger DC gain than HfLaSiON. Fig. 6 compares device degradation by PBT stress (125 °C, VG = VT + stress) and channel hot carrier (CHC) stress (25 °C, VG = VD = VT + stress), at various stress voltages. Lifetime is defined at the point where DVT becomes 50 mV. For PBT stress, the lifetime of HfLaSiON is 2 orders of magnitude greater than HfLaON at the same stress voltage. However, for CHC stress, the lifetime of HfLaSiON is slightly higher than that of HfLaON. It is noteworthy that reliability is dominated by HC stress i.e., HC lifetime is less than PBTI lifetime in both cases. Detrapping characteristics under PBT stress is compared in Fig. 7. HfLaON clearly has much more trapping and detrapping (detrapping voltage = 1 V) of electrons during stress, as shown
10
-5
10
HfLaSiON HfLaON
-6
10
-7
10
400
450
500
550
600
Ion @VG -VT = 0.6V μA/μm 4
Capacitance μF/cm 2
HfLaSiON HfLaON
Fig. 3. Comparison of device performance. (a) Drain current, ID vs. VG–VT, and (b) Ion vs. Ioff. Two MOSFETs shows almost identical characteristics except VG–VT < 0.2 V where ID is dominated by the gate current. Ion vs. Ioff shows slightly better characteristics for HfLaON. Ioff is picked up at VG–VT = 0.1 V to exclude the gate current component.
Area: 400 μm2
3
2
1 EOT = 0.8nm 0 -1.5 -1.0 -0.5
Tinv = 1.2nm 0.0
0.5
1.0
Gate Voltage (V) Fig. 1. C–V characteristics of HfLaSiON and HfLaON. Their EOTs is only 0.8 nm (Tinv = 1.2 nm), which is suitable for the 45 nm CMOS node.
in Fig. 7a. Fig. 7b shows stress voltage-dependent reversible and irreversible DVT after 1000s stress followed by 1000s detrapping. Only the HfLaON case demonstrated a strong dependence of irreversible VT on stress voltage while reversible VT does not depend on the stress voltage for either structures. The different behavior of the VT shifts under detrapping conditions is explained by the U-trap [8,9]. That is, under the positive bias, electrons are injected into the dielectric and the neutral vacancy will capture one electron. The one trapped electron becomes a meta-stable state and
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500
10
universal mobility HfLaSiON HfLaON
300
< 10 years > 7
10
Lifetime (sec)
2
Mobility cm /V-s
400 Filled: 70nm Open: 1μm
200 100
3
10
o
Filled: PBTI 125 C o Open: CHC 25 C
1
0 0.0
0.5
1.0
10 0.5
1.5
1.0
Effective Field (MV/cm)
1.5
2.0
2.5
VG -VT (V)
Fig. 4. Comparison of mobility. High field (1 MV/cm) mobility of HfLaSiON and HfLaON is 51–52% at Lgate = 70 nm (81–84% at Lgate = 1 lm) of universal mobility.
Fig. 6. Comparison of CHC and PBTI. HfLaSiON exhibits better PBTI immunity but degradation of CHC stress is similar for HfLaSiON and HfLaON.
15
100
VG=VT+0.1V 12 9 6
Filled: HfLaSiON Open: HfLaON o 125 C
VG -VT =1.4V VG -VT =1.6V
80 ΔVT (mV)
Drain Rout (kohm)
Lgate=70nm
HfLaSiON HfLaON
5
10
VG -VT =1.8V
60 40 20
3 0 400
HfLaSiON HfLaON 450
0 detrapping voltage=-1V
L=70nm 500
550
600
0
1000
ID @VG -VT =0.6V μA/μm
2000 Time (sec)
3000
4000
50
50
HfLaSiON HfLaON
40
40
ΔVT (mV)
DC gain (Rout * gm)
VG =VT+0.1V
30
30 Filled: Reversible VT
20
Open: Irreversible VT 10
20 HfLaSiON HfLaON 10 400
0 1.4
450
500
550
600
the captured electron can be detrapped by Poole-Frenkel emission. The second electron trapping transforms the meta-stable state into a stable state. Because the stable state has a deeper energy level than meta-stable state, detrapping of electrons in the stable state is slow. Therefore, the different behavior of the VT shifts under detrpping is due to the difference in the amount of electrons in stable states. For more information about charge trapping under the PBT stress, we extracted activation energy from an Arrehnius plot of the VT shift as shown in Fig. 8. The activation energy of HfLaSiON is 0.047 eV and HfLaON is 0.051 eV, respectively. The low activation energy indicates that charge trapping is dominated by the di-
1.6
1.7
1.8
VG -VT (V)
ID @VG -VT =0.6V μA/μm Fig. 5. Comparison of analog performance. (a) Rout vs. drain current and (b) DC gain vs. drain current. HfLaON shows better analog performance as the Rout of HfLaON is greater than HfLaSiON at the same drain current. The DC gain of HfLaON also indicates slightly better analog performance.
1.5
Fig. 7. Comparison of detrapping characteristics. (a) DVT vs. stress time with sequential trapping and detrapping, and (b) DVT vs. stress voltage. HfLaON exhibits larger charge trapping and detrapping (detrapping voltage of 1 V) than HfLaON and both of the reversible and irreversible VT of HfLaON is larger than HfLaSiON (after 1000 s stress followed by 1000s detrapping ( 1 V)).
rect tunneling of electrons as explained in [10]. Because the activation energy provides a measure of the migration of trapped electrons to other traps, similar activation energy of devices shows that the trap energy level of HfLaSiON and HfLaON is similar [11]. Therefore, the different charge trapping and detrapping behaviors may be due to different pre-existing trap densities at the same energy level. 4. Conclusions The device performance and reliability characteristics of MOSFETs with HfLaSiON and HfLaON are compared in depth. MOSFETs
W.-H. Choi et al. / Microelectronic Engineering 86 (2009) 268–271
Acknowledgement
-2.0
Ln ΔVT @ 1000sec (V)
271
HfLaSiON HfLaON
-2.5
This work was supported in part by the Research Program of the National Center for Nanomaterials Technology (NCNT), Korea.
Ea=0.051eV
-3.0
References
-3.5 -4.0 Ea=0.047eV
-4.5
VG =1.8+VT -5.0 28
30
32
34
1/kT eV
36
38
40
-1
Fig. 8. Arrhenius plot of the VT shift under PBT stress.
with HfLaON exhibit better digital and analog performance than those with HfLaSiON while HfLaSiON shows better reliability characteristics or less device degradation by PBT and CHC stresses than HfLaON. Therefore, digital and analog performance as well as reliability characteristics should be considered in developing high-k dielectrics that incorporate La for high performance CMOS technology.
[1] S.A. Compbell, J. Yan, IEEE Trans. Electron Dev. 44 (1997) 104. [2] S. Zafar, A. Callegari, E. Gusev, M.V. Fischetti, in: Proc. IEDM, 2002. [3] A. Morioka, H. Watanabe, M. Miyamura, T. Tatsumi, M. Saitoh, T. Ogura, T. Iwamoto, T. Ikarashi, Y. Saito, Y. Okada, H. Watanabe, Y. Mochiduki, T. Mogami, in: Proc. VLSI Symp., 2003. [4] C.D. Young, G. Bersuker, G.A. Brown, C.Lim, P. Lysaght, P. Zeitzoff, R.W. Murto, H.R. Huff, IEEE IRW Final Report, 2003. [5] X.P. Wang, M.F. Li, C. Ren, X.F. Yu, C. Shen, H.H. Ma, A. Chin, C.X. Zhu, J. Ning, M.B. Yu, D.L. Kwong, IEEE Electron Dev. Lett. 27 (2006) 31–33. [6] H.N. Alshareef, H.R. Harris, H.C. Wen, C.S. Park, C. Huffman, K. Choi, H.F. Luan, P. Majhi, B.H. Lee, R. Jammy, D.J. Lichtenwalner, J.S. Jur, A.I. Kingon, in: Proc. VLSI Symp., 2006. [7] P.D. Kirch, M.A. Quevedo-Lopez, S.A. Krishnan, C. Krug, H. Alshareef, C.S. Park, R. Harris, N. Moumen, A. Neugroschel, G. Bersuker, B.H. Lee, J.G. Wang, G. Pant, B.E. Gnade, M.J. Kim, R.M. Wallace, J.S. Jur, D.J. Lichtenwalner, A.I. Kingon, R. Jammy, in: Proc. IEDM, 2006. [8] C. Shen, M.F. Li, X.P. Wang, H.Y. Yu, Y.P. Feng, A.T.-L. Lim, Y.C. Yeo, D.S.H. Chan, D.L. Kwong, in: Proc. IEDM, 2004. [9] G. Ribes, M. Denais, S. Bruyere, D. Roy, F. Monsieur, V. Huard, C. Parthasarthy, M. Muller, T. Skotnicki, G. Ghibaudo, in: Proc. ESSDERC, 2005. [10] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, G. Ghibaudo, IEEE TDMR 5 (2005) 5–19. [11] S. Krishnan, M. Quevedo-Lopez, H.J. Li, P. Kirsch, R. Choi, C. Young, J.J. Peterson, B.H. Lee, G. Bersuker, J.C. Lee, IEEE IRPS (2006).
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON Won-Ho Choi a, In-Shik Han a, Hyuk-Min Kwon a, Tae-Gyu Goo a, Min-Ki Na a, Ook-Sang Yoo a,b,c, Ga-Won Lee a, Chang Yong Kang c, Rino Choi d, Seung Chul Song c, Byoung Hun Lee c, Raj Jammy c,e, Yoon-Ha Jeong f, Hi-Deok Lee a,b,c,* a
Department of Electronics Engineering, Chungnam National University, Yusong-Gu, Daejeon 305-764, Republic of Korea University of Texas at Austin, USA c SEMATECH, Austin, TX 78741, USA d Inha University, Republic of Korea e IBM Assignee f Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Republic of Korea b
a r t i c l e
i n f o
Article history: Received 26 September 2007 Received in revised form 15 February 2008 Accepted 13 April 2008 Available online 12 May 2008 Keywords: High-k HfLaON HfLaSiON Device performance PBTI Hot carrier Reliability
a b s t r a c t For the first time, we present a comparative study on HfLaSiON and HfLaON gate dielectric with an equivalent oxide thickness (EOT) of 0.8 nm (Tinv = 1.2 nm). A detailed DC analysis of Ion vs. Ioff shows HfLaON performs somewhat better than HfLaSiON. However, positive bias temperature instability (PBTI) lifetime of HfLaSiON is higher than HfLaON by about 2 orders of magnitude. On the other hand, hot carrier stress lifetime for HfLaSiON was similar to that of HfLaON. From the activation energy and U-trap, we found that the cause of different threshold voltage (VT) shifts under PBT stress and detrapping was originated from stable electron traps induced by different charge trapping rates. Ó 2008 Elsevier B.V. All rights reserved.
1. Introduction High-k dielectrics have been extensively studied for their application to metal–oxide–silicon field effect transistors (MOSFETs) as an alternative gate dielectric material to SiO2 because ultra-thin SiO2 has an extremely high gate leakage current due to direct tunneling current [1]. Hafnium oxide (HfO2), however, suffers from significant charge trapping in pre-existing traps, which is the cause of VT instability, mobility degradation, and reliability degradation, as reported by Zafar [2]. Hafnium silicate, another potential candidate, though has lower dielectric constants, has better leakage characteristics, lower mobility degradation [3], and a higher crystallization temperature than the hafnium oxide [4]. Recently, it has been reported that incorporating La in HfO2 [5] and HfSiO [6,7] can tune the work function of metal gate to near the Si conduction band edge for high performance CMOS technology. Incorporating La in HfO2 and HfSiO also can improve the electrical performances of MOSFETs. However, little has been reported on * Corresponding author. Address: Department of Electronics Engineering, Chungnam National University, Yusong-Gu, Daejeon 305-764, Republic of Korea. Tel.: +82 42 821 6868; fax: +82 42 823 9544. E-mail address: [email protected] (H.-D. Lee). 0167-9317/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2008.04.008
the comparison of device performance and reliability of HfSiO and HfO2 that incorporate La under the PBT and hot carrier stress. The purpose of this work is to systematically compare MOSFETs with the HfO2 (HfLaON) and HfSiO (HfLaSiON) in terms of device and reliability characteristics.
2. Experimental details The process flow for device fabrication is summarized as follows. After shallow trench isolation and well formation, HfSiO (2 nm) and HfO2 (2 nm) films were deposited on ultra-thin SiO2 (<1 nm) using atomic layer deposition (ALD) process followed by a post deposition treatment including thermal NH3. Ultra-thin La2O3 (0.5 nm) was deposited on HfSiO and HfO2 by molecular beam deposition (MBD) process. TaN metal gate (10 nm) was deposited on the dielectric stack and capped with poly-Si. 1070 °C spike anneal was used after source/drain (S/D) implantation. Detailed process conditions can be found in [6,7]. Current–voltage (I–V) and reliability and capacitance–voltage (C–V) characteristics were measured using an Agilent 4156C semiconductor parameter analyzer and an HP4280A C-V Plotter, respectively. Periodical stress and ID–VG measurements were controlled
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by the MATLAB program to minimize the delay between the stress and ID–VG measurements. Threshold voltage was extracted using the constant current method to avoid extrapolation errors due to the fluctuation of transconductance.
4
Gate Current Density A/cm2
3. Results and discussion
2
W/L=20/20μm
10
0
10
-2
10
-4
10
HfLaSiON
-6
10
HfLaSiON HfLaON
-8
10
HfLaON
-10
10
-2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
2.0
Gate Voltage (V) Fig. 2. Gate current density vs. gate voltage for a MOSFET with W/L of 20/20 lm. Gate current density of HfLaSiON and HfLaON is 65.7 A/cm2 and 11.6 A/cm2, respectively at VG = Vfb 1 V. Inset graph shows temperature dependence of gate current.
-3
-4
Drain Current A/μm
-5
10 10
10 Filled: HfLaSiON Open: HfLaON
VD=1.2V -6
10 W=10μm L=70nm
-5
10
-7
10
-6
10
-8
-7
10
10
-9
10
-8
10 -0.6
Gate Current A/μm
a
-10
-0.4
-0.2
0.0
0.2
0.4
10 0.6
VG -VT (V)
b Ioff @ VG -VT = -0.1V A/μm
Devices with HfLaON and HfLaSiON show well-behaved C–V characteristics as in Fig. 1, and their EOTs are almost the same, about 0.8 nm (Tinv 1.2 nm), which is enough for the 45 nm CMOS node. The gate current of HfLaSiON is higher than HfLaON as shown in Fig. 2. The gate current density at Vfb 1 V is 65.7 A/ cm2 (HfLaSiON) and 11.6 A/cm2 (HfLaON), respectively. Although the gate current of HfLaSiON is higher than that of HfLaON, the leakage current level of the ultra-thin La-based HfLaON and HfLaSiON is acceptable for nano-scale CMOSFETs as shown in [7]. Temperature dependence of gate current was shown in inset of Fig. 2. As shown in inset graph of Fig. 2, the temperature dependence is insignificant, which is due to thin high-k film. Thus, leakage current is dominated by tunneling current. Both MOSFETs exhibit good ID–VG characteristics as in Fig. 3a. The higher drain current of HfLaSiON at low voltage regions is due to the higher gate leakage current. However, Ion vs. Ioff shows HfLaON performs somewhat better than HfLaSiON. Ioff is picked up at VG–VT = 0.1 V to exclude the gate current component in the drain current as shown in Fig. 3a. Fig. 4 shows the effective mobility obtained by the split C–V method for different gate lengths (Lgate = 70 nm, 1 lm). HfLaSiON exhibits a little higher mobility than HfLaON about 3%; the high field (1 MV/cm) mobility of both structures at Lgate = 1 lm is 81–84% of universal mobility. As the integration of analog and digital MOSFETs on a chip is highly necessary for system on a chip or mixed signal applications, the analog performance of the two dielectrics is also compared in Fig. 5. HfLaON has a little better analog performance or greater drain output resistance, Rout and larger DC gain than HfLaSiON. Fig. 6 compares device degradation by PBT stress (125 °C, VG = VT + stress) and channel hot carrier (CHC) stress (25 °C, VG = VD = VT + stress), at various stress voltages. Lifetime is defined at the point where DVT becomes 50 mV. For PBT stress, the lifetime of HfLaSiON is 2 orders of magnitude greater than HfLaON at the same stress voltage. However, for CHC stress, the lifetime of HfLaSiON is slightly higher than that of HfLaON. It is noteworthy that reliability is dominated by HC stress i.e., HC lifetime is less than PBTI lifetime in both cases. Detrapping characteristics under PBT stress is compared in Fig. 7. HfLaON clearly has much more trapping and detrapping (detrapping voltage = 1 V) of electrons during stress, as shown
10
-5
10
HfLaSiON HfLaON
-6
10
-7
10
400
450
500
550
600
Ion @VG -VT = 0.6V μA/μm 4
Capacitance μF/cm 2
HfLaSiON HfLaON
Fig. 3. Comparison of device performance. (a) Drain current, ID vs. VG–VT, and (b) Ion vs. Ioff. Two MOSFETs shows almost identical characteristics except VG–VT < 0.2 V where ID is dominated by the gate current. Ion vs. Ioff shows slightly better characteristics for HfLaON. Ioff is picked up at VG–VT = 0.1 V to exclude the gate current component.
Area: 400 μm2
3
2
1 EOT = 0.8nm 0 -1.5 -1.0 -0.5
Tinv = 1.2nm 0.0
0.5
1.0
Gate Voltage (V) Fig. 1. C–V characteristics of HfLaSiON and HfLaON. Their EOTs is only 0.8 nm (Tinv = 1.2 nm), which is suitable for the 45 nm CMOS node.
in Fig. 7a. Fig. 7b shows stress voltage-dependent reversible and irreversible DVT after 1000s stress followed by 1000s detrapping. Only the HfLaON case demonstrated a strong dependence of irreversible VT on stress voltage while reversible VT does not depend on the stress voltage for either structures. The different behavior of the VT shifts under detrapping conditions is explained by the U-trap [8,9]. That is, under the positive bias, electrons are injected into the dielectric and the neutral vacancy will capture one electron. The one trapped electron becomes a meta-stable state and
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W.-H. Choi et al. / Microelectronic Engineering 86 (2009) 268–271 9
500
10
universal mobility HfLaSiON HfLaON
300
< 10 years > 7
10
Lifetime (sec)
2
Mobility cm /V-s
400 Filled: 70nm Open: 1μm
200 100
3
10
o
Filled: PBTI 125 C o Open: CHC 25 C
1
0 0.0
0.5
1.0
10 0.5
1.5
1.0
Effective Field (MV/cm)
1.5
2.0
2.5
VG -VT (V)
Fig. 4. Comparison of mobility. High field (1 MV/cm) mobility of HfLaSiON and HfLaON is 51–52% at Lgate = 70 nm (81–84% at Lgate = 1 lm) of universal mobility.
Fig. 6. Comparison of CHC and PBTI. HfLaSiON exhibits better PBTI immunity but degradation of CHC stress is similar for HfLaSiON and HfLaON.
15
100
VG=VT+0.1V 12 9 6
Filled: HfLaSiON Open: HfLaON o 125 C
VG -VT =1.4V VG -VT =1.6V
80 ΔVT (mV)
Drain Rout (kohm)
Lgate=70nm
HfLaSiON HfLaON
5
10
VG -VT =1.8V
60 40 20
3 0 400
HfLaSiON HfLaON 450
0 detrapping voltage=-1V
L=70nm 500
550
600
0
1000
ID @VG -VT =0.6V μA/μm
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3000
4000
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50
HfLaSiON HfLaON
40
40
ΔVT (mV)
DC gain (Rout * gm)
VG =VT+0.1V
30
30 Filled: Reversible VT
20
Open: Irreversible VT 10
20 HfLaSiON HfLaON 10 400
0 1.4
450
500
550
600
the captured electron can be detrapped by Poole-Frenkel emission. The second electron trapping transforms the meta-stable state into a stable state. Because the stable state has a deeper energy level than meta-stable state, detrapping of electrons in the stable state is slow. Therefore, the different behavior of the VT shifts under detrpping is due to the difference in the amount of electrons in stable states. For more information about charge trapping under the PBT stress, we extracted activation energy from an Arrehnius plot of the VT shift as shown in Fig. 8. The activation energy of HfLaSiON is 0.047 eV and HfLaON is 0.051 eV, respectively. The low activation energy indicates that charge trapping is dominated by the di-
1.6
1.7
1.8
VG -VT (V)
ID @VG -VT =0.6V μA/μm Fig. 5. Comparison of analog performance. (a) Rout vs. drain current and (b) DC gain vs. drain current. HfLaON shows better analog performance as the Rout of HfLaON is greater than HfLaSiON at the same drain current. The DC gain of HfLaON also indicates slightly better analog performance.
1.5
Fig. 7. Comparison of detrapping characteristics. (a) DVT vs. stress time with sequential trapping and detrapping, and (b) DVT vs. stress voltage. HfLaON exhibits larger charge trapping and detrapping (detrapping voltage of 1 V) than HfLaON and both of the reversible and irreversible VT of HfLaON is larger than HfLaSiON (after 1000 s stress followed by 1000s detrapping ( 1 V)).
rect tunneling of electrons as explained in [10]. Because the activation energy provides a measure of the migration of trapped electrons to other traps, similar activation energy of devices shows that the trap energy level of HfLaSiON and HfLaON is similar [11]. Therefore, the different charge trapping and detrapping behaviors may be due to different pre-existing trap densities at the same energy level. 4. Conclusions The device performance and reliability characteristics of MOSFETs with HfLaSiON and HfLaON are compared in depth. MOSFETs
W.-H. Choi et al. / Microelectronic Engineering 86 (2009) 268–271
Acknowledgement
-2.0
Ln ΔVT @ 1000sec (V)
271
HfLaSiON HfLaON
-2.5
This work was supported in part by the Research Program of the National Center for Nanomaterials Technology (NCNT), Korea.
Ea=0.051eV
-3.0
References
-3.5 -4.0 Ea=0.047eV
-4.5
VG =1.8+VT -5.0 28
30
32
34
1/kT eV
36
38
40
-1
Fig. 8. Arrhenius plot of the VT shift under PBT stress.
with HfLaON exhibit better digital and analog performance than those with HfLaSiON while HfLaSiON shows better reliability characteristics or less device degradation by PBT and CHC stresses than HfLaON. Therefore, digital and analog performance as well as reliability characteristics should be considered in developing high-k dielectrics that incorporate La for high performance CMOS technology.
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