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Comparison of lateral and vertical Si-MOSFETs with ultra short channels
Thin Solid Films 336 (1998) 313±318
Comparison of lateral and vertical Si-MOSFETs with ultra short channels D. Behammer a,*, M. Zeuner a, T. Hackbarth a, J. Herzog a, M. Schafer b, T. Grabolla c a
Daimler-Benz Research Center Ulm, P.O. Box 2360, 89013 Ulm, Germany b CADwalk, Stegackerstrasse 7, 89604 Allmendingen, Germany c Institute for Semiconductor Physics, Walter-Korsina-Strasse. 2, D15230 Frankfurt, Oder, Germany
Abstract The fabrication of a vertical MOSFET is compatible with standard CMOS technology for lateral MOSFETs. Process modules like gate oxidation, polysilicon gate contact, oxide spacer, contact implantation, salizidation, isolation and metallization were used for the integration of lateral and vertical hetero- and homo-MOS devices. For the vertical device the epitaxy of the drain±channel±source layer stack and the mesa etching are new processes. For a 100 nm vertical n-MOSFET (N A 1 £ 1018 cm 23) with a 5 nm thick thermal oxide we obtained: gm 375 mS/mm (U DS 2 V), U T 0:3 V, S 80 mV/dec and I Dmin 1 £ 10210 A/mm. For comparison, with a 0.5 pm lateral nMOSFET we achieved: gm 340 mS/mm, U T 0:34 V, S 66 mV/dec and I Dmin 1 £ 10210 A/mm. In addition, the intrinsic RF performance has been simulated to complete the comparison of the lateral and vertical n-MOSFET. It is shown, that the high source± drain capacitance CDS of the vertical MOSFET reduces the transit frequency. q 1998 Elsevier Science S.A. All rights reserved. Keywords: Si-MOSFETs; Ultra short channels
1. Introduction Channel lengths are continually scaled to smaller dimensions to improve performance and package density. Extrapolating the critical device dimensions for silicon ICs to the future, one will achieve MOS transistors with gate lengths of about 70 nm, realizing the 64 GBit DRAM around the year 2010 [1]. In recent years this has led to demonstrations of MOSFETs with effective channel lengths of 0.1 mm and below [2±5]. The key technology challenges at these linewidths include the lithography to achieve reproducibly ®ne dimensions, source and drain engineering to reduce device parasitics and channel engineering to control short-channel effects. Similar to the development of a vertical capacitor for DRAMs at small cell sizes, a vertical transistor technology would raise the package density, could avoid the lithography problem for the gate layer and open new ways for optimizing the doping pro®le using epitaxial layers deposited with atomic layer thickness control and various doping concentrations [6±16]. Integration concepts for vertical MOS transistors are based on simple mesa etched transistor topography and conventional source±drain implantation [6± 10] or source±channel±drain blanket epitaxy and mesa etching for a lateral de®nition of the transistor [11±14]. Standard applications for vertical MOS transistors are DRAMs * Corresponding author. Tel.: 149-731-5052247; Fax: 149-7315054102; e-mail: [email protected].
[6,7,10], the MultiMediaCard [14] or discrete power MOSFETs [15]. For these applications the high package density and/or/ the low Ron recommend the use of the vertical MOS transistor with relatively long channel length; (.0.5 mm). In this paper the lateral and vertical MOS transistor integration technology is compared with respect to the process ¯ow, the measured DC characteristics and the simulated RF performance. 2. Device fabrication and DC characterization The fabrication of the vertical MOSFET is compatible with a standard CMOS technology for lateral MOSFETs. Process modules like gate oxidation, polysilicon gate contact, oxide spacer, contact implantation, salizidation, isolation and metallization were used for the integration of lateral and vertical hetero- and homo-MOS devices. New process steps for the vertical device are the epitaxy of the drain±channel±source layer stack and the mesa etching. A schematic view of the process ¯ows is given in Fig. 1. 2.1. Vertical n-MOS transistor Following the molecular beam epitaxy of the npnn 1 layer stack on 2 mV cm n 1-substrate, the mesa was de®ned by reactive ion etching using a PECVD oxide hard mask. After a standard RCA clean, the gate oxide was formed by dry oxidation at a temperature of 8008C. The nominal gate oxide
0040-6090/98/$ - see front matter q 1998 Elsevier Science S.A. All rights reserved. PII S0 040-6090(98)012 85-1
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D. Behammer et al. / Thin Solid Films 336 (1998) 313±318
Fig. 1. Schematic view of the process ¯ows of the vertical and lateral n-MOSFET.
Fig. 2. TEM cross section of the gate oxide of the fabricated vertical nMOS transistor.
thickness was 3 nm for a standard p 2-substrate. The doping level, the highly doped substrate, the roughness of the sidewalls and the mechanical stress change the thermal oxidation rate, which led to the thickness ¯uctuation of the oxide shown in the cross section TEM of the fully fabricated transistor in Fig. 2. For the planar oxide reference the breakdown ®eld is .10 7 V/cm and the interface state density is ,5 £ 1010 cm 22/eV. On top of the gate oxide a 130 nm thick amorphous silicon layer was deposited at T 5608C from silane in a LPCVD reactor with an 2-spike in situ phosphorous doping. A sheet resistance of ,115 V/(A) was achieved after recrystallization at 9008C N2-RTA for 30 s. The de®nition of the gate contact was realized by etching in an anisotropic SF6/O2 plasma with an etch stop at the gate oxide. At the sidewalls of the mesa a suf®cient thick polysilicon spacer was built, which led to a surrounding gate structure
D. Behammer et al. / Thin Solid Films 336 (1998) 313±318
315
Fig. 3. REM cross section of the polysilicon spacer of the fabricated vertical n-MOS transistor.
(see Fig. 3). After an additional oxide spacer was formed a contact implantation (20 keV, 2 £ 1015 cm 22 P) and Co salizidation (from 10 nm Co) completed the de®nition of the low ohmic contacts. Following the isolation with 400 nm PECVD oxide and the contact hole etching, the 1.1 mm thick WTi/Al(Si1%Cu0.5%) metallization was patterned wet chemically. Finally a 5 min 4508C H2/N2 RTA anneal reduced the process induced damages. 2.2. Lateral n-MOS transistor The fabrication of the lateral n-MOSFET began with the oxidation of 200 nm ®eld oxide on 5 V cm p-substrate. Several boron implantations (e.g. 60 keNi 1 £ 1012 cm 22 B, 40 keV 1 £ 1012 cm 22 B, 10 keV 3 £ 1012 cm 22 B) de®ned the vertical pro®le, ®xed the threshold voltage and reduced the drain-induced-barrier-lowering and the parasitic inversion channel under the ®eld oxide. After a standard RCA clean, a 5 nm thick gate oxide was formed in a dry oxidation at 8008C. The phosphorus contact implantation was done in a self-aligned process after the de®nition of the in situ doped amorphous silicon gate. An oxide spacer masked the Co salizidation after the RTA of the source± drain contact implantation (30 s 9008C N2). The transistor contact was equal to the vertical transistor. The typical drain current/gate voltage (ID±VGS) and drain current/source±drain voltage (ID±VDS) characteristics of the fabricated vertical (l 0:1 mm, N A 1 £ 1018 cm 23 B) and lateral (l 0:5 mm) n-MOSFET are shown in Fig. 4. For the
100 nm vertical n-MOSFET (N A 1 £ 1018 cm 23) with a 5 nm thick thermal oxide (see Fig. 2) we measured gm 375 mS/mn: (U DS 2 V), U T 0:3 V, S 80 mV/dec and I Dmin l £ 10210 A/mm. First order calculations based on a drift diffusion model (ATLAS) resulted in gm 390 mS/ mm (U DS 2 V), U T 0:34 V. S 91 mV/dec and I Dmin 1 £ 1010 A/mm. For the 0.5 pm lateral n-MOSFET with a 5 nm gate oxide the measured (simulated) data are gm 340 mS/mm (270 mS/mm) at U DS 2 V, U m 0:34 V (0.38 V), S 66 mV/dec (85 mV/dec) and I Dmin 1 £ 10212 A/mm. 3. Comparison of vertical and lateral MOSFET The comparison of the package density of vertical and lateral MOSFETs in Fig. 5 is based or the same layout and technology rules. F is the minimum feature size and DF the misalignment 4F 1 10DF is the minimum gate width of the vertical MOS transistor and must be the same for both transistors. At DF 0:2F the package density of the vertical MOS transistor is doubled. On the other hand, the optimization of the DC characteristics of the vertical MOSFET is dif®cult, because it has an one-dimensional doping pro®le given by the growth parameters which may be changed by the process induced out-diffusion. So, only the channel doping can be varied and the sub-threshold slope S becomes the key ®gure. The optimum channel concentration is given in the minimum of S. This ®xes the threshold voltage UT and
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D. Behammer et al. / Thin Solid Films 336 (1998) 313±318
Fig. 4. Input and output characteristics of the fabricated vertical and lateral n-MOSFET.
Fig. 5. Package density of vertical and lateral MOSFETs based on the same layout and technology rules.
Fig. 6. Simulated S, UT and gm of a 100, 50 and 25 nm n-MOSFET versus the gate oxide thickness.
D. Behammer et al. / Thin Solid Films 336 (1998) 313±318
317
Fig. 7. Simulated fT and CSD of a 100 nm vertical and lateral n-MOSFET.
the transconductance gm. For lower doping levels S increases because of the punch through and for higher concentrations because of the reduced gate in¯uence. The simulated optimum channel concentration for a 100, 50 and 25 nm channel is given by a boron concentration of 1 1.5 and 2.5£10 18 cm 23 B. Fig. 6 summarizes the transistor data and makes it clear, that the reduction of the gate oxide improves the DC behaviour of the transistor much more than the down scaling of the gate length. The vertical MOSFET is in the ®rst simpli®cation a two-dimensional device and so suitable for the academic optimization of, e.g. in¯uence of d -doping and hetero barriers. The two-dimensional doping pro®le of the lateral device is de®ned by the boron implantation before the gate oxide deposition and the LDD and contact implantation. During the implantation it is possible to control the boron dose with the implantation current, whereas up to now there is no opportunity to measure in situ the doping concentration during the growth of the vertical MOSFET. The RF performance of the vertical and lateral MOSFET differs mainly because of the high source±drain capacitance CSD. Fig. 7 presents the simulated CSD of unit cells of 100 nm vertical and lateral n-channel MOS transistors. For the lateral device the transit frequency is f T . 75 GHz whereas in the vertical case fT is below 15 GHz. So, the vertical MOSFET is only suitable for RF applications after the removal of the parasitic mesa volume [16]. Only stacked vertical devices can enhance the performance of logic ICs as a consequence of the reduced interconnections.
4. Conclusion The lateral MOS transistor has a high source±drain symmetry, low parasitic resistances, low parasitic capacitances because of the gate contact self-alignment and can be optimized by simple channel engineering. In contrast, the vertical MOS transistor has a low source±drain symmetry, medium parasitic resistances, high parasitic capacitances (CSD, CSG and CDG) and has the disadvantage of a onedimensional doping pro®le. Both devices can be produced in standard low cost technology, but their applications must be selected individually. Acknowledgements This work bene®ted from the collaboration with H. Kibbel, G. Hock, M. Gluck, H. Walk, K. Hoffmann and U. Konig. Parts of this work were supported by ESPRIT project VAHMOS 2000. References [1] The National Technology Road Map for Semiconductors, SIA Semiconductor Industry Association, 1997. [2] Y. Taur, Y.-J. Mii, D.J. Frank, et al., IBM J. Res. Dev. 39(1/2) 245. [3] J. Lyu, B.-G. Park, K. Chun, J.D. Lee, IEDM (1995) 431. [4] M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, H. Iwai, Trans. Electron. Devices 42 (10) (1995) 1822.
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D. Behammer et al. / Thin Solid Films 336 (1998) 313±318
[5] C.H. Wann, R. Tu, B. Yu, et al., A Comparative Study of Advanced MOSFET Structures VLSI Symp. 1996, pp. 32±33. [6] S. Maeda, S. Maegawa, T. Ipposhi, et-al., Trans. Electron. Devices 42 (12) (1995) 2117. [7] H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, F. Masuako, Trans. Electron. Devices 38 (3) (1991) 573. [8] E. Takeda, D. Hisamoto, K. Nakamura, IEICE Trans. E 74 (2) (1991) 360. [9] S. Yamazaki, US Patent 5,403, 763 (1995). [10] J.T. Fitch, C.A. Mazure, K.E. Witek, US Patent 5,414,288 (1995). [11] L. Risch, W.H. Krautschneider, F. Hofmann, H. Schafer, ESSDERC (1995) 101.
[12] H. Gossner, F. Wittmann, W. Hansch, I. Eisele, T. Grabolla, D. Behammer, Electron. Lett. 31 (1995) 1394. [13] D. Behammer, L. Vescan, R. Loo, J. Moers, U. Zastrow, H. Luth, T. Grabolla, Electron. Lett. 32 (4) (1996) 406. [14] see MultiMedeaCard http://siemens.de/innovation. [15] Fairchild Semiconductor, Jedes Watt zahlt, Design und Elektronik, 5/ 1998. [16] T. Aeugle, L. Risch, W. Rosner, Th. Schulz, D. Behammer, ESSDERC (1998) 628.
Comparison of lateral and vertical Si-MOSFETs with ultra short channels D. Behammer a,*, M. Zeuner a, T. Hackbarth a, J. Herzog a, M. Schafer b, T. Grabolla c a
Daimler-Benz Research Center Ulm, P.O. Box 2360, 89013 Ulm, Germany b CADwalk, Stegackerstrasse 7, 89604 Allmendingen, Germany c Institute for Semiconductor Physics, Walter-Korsina-Strasse. 2, D15230 Frankfurt, Oder, Germany
Abstract The fabrication of a vertical MOSFET is compatible with standard CMOS technology for lateral MOSFETs. Process modules like gate oxidation, polysilicon gate contact, oxide spacer, contact implantation, salizidation, isolation and metallization were used for the integration of lateral and vertical hetero- and homo-MOS devices. For the vertical device the epitaxy of the drain±channel±source layer stack and the mesa etching are new processes. For a 100 nm vertical n-MOSFET (N A 1 £ 1018 cm 23) with a 5 nm thick thermal oxide we obtained: gm 375 mS/mm (U DS 2 V), U T 0:3 V, S 80 mV/dec and I Dmin 1 £ 10210 A/mm. For comparison, with a 0.5 pm lateral nMOSFET we achieved: gm 340 mS/mm, U T 0:34 V, S 66 mV/dec and I Dmin 1 £ 10210 A/mm. In addition, the intrinsic RF performance has been simulated to complete the comparison of the lateral and vertical n-MOSFET. It is shown, that the high source± drain capacitance CDS of the vertical MOSFET reduces the transit frequency. q 1998 Elsevier Science S.A. All rights reserved. Keywords: Si-MOSFETs; Ultra short channels
1. Introduction Channel lengths are continually scaled to smaller dimensions to improve performance and package density. Extrapolating the critical device dimensions for silicon ICs to the future, one will achieve MOS transistors with gate lengths of about 70 nm, realizing the 64 GBit DRAM around the year 2010 [1]. In recent years this has led to demonstrations of MOSFETs with effective channel lengths of 0.1 mm and below [2±5]. The key technology challenges at these linewidths include the lithography to achieve reproducibly ®ne dimensions, source and drain engineering to reduce device parasitics and channel engineering to control short-channel effects. Similar to the development of a vertical capacitor for DRAMs at small cell sizes, a vertical transistor technology would raise the package density, could avoid the lithography problem for the gate layer and open new ways for optimizing the doping pro®le using epitaxial layers deposited with atomic layer thickness control and various doping concentrations [6±16]. Integration concepts for vertical MOS transistors are based on simple mesa etched transistor topography and conventional source±drain implantation [6± 10] or source±channel±drain blanket epitaxy and mesa etching for a lateral de®nition of the transistor [11±14]. Standard applications for vertical MOS transistors are DRAMs * Corresponding author. Tel.: 149-731-5052247; Fax: 149-7315054102; e-mail: [email protected].
[6,7,10], the MultiMediaCard [14] or discrete power MOSFETs [15]. For these applications the high package density and/or/ the low Ron recommend the use of the vertical MOS transistor with relatively long channel length; (.0.5 mm). In this paper the lateral and vertical MOS transistor integration technology is compared with respect to the process ¯ow, the measured DC characteristics and the simulated RF performance. 2. Device fabrication and DC characterization The fabrication of the vertical MOSFET is compatible with a standard CMOS technology for lateral MOSFETs. Process modules like gate oxidation, polysilicon gate contact, oxide spacer, contact implantation, salizidation, isolation and metallization were used for the integration of lateral and vertical hetero- and homo-MOS devices. New process steps for the vertical device are the epitaxy of the drain±channel±source layer stack and the mesa etching. A schematic view of the process ¯ows is given in Fig. 1. 2.1. Vertical n-MOS transistor Following the molecular beam epitaxy of the npnn 1 layer stack on 2 mV cm n 1-substrate, the mesa was de®ned by reactive ion etching using a PECVD oxide hard mask. After a standard RCA clean, the gate oxide was formed by dry oxidation at a temperature of 8008C. The nominal gate oxide
0040-6090/98/$ - see front matter q 1998 Elsevier Science S.A. All rights reserved. PII S0 040-6090(98)012 85-1
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D. Behammer et al. / Thin Solid Films 336 (1998) 313±318
Fig. 1. Schematic view of the process ¯ows of the vertical and lateral n-MOSFET.
Fig. 2. TEM cross section of the gate oxide of the fabricated vertical nMOS transistor.
thickness was 3 nm for a standard p 2-substrate. The doping level, the highly doped substrate, the roughness of the sidewalls and the mechanical stress change the thermal oxidation rate, which led to the thickness ¯uctuation of the oxide shown in the cross section TEM of the fully fabricated transistor in Fig. 2. For the planar oxide reference the breakdown ®eld is .10 7 V/cm and the interface state density is ,5 £ 1010 cm 22/eV. On top of the gate oxide a 130 nm thick amorphous silicon layer was deposited at T 5608C from silane in a LPCVD reactor with an 2-spike in situ phosphorous doping. A sheet resistance of ,115 V/(A) was achieved after recrystallization at 9008C N2-RTA for 30 s. The de®nition of the gate contact was realized by etching in an anisotropic SF6/O2 plasma with an etch stop at the gate oxide. At the sidewalls of the mesa a suf®cient thick polysilicon spacer was built, which led to a surrounding gate structure
D. Behammer et al. / Thin Solid Films 336 (1998) 313±318
315
Fig. 3. REM cross section of the polysilicon spacer of the fabricated vertical n-MOS transistor.
(see Fig. 3). After an additional oxide spacer was formed a contact implantation (20 keV, 2 £ 1015 cm 22 P) and Co salizidation (from 10 nm Co) completed the de®nition of the low ohmic contacts. Following the isolation with 400 nm PECVD oxide and the contact hole etching, the 1.1 mm thick WTi/Al(Si1%Cu0.5%) metallization was patterned wet chemically. Finally a 5 min 4508C H2/N2 RTA anneal reduced the process induced damages. 2.2. Lateral n-MOS transistor The fabrication of the lateral n-MOSFET began with the oxidation of 200 nm ®eld oxide on 5 V cm p-substrate. Several boron implantations (e.g. 60 keNi 1 £ 1012 cm 22 B, 40 keV 1 £ 1012 cm 22 B, 10 keV 3 £ 1012 cm 22 B) de®ned the vertical pro®le, ®xed the threshold voltage and reduced the drain-induced-barrier-lowering and the parasitic inversion channel under the ®eld oxide. After a standard RCA clean, a 5 nm thick gate oxide was formed in a dry oxidation at 8008C. The phosphorus contact implantation was done in a self-aligned process after the de®nition of the in situ doped amorphous silicon gate. An oxide spacer masked the Co salizidation after the RTA of the source± drain contact implantation (30 s 9008C N2). The transistor contact was equal to the vertical transistor. The typical drain current/gate voltage (ID±VGS) and drain current/source±drain voltage (ID±VDS) characteristics of the fabricated vertical (l 0:1 mm, N A 1 £ 1018 cm 23 B) and lateral (l 0:5 mm) n-MOSFET are shown in Fig. 4. For the
100 nm vertical n-MOSFET (N A 1 £ 1018 cm 23) with a 5 nm thick thermal oxide (see Fig. 2) we measured gm 375 mS/mn: (U DS 2 V), U T 0:3 V, S 80 mV/dec and I Dmin l £ 10210 A/mm. First order calculations based on a drift diffusion model (ATLAS) resulted in gm 390 mS/ mm (U DS 2 V), U T 0:34 V. S 91 mV/dec and I Dmin 1 £ 1010 A/mm. For the 0.5 pm lateral n-MOSFET with a 5 nm gate oxide the measured (simulated) data are gm 340 mS/mm (270 mS/mm) at U DS 2 V, U m 0:34 V (0.38 V), S 66 mV/dec (85 mV/dec) and I Dmin 1 £ 10212 A/mm. 3. Comparison of vertical and lateral MOSFET The comparison of the package density of vertical and lateral MOSFETs in Fig. 5 is based or the same layout and technology rules. F is the minimum feature size and DF the misalignment 4F 1 10DF is the minimum gate width of the vertical MOS transistor and must be the same for both transistors. At DF 0:2F the package density of the vertical MOS transistor is doubled. On the other hand, the optimization of the DC characteristics of the vertical MOSFET is dif®cult, because it has an one-dimensional doping pro®le given by the growth parameters which may be changed by the process induced out-diffusion. So, only the channel doping can be varied and the sub-threshold slope S becomes the key ®gure. The optimum channel concentration is given in the minimum of S. This ®xes the threshold voltage UT and
316
D. Behammer et al. / Thin Solid Films 336 (1998) 313±318
Fig. 4. Input and output characteristics of the fabricated vertical and lateral n-MOSFET.
Fig. 5. Package density of vertical and lateral MOSFETs based on the same layout and technology rules.
Fig. 6. Simulated S, UT and gm of a 100, 50 and 25 nm n-MOSFET versus the gate oxide thickness.
D. Behammer et al. / Thin Solid Films 336 (1998) 313±318
317
Fig. 7. Simulated fT and CSD of a 100 nm vertical and lateral n-MOSFET.
the transconductance gm. For lower doping levels S increases because of the punch through and for higher concentrations because of the reduced gate in¯uence. The simulated optimum channel concentration for a 100, 50 and 25 nm channel is given by a boron concentration of 1 1.5 and 2.5£10 18 cm 23 B. Fig. 6 summarizes the transistor data and makes it clear, that the reduction of the gate oxide improves the DC behaviour of the transistor much more than the down scaling of the gate length. The vertical MOSFET is in the ®rst simpli®cation a two-dimensional device and so suitable for the academic optimization of, e.g. in¯uence of d -doping and hetero barriers. The two-dimensional doping pro®le of the lateral device is de®ned by the boron implantation before the gate oxide deposition and the LDD and contact implantation. During the implantation it is possible to control the boron dose with the implantation current, whereas up to now there is no opportunity to measure in situ the doping concentration during the growth of the vertical MOSFET. The RF performance of the vertical and lateral MOSFET differs mainly because of the high source±drain capacitance CSD. Fig. 7 presents the simulated CSD of unit cells of 100 nm vertical and lateral n-channel MOS transistors. For the lateral device the transit frequency is f T . 75 GHz whereas in the vertical case fT is below 15 GHz. So, the vertical MOSFET is only suitable for RF applications after the removal of the parasitic mesa volume [16]. Only stacked vertical devices can enhance the performance of logic ICs as a consequence of the reduced interconnections.
4. Conclusion The lateral MOS transistor has a high source±drain symmetry, low parasitic resistances, low parasitic capacitances because of the gate contact self-alignment and can be optimized by simple channel engineering. In contrast, the vertical MOS transistor has a low source±drain symmetry, medium parasitic resistances, high parasitic capacitances (CSD, CSG and CDG) and has the disadvantage of a onedimensional doping pro®le. Both devices can be produced in standard low cost technology, but their applications must be selected individually. Acknowledgements This work bene®ted from the collaboration with H. Kibbel, G. Hock, M. Gluck, H. Walk, K. Hoffmann and U. Konig. Parts of this work were supported by ESPRIT project VAHMOS 2000. References [1] The National Technology Road Map for Semiconductors, SIA Semiconductor Industry Association, 1997. [2] Y. Taur, Y.-J. Mii, D.J. Frank, et al., IBM J. Res. Dev. 39(1/2) 245. [3] J. Lyu, B.-G. Park, K. Chun, J.D. Lee, IEDM (1995) 431. [4] M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, H. Iwai, Trans. Electron. Devices 42 (10) (1995) 1822.
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D. Behammer et al. / Thin Solid Films 336 (1998) 313±318
[5] C.H. Wann, R. Tu, B. Yu, et al., A Comparative Study of Advanced MOSFET Structures VLSI Symp. 1996, pp. 32±33. [6] S. Maeda, S. Maegawa, T. Ipposhi, et-al., Trans. Electron. Devices 42 (12) (1995) 2117. [7] H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, F. Masuako, Trans. Electron. Devices 38 (3) (1991) 573. [8] E. Takeda, D. Hisamoto, K. Nakamura, IEICE Trans. E 74 (2) (1991) 360. [9] S. Yamazaki, US Patent 5,403, 763 (1995). [10] J.T. Fitch, C.A. Mazure, K.E. Witek, US Patent 5,414,288 (1995). [11] L. Risch, W.H. Krautschneider, F. Hofmann, H. Schafer, ESSDERC (1995) 101.
[12] H. Gossner, F. Wittmann, W. Hansch, I. Eisele, T. Grabolla, D. Behammer, Electron. Lett. 31 (1995) 1394. [13] D. Behammer, L. Vescan, R. Loo, J. Moers, U. Zastrow, H. Luth, T. Grabolla, Electron. Lett. 32 (4) (1996) 406. [14] see MultiMedeaCard http://siemens.de/innovation. [15] Fairchild Semiconductor, Jedes Watt zahlt, Design und Elektronik, 5/ 1998. [16] T. Aeugle, L. Risch, W. Rosner, Th. Schulz, D. Behammer, ESSDERC (1998) 628.