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Compound semiconductor MOSFETs
Microelectronic Engineering 84 (2007) 2138–2141 www.elsevier.com/locate/mee
Compound semiconductor MOSFETs R. Droopad*, K. Rajagopalan, J. Abrokwah, P. Zurcher, M. Passlack Freescale Semiconductor, 2100E Elliot Road, Tempe, AZ 85284, USA
Abstract Enhancement mode, high electron mobility MOSFET devices have been fabricated using an oxide high-N gate dielectric stack developed using molecular beam epitaxy. A template layer of Ga2O3, initially deposited on the surface of the III-V device unpins the GaAs Fermi level while a (GdxGa1-x)2O3 bulk ternary layer forms the highly resistive layer to reduce leakage current through the dielectric stack. A midgap interface state density of ~2x1011 cm-2 eV-1 and a dielectric constant of 20 are determined using electrical measurements.Ҡ N-channel MOSFETs with a gate length of 1µm and a source-drain spacing of 3µm show a threshold voltage, saturation current and transconductance of 0.11V, 380mA/mm and 250mS/mm, respectively. Keywords: GaAs gate dielectric; III-V MOSFETs; compound semiconductors
1. Introduction As a result of device scaling, silicon complementary metal oxide semiconductor (CMOS) technology is rapidly reaching fundamental limits leading to increased research into alternative channel materials. Although high mobility III-V compound semiconductors are suitable candidates for implementation in future CMOS-type devices, they have suffered from a lack of a suitable gate dielectric material. Any gate dielectric on compound semiconductor should result in low interface state
Corresponding author. Tel.:+ 1 480 413 7513; fax: +1 480 413 3294. E-mail address:[email protected]
0167-9317/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.04.018
densities and an unpinned Fermi level for enhancement mode operation and be thermodynamically stable with the semiconductor throughout device fabrication. Successful development of such a gate dielectric would also open up a wide range of applications in the wireless and optoelectronic arenas. Initial attempts on developing a gate dielectric on GaAs that utilized a number of oxidation processes similar to the thermal oxidation technique of silicon were not encouraging [1-6]. It wasn’t until an MBE approach was used that a low interface state density Ga2O3/GaAs interface was realized [7-9]. This approach used electron beam evaporation from a high purity single crystal gadolinium garnet (Gd3Ga5O12) and both inversion and accumulation were reported
R. Droopad et al. / Microelectronic Engineering 84 (2007) 2138–2141
in n- and p-type GaAs MOS capacitors which were found to have an oxide/GaAs interfacial region of very low Gd concentration. However, the oxide compositional depth profile was difficult to predict and control because of the deposition technique used. Later, Gd2O3 was intentionally formed on GaAs leading to deteriorated C-V characteristics with large frequency dispersion with increasing Gd film content [10-11]. More recently we have utilized polycrystalline Ga2O3 in an effusion source during MBE to form a high purity amorphous Ga2O3 bulk layer on GaAs (001) [12-13]. However, large leakage currents obtained for Ga2O3 bulk films limit their usefulness as a gate dielectric for transistor applications. In this paper we report on the development of a gate dielectric technology on GaAs based on a (GdxGa1-x)2O3/Ga2O3 dielectric stack. The use of MBE in the deposition of such stack allows for the reproducible control of the oxide/semiconductor and the formation of smooth and low defectivity films leading to an unpinned Fermi level. Enhancement mode MOSFET devices have been fabricated and characterized. 2. Oxide/GaAs Interface Structure To create interfaces in which the semiconductor Fermi level is unpinned, the atomic structure of the GaAs/oxide interface must be reproducibly controlled. Early work by Spicer [14] and Pianetta [15] on the surface reactivity of III-V semiconductors revealed the importance of surface preparation in the development of any gate dielectric on compound semiconductors. Deposition conditions are needed in which an ordered and oxygen free semiconductor surface is maintained prior to the deposition of the oxide layer. The binary Ga2O3 layer is critical in the formation of an unpinned Fermi level for GaAs. STM has been utilized to study the initial stages of deposition and determine the absorption sites which can potentially provide for an unpinned Fermi level [16]. Figure 1 shows a filled state STM image taken on a cleaned (2x4) reconstructed GaAs surface that was dosed with Ga2O and O2 molecules produced from the sublimation of a polycrystalline Ga2O3 source. From the image, it can be seen that a Ga2O molecule is inserted into a pair of arsenic dimers on top of the
original arsenic dimer row. The ball and stick model also shown in figure 1 shows the atomic positions of molecules. Scanning tunneling the Ga2O spectroscopy measurements have determined that the density of states and the Fermi level position for both n- and p-GaAs are indicative of unpinned surfaces.
Fig. 1. Filled state STM image of a clean GaAs (2x4) reconstructed surface which has been dosed with Ga2O and O2 molecules. The brightest features in the image are the Ga2O molecules [16].
3. Experimental Growth is carried out in a multi-chamber MBE system having dedicated chambers for III-V and oxide deposition. The oxide chamber is configured for multiple e-beams, effusion cells as well as an oxygen plasma source. Both chambers are equipped with reflection high energy electron diffraction (RHEED) systems for in-situ calibration of GaAs growth parameters and monitoring the evolution of the interface as the oxide transitions from an ordered surface to an amorphous bulk film. The oxide-based gate dielectric under development consists of a thin template layer of Ga2O3 followed by a thick layer of (GdxGa1-x)2O3. Ga2O3 deposition is carried out using Ga2O and O2 molecules, resulting from the decomposition of a polycrystalline Ga2O3 source and is initiated on a (2x4) reconstructed GaAs surface, in the temperature range of 400-450°C. The ternary (GdxGa1-x)2O3 layer is formed by utilizing a Gd elemental source, the Ga2O3 source as well as molecular oxygen. 4. Oxide Properties An initial evaluation of the oxide/semiconductor interface is carried out using the photoluminescence intensity technique to determine the electrical quality of the interface between the grown films and GaAs.
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In this technique, PL spectra are acquired as a function of laser intensity as shown in figure 2. The analysis domain (lines with circles) is defined by a known best interface with very low defectivity (AlGaAs on GaAs) and the lower boundary by a known worst interface (native oxide on GaAs). The four data curves close to the native oxide represent a large group of materials forming a high defectivity interface on GaAs. This group comprises more than 10 materials investigated over the years including oxides (e.g. Al2O3, Gd2O3, SiO2), SiN, and Si. The only material departing from “native oxide” behavior is Ga2O3 (bulk Ga2O3, triangles) which shows an interface defectivity adequate for MOSFET operation. The high quality Ga2O3/GaAs interface is preserved if the top oxide does not disrupt the template layer, as observed for the case of optimized deposition of (GdxGa1-x)2O3 (squares). The interface quality of both bulk Ga2O3 and the dielectric stack can further be improved with appropriate hydrogen passivation. Further details can be found in Ref. [17]. The interface state density of the (GdxGa1x)2O3/Ga2O3 dielectric stack on GaAs has been determined as a function of GaAs bandgap energy by capacitance-voltage measurements. Figure 3 shows typical quasi-static and high-frequency (1 MHz) C-V
Fig. 2. Normalized GaAs photoluminescence intensity as a function of excitation intensity for AlGaAs (solid circles), Ga2O3 (open triangles), (GdxGa1-x)2O3/Ga2O3 (solid squares), high interface defectivity films, and native oxide (solid circles) on GaAs.
curves of the dielectric stack deposited on a MOSFET like structure. The midgap interface state density for the (GdxGa1-x)2O3/Ga2O3 dielectric stack with a dielectric constant N = 20 was determined to be ~2.5x1011 cm-2eV-1.
Fig. 3. Quasi-static and high-frequency (1 MHz) C-V curves of a (GdxGa1-x)2O3/Ga2O3 dielectric stack on a GaAs based MOSFET structure.
4. MOSFET Device Properties PHEMT-based MOSFETs have been grown with the (GdxGa1-x)2O3/Ga2O3 dielectric stack. Room temperature mobilities in excess of 6000 cm2V-1s-1 with carrier concentrations of 2-3x1012 cm-2 have been measured for a 100Å In0.3Ga0.7As channel. The inset in figure 4 is a high-resolution TEM image of the oxide semiconductor interface in which the Ga2O3 template is clearly visible. MOSFET devices have been fabricated by first forming ohmic contacts using ion milling to remove the oxide layer and depositing Ni/Ge/Au. Pt/Au gate contacts were then deposited by electron beam evaporation and patterned using conventional lift off techniques. Figure 5 shows GaAs enhancement mode n-channel MOSFET Id-Vd curves for a 1µm gate length device. The maximum drain current IDss of 380 mA/mm and gm of 250 mS/mm were determined. This represents the first enhancement mode GaAs n-channel MOSFET with high channel mobility and an unpinned Fermi level at the oxide/GaAs interface. The transconductance value represents a >60X improvement over previously reported GaAs MOSFET devices.
R. Droopad et al. / Microelectronic Engineering 84 (2007) 2138–2141
Acknowledgements The authors would like to thank N. England, D. Uebelhoer, and L. Adams for wafer growth and processing, Freescale’s Physical Analysis Laboratories, Motorola’s Physical Technologies Laboratory within the Embedded Systems Research Center of Excellence, and K. Johnson and M. Miller for their support. References
Fig. 4. Dark field TEM micrograph of a MOSFET structure with an InGaAs channel. The inset shows a high resolution image of the oxide/semiconductor interface.
Fig. 5. Measured GaAs enhancement mode n-channel MOSFET ID-VD characteristics.
5. Conclusions A novel oxide high-N gate dielectric stack on GaAs which unpins the Fermi level has been developed using molecular beam epitaxy. A template layer of Ga2O3 is initially deposited on the GaAs surface followed by a ternary (GdxGa1-x)2O3 layer. Electrical measurements have been used to determine that the midgap interface state density is around 2.5x1011 cm-2eV-1. GaAs MOSFET devices have been fabricated using this gate dielectric stack on a PHEMT-type structure with saturation current of 380 mA/mm and transconductance of 250 mS/mm.
[1] W. F. Croydon, E. H. C. Parker in Dielectric films on Gallium Arsenide, Gordon and Breach Scientific Publishers, 1981. [2] C.W. Wilmsen, Physics and Chemistry of III-V Compound Semiconductor Interfaces, Plenum Press, 1985. [3] H. Becke, R. Hall, J. White, Solid State Electron. 8 (1965) 813-823. [4] T. Ito, Y. Sakai, Solid State Electron. 17 (1974) 751759. [5] K. Kamimura, Y. Sakai, Thin Solid Films 56 (1979) 215-223. [6] T. Mimura, K. Odani, N. Yokoyama, M. Fukuta, Electron Lett. 12 (1978) 500-502. [7] M. Passlack, M. Hong, J. P. Mannaerts, Appl. Phys. Letts. 68 (1996) 1099-1101. [8] M. Passlack, M. Hong, J. P. Mannaerts, S. Chu, R. Opila, N. Moriya, IEDM Tech. Dig. (1995) 383-386. [9] M. Passlack, M. Hong, J. P. Mannaerts, R. Opila, S. Chu, N. Moriya, F. Ren, J. Kwo, IEEE Trans. Electron. Dev. ED-44 (1997) 214-215. [10] J. Kwo, D. W. Murphy, M. Hong, R. L. Opila, J. P. Mannaerts, A. M. Sergent, R. L. Masaitis, Appl. Phys. Lett. 75 (1999) 1116-1118. [11] J. Kwo, M. Hong, A.R. Kortan, D.W. Murphy, J.P. Mannaerts, A.M. Sergent, Y.C. Wang, and K.C. Hsieh, Mat. Res. Soc. Symp. Proc. 573 (1999) 57. [12] M. Passlack, J. Abrokwah, Z. Yu, R. Droopad, C. Overgaard, Appl. Phys. Lett. 82 (2003) 1691-1693. [13] M. Passlack, Z. Yu, R. Droopad, J. Abrokwah, D. Braddock, S. Yi, M. Hale, J. Sexton, A. Kummel, in: W. Cai, ed., III-V Semiconductor Heterostructures: Physics and Devices, (2003) 327-355. [14] W. E. Spicer, I. Lindau, P. Skeath, C. Y. Su, P. Chye, J. Vac. Sci. Technol. 17 (1980) 1019-1027. [15] P. Pianetta, I. Lindau, C. M. Garner, W. E. Spicer, Surf. Sci. 88 (1979) 439-460. [16] M. J. Hale, S. I. Yi, J. Z. Sexton, A. C. Kummel, M. Passlack, J. Chem.Phys. 119 (2003) 6719-6728. [17] M. Passlack, in Materials Fundamentals of Gate Dielectrics, edited by A.A. Demkov and A. Navrotsky, Springer, New York (2005) 403.
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Compound semiconductor MOSFETs R. Droopad*, K. Rajagopalan, J. Abrokwah, P. Zurcher, M. Passlack Freescale Semiconductor, 2100E Elliot Road, Tempe, AZ 85284, USA
Abstract Enhancement mode, high electron mobility MOSFET devices have been fabricated using an oxide high-N gate dielectric stack developed using molecular beam epitaxy. A template layer of Ga2O3, initially deposited on the surface of the III-V device unpins the GaAs Fermi level while a (GdxGa1-x)2O3 bulk ternary layer forms the highly resistive layer to reduce leakage current through the dielectric stack. A midgap interface state density of ~2x1011 cm-2 eV-1 and a dielectric constant of 20 are determined using electrical measurements.Ҡ N-channel MOSFETs with a gate length of 1µm and a source-drain spacing of 3µm show a threshold voltage, saturation current and transconductance of 0.11V, 380mA/mm and 250mS/mm, respectively. Keywords: GaAs gate dielectric; III-V MOSFETs; compound semiconductors
1. Introduction As a result of device scaling, silicon complementary metal oxide semiconductor (CMOS) technology is rapidly reaching fundamental limits leading to increased research into alternative channel materials. Although high mobility III-V compound semiconductors are suitable candidates for implementation in future CMOS-type devices, they have suffered from a lack of a suitable gate dielectric material. Any gate dielectric on compound semiconductor should result in low interface state
Corresponding author. Tel.:+ 1 480 413 7513; fax: +1 480 413 3294. E-mail address:[email protected]
0167-9317/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.04.018
densities and an unpinned Fermi level for enhancement mode operation and be thermodynamically stable with the semiconductor throughout device fabrication. Successful development of such a gate dielectric would also open up a wide range of applications in the wireless and optoelectronic arenas. Initial attempts on developing a gate dielectric on GaAs that utilized a number of oxidation processes similar to the thermal oxidation technique of silicon were not encouraging [1-6]. It wasn’t until an MBE approach was used that a low interface state density Ga2O3/GaAs interface was realized [7-9]. This approach used electron beam evaporation from a high purity single crystal gadolinium garnet (Gd3Ga5O12) and both inversion and accumulation were reported
R. Droopad et al. / Microelectronic Engineering 84 (2007) 2138–2141
in n- and p-type GaAs MOS capacitors which were found to have an oxide/GaAs interfacial region of very low Gd concentration. However, the oxide compositional depth profile was difficult to predict and control because of the deposition technique used. Later, Gd2O3 was intentionally formed on GaAs leading to deteriorated C-V characteristics with large frequency dispersion with increasing Gd film content [10-11]. More recently we have utilized polycrystalline Ga2O3 in an effusion source during MBE to form a high purity amorphous Ga2O3 bulk layer on GaAs (001) [12-13]. However, large leakage currents obtained for Ga2O3 bulk films limit their usefulness as a gate dielectric for transistor applications. In this paper we report on the development of a gate dielectric technology on GaAs based on a (GdxGa1-x)2O3/Ga2O3 dielectric stack. The use of MBE in the deposition of such stack allows for the reproducible control of the oxide/semiconductor and the formation of smooth and low defectivity films leading to an unpinned Fermi level. Enhancement mode MOSFET devices have been fabricated and characterized. 2. Oxide/GaAs Interface Structure To create interfaces in which the semiconductor Fermi level is unpinned, the atomic structure of the GaAs/oxide interface must be reproducibly controlled. Early work by Spicer [14] and Pianetta [15] on the surface reactivity of III-V semiconductors revealed the importance of surface preparation in the development of any gate dielectric on compound semiconductors. Deposition conditions are needed in which an ordered and oxygen free semiconductor surface is maintained prior to the deposition of the oxide layer. The binary Ga2O3 layer is critical in the formation of an unpinned Fermi level for GaAs. STM has been utilized to study the initial stages of deposition and determine the absorption sites which can potentially provide for an unpinned Fermi level [16]. Figure 1 shows a filled state STM image taken on a cleaned (2x4) reconstructed GaAs surface that was dosed with Ga2O and O2 molecules produced from the sublimation of a polycrystalline Ga2O3 source. From the image, it can be seen that a Ga2O molecule is inserted into a pair of arsenic dimers on top of the
original arsenic dimer row. The ball and stick model also shown in figure 1 shows the atomic positions of molecules. Scanning tunneling the Ga2O spectroscopy measurements have determined that the density of states and the Fermi level position for both n- and p-GaAs are indicative of unpinned surfaces.
Fig. 1. Filled state STM image of a clean GaAs (2x4) reconstructed surface which has been dosed with Ga2O and O2 molecules. The brightest features in the image are the Ga2O molecules [16].
3. Experimental Growth is carried out in a multi-chamber MBE system having dedicated chambers for III-V and oxide deposition. The oxide chamber is configured for multiple e-beams, effusion cells as well as an oxygen plasma source. Both chambers are equipped with reflection high energy electron diffraction (RHEED) systems for in-situ calibration of GaAs growth parameters and monitoring the evolution of the interface as the oxide transitions from an ordered surface to an amorphous bulk film. The oxide-based gate dielectric under development consists of a thin template layer of Ga2O3 followed by a thick layer of (GdxGa1-x)2O3. Ga2O3 deposition is carried out using Ga2O and O2 molecules, resulting from the decomposition of a polycrystalline Ga2O3 source and is initiated on a (2x4) reconstructed GaAs surface, in the temperature range of 400-450°C. The ternary (GdxGa1-x)2O3 layer is formed by utilizing a Gd elemental source, the Ga2O3 source as well as molecular oxygen. 4. Oxide Properties An initial evaluation of the oxide/semiconductor interface is carried out using the photoluminescence intensity technique to determine the electrical quality of the interface between the grown films and GaAs.
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In this technique, PL spectra are acquired as a function of laser intensity as shown in figure 2. The analysis domain (lines with circles) is defined by a known best interface with very low defectivity (AlGaAs on GaAs) and the lower boundary by a known worst interface (native oxide on GaAs). The four data curves close to the native oxide represent a large group of materials forming a high defectivity interface on GaAs. This group comprises more than 10 materials investigated over the years including oxides (e.g. Al2O3, Gd2O3, SiO2), SiN, and Si. The only material departing from “native oxide” behavior is Ga2O3 (bulk Ga2O3, triangles) which shows an interface defectivity adequate for MOSFET operation. The high quality Ga2O3/GaAs interface is preserved if the top oxide does not disrupt the template layer, as observed for the case of optimized deposition of (GdxGa1-x)2O3 (squares). The interface quality of both bulk Ga2O3 and the dielectric stack can further be improved with appropriate hydrogen passivation. Further details can be found in Ref. [17]. The interface state density of the (GdxGa1x)2O3/Ga2O3 dielectric stack on GaAs has been determined as a function of GaAs bandgap energy by capacitance-voltage measurements. Figure 3 shows typical quasi-static and high-frequency (1 MHz) C-V
Fig. 2. Normalized GaAs photoluminescence intensity as a function of excitation intensity for AlGaAs (solid circles), Ga2O3 (open triangles), (GdxGa1-x)2O3/Ga2O3 (solid squares), high interface defectivity films, and native oxide (solid circles) on GaAs.
curves of the dielectric stack deposited on a MOSFET like structure. The midgap interface state density for the (GdxGa1-x)2O3/Ga2O3 dielectric stack with a dielectric constant N = 20 was determined to be ~2.5x1011 cm-2eV-1.
Fig. 3. Quasi-static and high-frequency (1 MHz) C-V curves of a (GdxGa1-x)2O3/Ga2O3 dielectric stack on a GaAs based MOSFET structure.
4. MOSFET Device Properties PHEMT-based MOSFETs have been grown with the (GdxGa1-x)2O3/Ga2O3 dielectric stack. Room temperature mobilities in excess of 6000 cm2V-1s-1 with carrier concentrations of 2-3x1012 cm-2 have been measured for a 100Å In0.3Ga0.7As channel. The inset in figure 4 is a high-resolution TEM image of the oxide semiconductor interface in which the Ga2O3 template is clearly visible. MOSFET devices have been fabricated by first forming ohmic contacts using ion milling to remove the oxide layer and depositing Ni/Ge/Au. Pt/Au gate contacts were then deposited by electron beam evaporation and patterned using conventional lift off techniques. Figure 5 shows GaAs enhancement mode n-channel MOSFET Id-Vd curves for a 1µm gate length device. The maximum drain current IDss of 380 mA/mm and gm of 250 mS/mm were determined. This represents the first enhancement mode GaAs n-channel MOSFET with high channel mobility and an unpinned Fermi level at the oxide/GaAs interface. The transconductance value represents a >60X improvement over previously reported GaAs MOSFET devices.
R. Droopad et al. / Microelectronic Engineering 84 (2007) 2138–2141
Acknowledgements The authors would like to thank N. England, D. Uebelhoer, and L. Adams for wafer growth and processing, Freescale’s Physical Analysis Laboratories, Motorola’s Physical Technologies Laboratory within the Embedded Systems Research Center of Excellence, and K. Johnson and M. Miller for their support. References
Fig. 4. Dark field TEM micrograph of a MOSFET structure with an InGaAs channel. The inset shows a high resolution image of the oxide/semiconductor interface.
Fig. 5. Measured GaAs enhancement mode n-channel MOSFET ID-VD characteristics.
5. Conclusions A novel oxide high-N gate dielectric stack on GaAs which unpins the Fermi level has been developed using molecular beam epitaxy. A template layer of Ga2O3 is initially deposited on the GaAs surface followed by a ternary (GdxGa1-x)2O3 layer. Electrical measurements have been used to determine that the midgap interface state density is around 2.5x1011 cm-2eV-1. GaAs MOSFET devices have been fabricated using this gate dielectric stack on a PHEMT-type structure with saturation current of 380 mA/mm and transconductance of 250 mS/mm.
[1] W. F. Croydon, E. H. C. Parker in Dielectric films on Gallium Arsenide, Gordon and Breach Scientific Publishers, 1981. [2] C.W. Wilmsen, Physics and Chemistry of III-V Compound Semiconductor Interfaces, Plenum Press, 1985. [3] H. Becke, R. Hall, J. White, Solid State Electron. 8 (1965) 813-823. [4] T. Ito, Y. Sakai, Solid State Electron. 17 (1974) 751759. [5] K. Kamimura, Y. Sakai, Thin Solid Films 56 (1979) 215-223. [6] T. Mimura, K. Odani, N. Yokoyama, M. Fukuta, Electron Lett. 12 (1978) 500-502. [7] M. Passlack, M. Hong, J. P. Mannaerts, Appl. Phys. Letts. 68 (1996) 1099-1101. [8] M. Passlack, M. Hong, J. P. Mannaerts, S. Chu, R. Opila, N. Moriya, IEDM Tech. Dig. (1995) 383-386. [9] M. Passlack, M. Hong, J. P. Mannaerts, R. Opila, S. Chu, N. Moriya, F. Ren, J. Kwo, IEEE Trans. Electron. Dev. ED-44 (1997) 214-215. [10] J. Kwo, D. W. Murphy, M. Hong, R. L. Opila, J. P. Mannaerts, A. M. Sergent, R. L. Masaitis, Appl. Phys. Lett. 75 (1999) 1116-1118. [11] J. Kwo, M. Hong, A.R. Kortan, D.W. Murphy, J.P. Mannaerts, A.M. Sergent, Y.C. Wang, and K.C. Hsieh, Mat. Res. Soc. Symp. Proc. 573 (1999) 57. [12] M. Passlack, J. Abrokwah, Z. Yu, R. Droopad, C. Overgaard, Appl. Phys. Lett. 82 (2003) 1691-1693. [13] M. Passlack, Z. Yu, R. Droopad, J. Abrokwah, D. Braddock, S. Yi, M. Hale, J. Sexton, A. Kummel, in: W. Cai, ed., III-V Semiconductor Heterostructures: Physics and Devices, (2003) 327-355. [14] W. E. Spicer, I. Lindau, P. Skeath, C. Y. Su, P. Chye, J. Vac. Sci. Technol. 17 (1980) 1019-1027. [15] P. Pianetta, I. Lindau, C. M. Garner, W. E. Spicer, Surf. Sci. 88 (1979) 439-460. [16] M. J. Hale, S. I. Yi, J. Z. Sexton, A. C. Kummel, M. Passlack, J. Chem.Phys. 119 (2003) 6719-6728. [17] M. Passlack, in Materials Fundamentals of Gate Dielectrics, edited by A.A. Demkov and A. Navrotsky, Springer, New York (2005) 403.
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