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Comprehensive gate-oxide reliability evaluation for dram processes
Microelectron. Reliab., Vol. 36, No. 11/12, pp. 1631-1638, 1996 Copyright © 1996 Elsevier Science Ltd Printed in Great Britain. All rights reserved 0026-2714/96 $15.00 + .00
Pergamon
PIh S0026-2714(96)00162-X
COMPREHENSIVE GATE-OXIDE RELIABILITY EVALUATION FOR DRAM PROCESSES R.-P. VOLLERTSEN 1 and W. W. ABADEER 2 tSIEMENS Comp., Inc., c/o IBM MD 967A, 1000 River Street, Essex Junction, VT 05452, USA 2IBM Microelectronics Division, 1000 River Street, Essex Junction, VT 05452, USA Abstract: This paper discusses dielectric breakdown as a major cause for failure oflCs with less than a half-micron linewidth. Focusing on DRAMs the characterization of dielectric reliability using different types of properly designed test structures and appropriate stress methods is reviewed. Considerations concerning screens and upper limits for stress conditions are presented. With a step stress, the sample size can be reduced and efficiently used to cover the specified lifetime. To understand and identify relevant failure mechanisms, physical failure analysis of representative fails is required. Copyright © 1996 Elsevier Science Ltd INTRODUCTION Thin gate oxides produced by modern MOS technologies are used in a variety of different applications including DRAMs, SRAMs, logic circuits, EEPROMs and power MOSFETs. The demand for higher speed, less power consumption and higher integration density results in downscaling of circuit dimensions, oxide thickness and operation voltage. Due to the nonproportional scaling of oxide thickness and applied voltage, the field over the gate oxide increases [ 1, 2]. At the same time, the oxide becomes more sensitive to defects introduced by process variations and contaminants. Thus, the reliability margins shrink and more accurate evaluation methods are required to balance the cost for process improvement versus reliability margin. Cost and fast feedback are also drivers for fast inline-wafer-level tests [3, 4]. This paper describes methods and considerations for product-relevant, gate-oxide-reliability evaluation during development. Focusing on DRAMs, issues such as failure distribution, modeling, measurement requirements and limitations will be covered as well as the need for failure analysis subsequent to electrical testing. The presented considerations are based on oxide thicknesses ranging from about 9 nm to 22 nm and will also be applicable to products with thinner oxide thickness. STRESS AND EVALUATION PHILOSOPHY The common stress method for reliability analysis of gate oxides operated under constant voltage in the product is an accelerated constant voltage stress. The same mechanism is assumed to dominate degradation during operation and stress. The physical reason for selecting a constant voltage stress is because of charge trapping during stress, which results in decreasing current (negative feedback), thereby slowing down the degradation process and increasing the time to breakdown (tbd). This does not occur, however, for constant current stresses, where the amount of damage-causing carders is kept constant by adjusting the external voltage. Another reason for selecting a constant voltage stress is the availability of models which relate the results from accelerated conditions to operating conditions [5-8], thereby allowing an estimate of the feasibility of an oxide in the product. The times to breakdown resulting from a constant voltage stress are plotted in a Weibull net, which for various
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reasons is best suited for oxide breakdown [9-14]. For large gate-oxide areas and/or large enough sample sizes, bimodal distributions are observed (Fig. 1). The steep part of the distribution (slope>l) is called, by definition, intrinsic distribution or wearout. This nomenclature may sometimes be confusing because physically intrinsic fails are supposed to exhibit identical distributions independent of the area. For gate oxide, however, mostly area scaling of intrinsic distributions is observed. Area-independent intrinsic distributions have been reported [ 15], however, further analysis in this case revealed that all fails were located at the LOCOS edge as the weakest spot of the structure, which limited the lifetime independent of the area. This suggests that for gate oxide, intrinsic distributions mostly represent structural- and/or technology-induced properties rather than pure material properties. The part before the intrinsic distribution (Fig. 1) is caused by defects and called extrinsic distribution. While these fails are also technology induced, they are more severe than the intrinsic fails. The level of the extrinsic part depends strongly on area. Analytical formulas are available to describe the complete bimodal distribution as a combined [16, 17] or competing distribution [12, 17]. However, it was shown that modeling bimodal distributions as competing distributions is more plausible [16, 17] for gate oxide. For products, the extrinsic distribution is usually the relevant part, whereas the intrinsic portion is well beyond lifetime. The latter, of course, must be verified and cannot be taken for granted.
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Figure 1 Bimodal time-to-breakdown distribution in the Weibull net For efficiency, parallel stressing of many parts is usually preferred over serial stressing. This is an advantage of module stresses. On the wafer level, equal structures on different chips are usually so far apart that proper contact and the maintenance of contact is at least difficult. However, different test structures on the same chip can be stressed simultaneously. A different approach to saving time is possible if extrinsic distributions are of interest only. In this case a voltage step stress can be performed. This is a sequence of three to five subsequent constant voltage stresses at different voltages [ 18]. This type of stress uses the same samples throughout the stress, which is the most efficient use of the sample and, at the same time, minimizes the effects of sample inhomogeneities. It also reduces extrapolation uncertainties because the first step can be close to or at use condition. The time saving results from limiting the stress duration of each step. Excellent agreement between step stress and constant-voltage stress results has been demonstrated [19]. E F F E C T O F T E S T DESIGN AND EVALUATION A S S U M P T I O N S The effect of workfunction and polysilicon depletion on the effective oxide field is well known [20, 21 ] and can be estimated using equations of basic physics [ 14]. Series resistance causes an increasing voltage drop with increasing stress voltages and must be taken into account when stressing at highly accelerated voltage or current conditions [22, 23]. Series resistance can be minimized by the proper design of test structure and stress setup. However, in some constant-voltage stress setups, the current is measured across a resistor in the stress circuitry. This is particularly the case when multiple capacitors are stressed in parallel, because voltages can be measured faster than currents and, at the same time, current is limited after a breakdown event.
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For intrinsic distributions, a short screen test at a low voltage prior to stressing successfully eliminates unwanted defective capacitors. The same screening procedure applied when extrinsic distributions are to be stressed may significantly alter the parameters that should be determined [ 18]. A screen has more impact the closer it's voltage is to the stress voltage, because it is not selective, i.e., it does not just remove the unwanted early failure population (different failure mechanism) but also capacitors which belong to the main distribution. According to the effective thickness model [24], the extrinsic distribution consists of capacitors with a wide range of effective thicknesses, which approach zero at very short times (much shorter than the response time of the measurement equipmen0. For capacitors with these weak spots, a low voltage like the screen voltage means a high local field, which causes rapid breakdown. The purpose of the screen is to eliminate a population that represents a different failure mechanism (e.g., real shorts), because they flatten the extrinsic distribution (Fig. 2). A dilemma exists in that the lack of screening eventually results in distributions which are too flat and that inappropriate screening results in distributions that are too steep (Fig. 2). Therefore, Ref. 17 proposes that fields as lbw as 1 MV/cm be used for screening. Even with use of a correct screen prior to the step stress, deviations of step-stress results from constant-voltage-stress results can occur if the difference between subsequent voltages are too small. This is caused by the prestress of the previous step [18]. If prestress is minimized compared to the stress level at the beginning of the accessible time window, tbd distributions will result in straight lines as distributions from constant-voltage stress (Fig. 3). This is achieved by increasing the voltage difference between the steps, with the difference in necessary voltage depending on the acceleration. Improvement of tbd, as in the case of a voltage ramp before a constant voltage stress [25], is not observed for the voltage step stress. 2 1
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TEST S T R U C T U R E TOPOLOGY AND AREA For the investigation of basic gate-oxide breakdown physics, simple planar capacitors are employed which are specially designed to avoid influence from the perimeter. In addition to those structures in early product development, test structures are designed to reflect all possible perimeter- and edgeeffects that are expected on the product. Some of those structures accompany the entire development, e.g., polysilicon gate edges and crossings with thick-oxide isolation, the edge of the thick oxide (LOCOS or STI edges) or trench edges. Both LOCOS edges and shallow-trench isolations (STI) tend to exhibit oxide thinnings (Fig. 4). In addition to the thinning, the STI edge can be very sharp, leading to enhanced electric fields across the oxide. A set of test structures with an identical gate-oxide area but different critical-edge lengths helps to distinguish between gate-oxide area- and perimeter-related fails. Both the topology and area should be somewhat representative for the product, especially if defects need to be investigated. To contain uncertainties in the area extrapolation, the ratio of stressed and projected area should not be more than a factor of 10 [26]. Therefore, test structures will require a
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great deal of space, which for the most part is not available. A solution to the problem is use of a special reliability-test structure in the product area with topology and critical edges of the product. A schematic floor plan of such a structure is shown in Fig. 5 for a 64Mbit chip. The chip's metal-level wiring is changed so that 2Mbit and 4Mbit blocks are generated and all transfer transistor gates are connected in parallel within each block. The layout of the metal lines account for series resistance effects and minimizes them. Almost no metal remains over the array and special marks are implemented to ease failure localization by an optical beam-induced current technique (OBIC [27]). The 2Mbit and 4Mbit blocks are wired to standard 1 x 25 pad sets, with two pad sets placed in parallel to allow efficient parallel testing of 32Mbits in one pass. Because everything below the metal levels is real product, the test structure will perfectly represent the product. Also, the area of the individual blocks is smaller than the product, thereby allowing a higher yield in early development and lower currents than on a large area during high-field stress. The results from the smaller areas can be combined after stress on a by-chip basis, generating tbd distributions for various areas [26]. With this special test structure, all isolation layers are stressed at the same time and fails are not necessarily caused by gate oxide. Therefore, failure analysis is required to determine the dominant failure mechanisms. Antenna structures to monitor inline charging are also important test structures. These consist of a large polysilicon plate over thick-oxide isolation and a small area of thin oxide. By varying the ratio of the thin-oxide and the thick-oxide areas, structures with different sensitivities are defined. Typical ratios are 1:1000 to 1:100000. 4 Mbit •
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Figure 4 TEM cross section of a MOSFET bordered by shallow-trench isolation (STI)
Figure 5 Schematic floor plan of a 64 Mbit chip specially prepared for gate-oxide stress
ACCELERATION MODELING For the prediction of oxide reliability at operating conditions, two different field acceleration models are widely used. One model describes the time as exponentially dependent on the electric field (E model), whereas in the other model the time depends exponentially on the inverse field (1/E model). Empirical and physical justifications have been published for both models [6-8, 13, 28-31]. An extension of the I/E model, which relates the model to time-to-breakdown distributions considering defects as locally reduced effective-oxide thickness (AXox model), was developed [24] and generalized for both field acceleration models [ 14, 32]. Experimental efforts to identify the correct model showed, for intrinsic distributions, that both models fit the data over a wide field range [29, 30, 33] and, in consequence, data need to be taken especially at low electric fields close to or at operating voltage. For extrinsic distributions no differentiation between the models was possible, despite having data that covered a wide field range including operating conditions [34]. Measurements were performed at very high temperatures well beyond operation or bum-in conditions to reduce stress time at low fields [30, 33, 35]. Resulting data fit to a straight line in the log(tbd) vs. E plot and deviated from a straight line in the 1/E plot. However, at high temperatures a change of the degradation mechanism, as discussed in the next section (Fig. 6), already occurs at a medium field, so part of the data have been taken above that transition. The approach used to identify the correct acceleration model, i.e., fitting the data from a wide range of fields to a straight line is doubtful because once a model is declared to be the correct one, data will be taken mostly at high fields. Therefore, a more
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rigorous approach is to use the high-field data only to determine the model parameters and then verify that the behavior at low fields is correctly predicted. In many cases (e.g., also in Ref. 35), this will reveal the transition which is clearly seen in the 1/E plot (Fig. 6), even in the E plot. Thus, the available data does not prove the validity of either model, but rather indicates that the E plot is more forgiving with respect to the degradation physics. Projections from high-field data represent the worst case for the E model and the best case for the 1/E model. For bimodal distributions, the E model has been proposed for the intrinsic and the 1/E model for the extrinsic part of the distribution [35], which suggests that the failure mechanism can also affect acceleration behavior. An alternative statistical approach was proposed [36], which accounted for the slope of the breakdown distributions. The tbd distributions are expected to be parallel and, for the same field difference, equidistant, according to the E model, but showing increasing time differences and decreasing slope with decreasing fields for the 1/E model. The statistical model [36] suggested that the intrinsic and extrinsic part of a bimodal distribution can both independently be modeled using basically the AXox model, but with an additional term for adjusting the acceleration of each failure percentage, which is equivalent to the defect density if the area is kept constant. The additional term considers the slope of the distributions in a way that the data suggest it rather than the AXox model forces it, i.e., the tbd distributions from different voltages can as well be parallel, as expected from the E model. Separate sets of model parameters are required for both the extrinsic and intrinsic distribution [36]. A similar model applied to entire bimodal distributions was proposed recently [ 17]. The different data reported suggest that there is a variety of oxide-field acceleration behaviors, probably technology-related, rather than one universal behavior for all oxides. The pragmatic approach of not forcing certain model parameters to the data, but yet obtaining the complete set of parameters for statistical modeling from the data [37] is a more general alternative. These parameters are determined simultaneously from all data by multiple linear regression [37] or the maximum likelihood method [ 17]. An example of this method is shown in Fig. 3 for step-stress data. The dashed lines represent the projections from multiple linear regression. Even down to operating conditions, the projection shows excellent agreement. This leads to high confidence in the projection. All further modeling can then be based on the parameters used for this projection. Temperature acceleration is modeled using the Arrhenius relation. Different activation energy behaviors are reported. Some works state a field-independent activation energy [30, 33, 38], while others found an electric-field-dependent activation energy [6, 21, 30, 33-35, 39] which eventually saturated [34, 35]. Some data indicates a temperature-range-dependent activation energy on top of the field dependence [37-40]. If such dependencies are present, there is a difference in how the required set of parameters is determined -- whether the field acceleration projection is performed first and the temperature projection is done subsequently or vise versa. The conservative approach, which is to stay within a certain range of the projection target conditions, reduces uncertainties [37]. U P P E R LIMITS FOR TEST CONDITIONS Accelerated testing is only useful as long as the degradation mechanisms remain unchanged, i.e., as long as the extrapolation model is valid. It has been reported that at high voltages the field acceleration changes [36, 37]. This is believed to be due to anode-hole injection occurring at high fields in addition to trap generation dominating at low fields [41, 42]. At very high fields, another transition occurs [43] that is caused by impact ionization becoming significant [41]. In Ref. 43, curves modeling the different mechanisms revealed that the transition can barely be detected in an E plot, which is consistent with data. In Fig. 6, the time-to-breakdown for several different oxides is plotted versus the inverse electric field. The transition from low-field to high-field degradation can be clearly seen. The change depends on oxide thickness, technology and temperature. The trap generation process, especially, has a strong temperature sensitivity [45].
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These upper limits must be considered when extrapolation to a small voltage is intended. The possible range of accelerated condition can be further reduced if the observed change of the thermal activation energy [37-40] is considered. However, since so many different behaviors of the thermal activation energy are reported, it must be verified for each technology, whether or not this limit applies. E (MVlcm)
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Figure 6 Transition from high to low field degradation in the 1/E plot T H E R O L E O F PHYSICAL F A I L U R E ANALYSIS An important part of oxide reliability evaluation is physical failure analysis of stress fails. For oxides in planar capacitors, the detection of the failure location can reveal valuable clues, e.g., if the fails were located at the LOCOS edge [15]. It is also useful to check for the failure location, if test structures with the same gate oxide area but different critical edge lengths show the same yield, to verify whether the breakdown is area driven and not dominated by the critical edge. In more sophisticated, fully integrated, product-like test structures, failure analysis is essential to avoid wrong conclusions and costly process improvement at the wrong process step. For example, the failure-analysis results for a large sample of fails shown in Fig. 3 showed no gate-oxide failures but foreign material and polysilicon extensions, which locally thin down the inter-polysilicon isolation and cause reliability fails. It is interesting, therefore, to find that the real problems in a test designed to characterize the gate oxide are in a different process. This cannot be concluded from the electrical results, which represent typical defect-dominated distributions. However, knowing the failure mechanism allows these to be efficiently eliminated. CONCLUSION This overview covers state-of-the-art gate-oxide reliability evaluation. It was demonstrated that test structure, stress setup and procedure as well as the analysis of the data need comprehensive considerations. Acceleration models were discussed and a statistical approach proposed as an alternative. A transition of the degradation mechanism at high fields occurs, which must be accounted for if data from high fields are used for projection and acceleration-model comparison.
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ACKNOWLEDGEMENT Ernest Y. Wu (IBM) is gratefully acknowledged for many valuable discussions. REFERENCES I.
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28. S. Chiang, R. Wang, J. Chen, K. Hayes, J. McCollum, E. Hamdy, C. Hu, Oxide-nitride-oxideantifuse reliability,IEEE Proc. IRPS, 186-192 (1990). 29. W.M.Mi••er• C.Messiek•N.F.Smith•J.A.Shide•er•Eviden•ef•ra••rre•tSi•2 V••tage A•ee•era••nMode•••EEEPr•c. IRW Final Report, 45-51 (1993). 30. J.S. Suehle, P. Chaparala, C.R. Messick, W.M. Miller, K.C. Boyko, Field and Temperature Acceleration of TimeDependent Dielectric Breakdown in Intrinsic Thin SiO2, IEEE Proc. IRPS, 120-125 (1994). 31. B. Schlund, C.R. Messick, J.S. Suehle, P. Chaparala, A new Physics-based Model for Time-dependent-DielectricBreakdown, IEEE Proc. IRPS, 84-92 (1996). 32. D.J. Coleman, W.R. Hunter, G.A. Brown, I.-C. Chert, Extensions of the Effective Thickness Theory of Oxide Breakdown, IEEE Proc. IRPS, 39-42 (1989). 33. J. Sueh•e• P.Chapara•a• Time-Dependent Die•e•trie Breakd•wn in Thin •ntrinsie Si•2 Fi•ms•Mat. Res. S•c. Symp. Pr•c. 386, 227-235 (1995). 34. K.C. B~yk~ and D.L. Ger~a~h~Time Dependent Die~eetri~ Breakd~wn ~f 2 ~~ `~`~xides~EEE Pr~c. ~RPS~ ~-8 ( ~989 ). 35. J. Prendergast, J. Suehle, P. Chaparala, E. Murphy, M. Stephenson, TDDB Characterization of Thin SiO2 Films with Bimodal Failure Populations, IEEE Proc. IRPS, 124-130 (1995). 36. R.-P. V•••ertsen• Statisti•al Mode••ing •f Time Dependent •xide Breakd•wn Distributi•ns•Micr•electr•n. Reliab. 33• 1665-1677 (1993). 37. R.-P. Vollertsen and W. W. Abadeer, Upper Voltage and Temperature Limitations of Stress Conditions for Relevant Dielectric Breakdown Projections, Proc. ESREF, 551-556 (1994). 38. C. Monserie, P. Mortini, G. Ghibaudo and G. Panankakis, Breakdown Characteristics ofGate andTunnel Oxides versus Field and Temperature, Quality and Reliability Engineering International 9, 321-324 (1993). 39. R. Moazzami, J.C. Lee and C. Hu, Temperature Acceleration of Time-Dependent Breakdown, ED-36, 2462-2465 (1989). 40. C.-F. Chert, C.-Y. Wu, M.-K. Lee and C.-N. Chen, The Dielectric Reliability of Intrinsic Thin SiO2 Films Thermally Grown on a Heavily Doped Si Substrate - Characterization and Modeling, ED-34, 1540-1551 (1987). 41. D. Arnold, E. Cartier, D.J. DiMaria, Theory of high-field electron transport and impact ionization in silicon dioxide, Physical Review B 49, 10 278-10 297 (1994). 42. K.F. Schuegraf, C. Hu, Hole Injection Oxide Breakdown Model for very low Voltage Lifetime Extrapolation, IEEE Proc. IRPS, 7-12 (1993). 43. W.W. Abadeer, R.-P. Vollertsen, R.J. Bolam, D.J. DiMaria and E. Cartier, Correlation between Theory and Data for Mechanisms Leading to Dielectric Breakdown, IEEE'94 Symp. VLSI Techn. Digest of Techn. Papers, 43-44 (1994). 44. N.Shiono, M. Itsumi, A Lifetime Projection Method using Series Model and AccelerationFactors for TDDB failures of Thin Gate Oxides, IEEEProc. IRPS, 1-6 (1993). 45. W.W. Abadeer, R.-P. Vollertsen, Physical Mechanisms of Dielectric Breakdown in SiO2 for the Range of -150°C to 150°C, Proc. ESREF, 107-109 (1995).
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COMPREHENSIVE GATE-OXIDE RELIABILITY EVALUATION FOR DRAM PROCESSES R.-P. VOLLERTSEN 1 and W. W. ABADEER 2 tSIEMENS Comp., Inc., c/o IBM MD 967A, 1000 River Street, Essex Junction, VT 05452, USA 2IBM Microelectronics Division, 1000 River Street, Essex Junction, VT 05452, USA Abstract: This paper discusses dielectric breakdown as a major cause for failure oflCs with less than a half-micron linewidth. Focusing on DRAMs the characterization of dielectric reliability using different types of properly designed test structures and appropriate stress methods is reviewed. Considerations concerning screens and upper limits for stress conditions are presented. With a step stress, the sample size can be reduced and efficiently used to cover the specified lifetime. To understand and identify relevant failure mechanisms, physical failure analysis of representative fails is required. Copyright © 1996 Elsevier Science Ltd INTRODUCTION Thin gate oxides produced by modern MOS technologies are used in a variety of different applications including DRAMs, SRAMs, logic circuits, EEPROMs and power MOSFETs. The demand for higher speed, less power consumption and higher integration density results in downscaling of circuit dimensions, oxide thickness and operation voltage. Due to the nonproportional scaling of oxide thickness and applied voltage, the field over the gate oxide increases [ 1, 2]. At the same time, the oxide becomes more sensitive to defects introduced by process variations and contaminants. Thus, the reliability margins shrink and more accurate evaluation methods are required to balance the cost for process improvement versus reliability margin. Cost and fast feedback are also drivers for fast inline-wafer-level tests [3, 4]. This paper describes methods and considerations for product-relevant, gate-oxide-reliability evaluation during development. Focusing on DRAMs, issues such as failure distribution, modeling, measurement requirements and limitations will be covered as well as the need for failure analysis subsequent to electrical testing. The presented considerations are based on oxide thicknesses ranging from about 9 nm to 22 nm and will also be applicable to products with thinner oxide thickness. STRESS AND EVALUATION PHILOSOPHY The common stress method for reliability analysis of gate oxides operated under constant voltage in the product is an accelerated constant voltage stress. The same mechanism is assumed to dominate degradation during operation and stress. The physical reason for selecting a constant voltage stress is because of charge trapping during stress, which results in decreasing current (negative feedback), thereby slowing down the degradation process and increasing the time to breakdown (tbd). This does not occur, however, for constant current stresses, where the amount of damage-causing carders is kept constant by adjusting the external voltage. Another reason for selecting a constant voltage stress is the availability of models which relate the results from accelerated conditions to operating conditions [5-8], thereby allowing an estimate of the feasibility of an oxide in the product. The times to breakdown resulting from a constant voltage stress are plotted in a Weibull net, which for various
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reasons is best suited for oxide breakdown [9-14]. For large gate-oxide areas and/or large enough sample sizes, bimodal distributions are observed (Fig. 1). The steep part of the distribution (slope>l) is called, by definition, intrinsic distribution or wearout. This nomenclature may sometimes be confusing because physically intrinsic fails are supposed to exhibit identical distributions independent of the area. For gate oxide, however, mostly area scaling of intrinsic distributions is observed. Area-independent intrinsic distributions have been reported [ 15], however, further analysis in this case revealed that all fails were located at the LOCOS edge as the weakest spot of the structure, which limited the lifetime independent of the area. This suggests that for gate oxide, intrinsic distributions mostly represent structural- and/or technology-induced properties rather than pure material properties. The part before the intrinsic distribution (Fig. 1) is caused by defects and called extrinsic distribution. While these fails are also technology induced, they are more severe than the intrinsic fails. The level of the extrinsic part depends strongly on area. Analytical formulas are available to describe the complete bimodal distribution as a combined [16, 17] or competing distribution [12, 17]. However, it was shown that modeling bimodal distributions as competing distributions is more plausible [16, 17] for gate oxide. For products, the extrinsic distribution is usually the relevant part, whereas the intrinsic portion is well beyond lifetime. The latter, of course, must be verified and cannot be taken for granted.
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Figure 1 Bimodal time-to-breakdown distribution in the Weibull net For efficiency, parallel stressing of many parts is usually preferred over serial stressing. This is an advantage of module stresses. On the wafer level, equal structures on different chips are usually so far apart that proper contact and the maintenance of contact is at least difficult. However, different test structures on the same chip can be stressed simultaneously. A different approach to saving time is possible if extrinsic distributions are of interest only. In this case a voltage step stress can be performed. This is a sequence of three to five subsequent constant voltage stresses at different voltages [ 18]. This type of stress uses the same samples throughout the stress, which is the most efficient use of the sample and, at the same time, minimizes the effects of sample inhomogeneities. It also reduces extrapolation uncertainties because the first step can be close to or at use condition. The time saving results from limiting the stress duration of each step. Excellent agreement between step stress and constant-voltage stress results has been demonstrated [19]. E F F E C T O F T E S T DESIGN AND EVALUATION A S S U M P T I O N S The effect of workfunction and polysilicon depletion on the effective oxide field is well known [20, 21 ] and can be estimated using equations of basic physics [ 14]. Series resistance causes an increasing voltage drop with increasing stress voltages and must be taken into account when stressing at highly accelerated voltage or current conditions [22, 23]. Series resistance can be minimized by the proper design of test structure and stress setup. However, in some constant-voltage stress setups, the current is measured across a resistor in the stress circuitry. This is particularly the case when multiple capacitors are stressed in parallel, because voltages can be measured faster than currents and, at the same time, current is limited after a breakdown event.
Gate-oxide reliability evaluation
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For intrinsic distributions, a short screen test at a low voltage prior to stressing successfully eliminates unwanted defective capacitors. The same screening procedure applied when extrinsic distributions are to be stressed may significantly alter the parameters that should be determined [ 18]. A screen has more impact the closer it's voltage is to the stress voltage, because it is not selective, i.e., it does not just remove the unwanted early failure population (different failure mechanism) but also capacitors which belong to the main distribution. According to the effective thickness model [24], the extrinsic distribution consists of capacitors with a wide range of effective thicknesses, which approach zero at very short times (much shorter than the response time of the measurement equipmen0. For capacitors with these weak spots, a low voltage like the screen voltage means a high local field, which causes rapid breakdown. The purpose of the screen is to eliminate a population that represents a different failure mechanism (e.g., real shorts), because they flatten the extrinsic distribution (Fig. 2). A dilemma exists in that the lack of screening eventually results in distributions which are too flat and that inappropriate screening results in distributions that are too steep (Fig. 2). Therefore, Ref. 17 proposes that fields as lbw as 1 MV/cm be used for screening. Even with use of a correct screen prior to the step stress, deviations of step-stress results from constant-voltage-stress results can occur if the difference between subsequent voltages are too small. This is caused by the prestress of the previous step [18]. If prestress is minimized compared to the stress level at the beginning of the accessible time window, tbd distributions will result in straight lines as distributions from constant-voltage stress (Fig. 3). This is achieved by increasing the voltage difference between the steps, with the difference in necessary voltage depending on the acceleration. Improvement of tbd, as in the case of a voltage ramp before a constant voltage stress [25], is not observed for the voltage step stress. 2 1
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TEST S T R U C T U R E TOPOLOGY AND AREA For the investigation of basic gate-oxide breakdown physics, simple planar capacitors are employed which are specially designed to avoid influence from the perimeter. In addition to those structures in early product development, test structures are designed to reflect all possible perimeter- and edgeeffects that are expected on the product. Some of those structures accompany the entire development, e.g., polysilicon gate edges and crossings with thick-oxide isolation, the edge of the thick oxide (LOCOS or STI edges) or trench edges. Both LOCOS edges and shallow-trench isolations (STI) tend to exhibit oxide thinnings (Fig. 4). In addition to the thinning, the STI edge can be very sharp, leading to enhanced electric fields across the oxide. A set of test structures with an identical gate-oxide area but different critical-edge lengths helps to distinguish between gate-oxide area- and perimeter-related fails. Both the topology and area should be somewhat representative for the product, especially if defects need to be investigated. To contain uncertainties in the area extrapolation, the ratio of stressed and projected area should not be more than a factor of 10 [26]. Therefore, test structures will require a
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R.-P. Vollertsen and W. W. Abadeer
great deal of space, which for the most part is not available. A solution to the problem is use of a special reliability-test structure in the product area with topology and critical edges of the product. A schematic floor plan of such a structure is shown in Fig. 5 for a 64Mbit chip. The chip's metal-level wiring is changed so that 2Mbit and 4Mbit blocks are generated and all transfer transistor gates are connected in parallel within each block. The layout of the metal lines account for series resistance effects and minimizes them. Almost no metal remains over the array and special marks are implemented to ease failure localization by an optical beam-induced current technique (OBIC [27]). The 2Mbit and 4Mbit blocks are wired to standard 1 x 25 pad sets, with two pad sets placed in parallel to allow efficient parallel testing of 32Mbits in one pass. Because everything below the metal levels is real product, the test structure will perfectly represent the product. Also, the area of the individual blocks is smaller than the product, thereby allowing a higher yield in early development and lower currents than on a large area during high-field stress. The results from the smaller areas can be combined after stress on a by-chip basis, generating tbd distributions for various areas [26]. With this special test structure, all isolation layers are stressed at the same time and fails are not necessarily caused by gate oxide. Therefore, failure analysis is required to determine the dominant failure mechanisms. Antenna structures to monitor inline charging are also important test structures. These consist of a large polysilicon plate over thick-oxide isolation and a small area of thin oxide. By varying the ratio of the thin-oxide and the thick-oxide areas, structures with different sensitivities are defined. Typical ratios are 1:1000 to 1:100000. 4 Mbit •
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Figure 4 TEM cross section of a MOSFET bordered by shallow-trench isolation (STI)
Figure 5 Schematic floor plan of a 64 Mbit chip specially prepared for gate-oxide stress
ACCELERATION MODELING For the prediction of oxide reliability at operating conditions, two different field acceleration models are widely used. One model describes the time as exponentially dependent on the electric field (E model), whereas in the other model the time depends exponentially on the inverse field (1/E model). Empirical and physical justifications have been published for both models [6-8, 13, 28-31]. An extension of the I/E model, which relates the model to time-to-breakdown distributions considering defects as locally reduced effective-oxide thickness (AXox model), was developed [24] and generalized for both field acceleration models [ 14, 32]. Experimental efforts to identify the correct model showed, for intrinsic distributions, that both models fit the data over a wide field range [29, 30, 33] and, in consequence, data need to be taken especially at low electric fields close to or at operating voltage. For extrinsic distributions no differentiation between the models was possible, despite having data that covered a wide field range including operating conditions [34]. Measurements were performed at very high temperatures well beyond operation or bum-in conditions to reduce stress time at low fields [30, 33, 35]. Resulting data fit to a straight line in the log(tbd) vs. E plot and deviated from a straight line in the 1/E plot. However, at high temperatures a change of the degradation mechanism, as discussed in the next section (Fig. 6), already occurs at a medium field, so part of the data have been taken above that transition. The approach used to identify the correct acceleration model, i.e., fitting the data from a wide range of fields to a straight line is doubtful because once a model is declared to be the correct one, data will be taken mostly at high fields. Therefore, a more
Gate-oxide reliability evaluation
1635
rigorous approach is to use the high-field data only to determine the model parameters and then verify that the behavior at low fields is correctly predicted. In many cases (e.g., also in Ref. 35), this will reveal the transition which is clearly seen in the 1/E plot (Fig. 6), even in the E plot. Thus, the available data does not prove the validity of either model, but rather indicates that the E plot is more forgiving with respect to the degradation physics. Projections from high-field data represent the worst case for the E model and the best case for the 1/E model. For bimodal distributions, the E model has been proposed for the intrinsic and the 1/E model for the extrinsic part of the distribution [35], which suggests that the failure mechanism can also affect acceleration behavior. An alternative statistical approach was proposed [36], which accounted for the slope of the breakdown distributions. The tbd distributions are expected to be parallel and, for the same field difference, equidistant, according to the E model, but showing increasing time differences and decreasing slope with decreasing fields for the 1/E model. The statistical model [36] suggested that the intrinsic and extrinsic part of a bimodal distribution can both independently be modeled using basically the AXox model, but with an additional term for adjusting the acceleration of each failure percentage, which is equivalent to the defect density if the area is kept constant. The additional term considers the slope of the distributions in a way that the data suggest it rather than the AXox model forces it, i.e., the tbd distributions from different voltages can as well be parallel, as expected from the E model. Separate sets of model parameters are required for both the extrinsic and intrinsic distribution [36]. A similar model applied to entire bimodal distributions was proposed recently [ 17]. The different data reported suggest that there is a variety of oxide-field acceleration behaviors, probably technology-related, rather than one universal behavior for all oxides. The pragmatic approach of not forcing certain model parameters to the data, but yet obtaining the complete set of parameters for statistical modeling from the data [37] is a more general alternative. These parameters are determined simultaneously from all data by multiple linear regression [37] or the maximum likelihood method [ 17]. An example of this method is shown in Fig. 3 for step-stress data. The dashed lines represent the projections from multiple linear regression. Even down to operating conditions, the projection shows excellent agreement. This leads to high confidence in the projection. All further modeling can then be based on the parameters used for this projection. Temperature acceleration is modeled using the Arrhenius relation. Different activation energy behaviors are reported. Some works state a field-independent activation energy [30, 33, 38], while others found an electric-field-dependent activation energy [6, 21, 30, 33-35, 39] which eventually saturated [34, 35]. Some data indicates a temperature-range-dependent activation energy on top of the field dependence [37-40]. If such dependencies are present, there is a difference in how the required set of parameters is determined -- whether the field acceleration projection is performed first and the temperature projection is done subsequently or vise versa. The conservative approach, which is to stay within a certain range of the projection target conditions, reduces uncertainties [37]. U P P E R LIMITS FOR TEST CONDITIONS Accelerated testing is only useful as long as the degradation mechanisms remain unchanged, i.e., as long as the extrapolation model is valid. It has been reported that at high voltages the field acceleration changes [36, 37]. This is believed to be due to anode-hole injection occurring at high fields in addition to trap generation dominating at low fields [41, 42]. At very high fields, another transition occurs [43] that is caused by impact ionization becoming significant [41]. In Ref. 43, curves modeling the different mechanisms revealed that the transition can barely be detected in an E plot, which is consistent with data. In Fig. 6, the time-to-breakdown for several different oxides is plotted versus the inverse electric field. The transition from low-field to high-field degradation can be clearly seen. The change depends on oxide thickness, technology and temperature. The trap generation process, especially, has a strong temperature sensitivity [45].
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R.-P. Vollertsenand W. W. Abadeer
These upper limits must be considered when extrapolation to a small voltage is intended. The possible range of accelerated condition can be further reduced if the observed change of the thermal activation energy [37-40] is considered. However, since so many different behaviors of the thermal activation energy are reported, it must be verified for each technology, whether or not this limit applies. E (MVlcm)
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Figure 6 Transition from high to low field degradation in the 1/E plot T H E R O L E O F PHYSICAL F A I L U R E ANALYSIS An important part of oxide reliability evaluation is physical failure analysis of stress fails. For oxides in planar capacitors, the detection of the failure location can reveal valuable clues, e.g., if the fails were located at the LOCOS edge [15]. It is also useful to check for the failure location, if test structures with the same gate oxide area but different critical edge lengths show the same yield, to verify whether the breakdown is area driven and not dominated by the critical edge. In more sophisticated, fully integrated, product-like test structures, failure analysis is essential to avoid wrong conclusions and costly process improvement at the wrong process step. For example, the failure-analysis results for a large sample of fails shown in Fig. 3 showed no gate-oxide failures but foreign material and polysilicon extensions, which locally thin down the inter-polysilicon isolation and cause reliability fails. It is interesting, therefore, to find that the real problems in a test designed to characterize the gate oxide are in a different process. This cannot be concluded from the electrical results, which represent typical defect-dominated distributions. However, knowing the failure mechanism allows these to be efficiently eliminated. CONCLUSION This overview covers state-of-the-art gate-oxide reliability evaluation. It was demonstrated that test structure, stress setup and procedure as well as the analysis of the data need comprehensive considerations. Acceleration models were discussed and a statistical approach proposed as an alternative. A transition of the degradation mechanism at high fields occurs, which must be accounted for if data from high fields are used for projection and acceleration-model comparison.
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ACKNOWLEDGEMENT Ernest Y. Wu (IBM) is gratefully acknowledged for many valuable discussions. REFERENCES I.
2. 3. 4. 5. 6. 7. 8.
9.
I0. 1I. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27.
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