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Contactless measurement of the Si-buried oxide interfacial charges in SOI wafers with surface photovoltage technique
MICROELECTRONIC ENGINEERING ELSEVIER
M~croelectronic Engineering 36 (1997) 351-357
Contactless Measurement of the Si - Buried Oxide lnterfacial Charges in SOl Wafers with Surface Photovoltage Technique. K. Nauka Hewlett-Packard Laboratories, Palo Alto, CA 94304
Surface Photovoltage Technique has been employed to image distribution of the oxide charges present at the Si active layer - buried oxide interface in its vicinity. SOl substrates fabricated by oxygen ion implantation and by wafer bonding have been compared. Oxygen implanted wafers exhibited larger and less uniformly distributed charges than the comparable bonded substrates. Charge density and distribution uniformity was dependent on the oxygen implant dose. Measured charges were not affected by the annealing imitating device processing heat cycle. Demonstrated charge imaging technique could offers an effective way for the SOI substrate screening.
I. Introduction Silicon on Insulator (SO!) subsWates Offer opportunities for extending CMOS IC technology beyond the boundaries imposed by the bulk Si substrates. SOI MOSFETs can consume less power and switch faster than the corresponding bulk Si transistor [1,2]. Additionally, presence of buried oxide can simplify insulation between PMOS and NMOS devices in the CMOS circuit [3]. However, application of SOI substrates in the mainstream CMOS technology requires demonstration of acceptable yields in complex circuits with more than 107 transistors with simultaneous process robustness, scalability, and cost equivalent to the bulk Si processes. Application of the SO1 wafers for sub - 0.25 ~tm CMOS devices requires an in-depth understanding and control of the material properties that might impact the device quality. This is complicated by a variety of competing choices in presently available SOl substrates with no clear winner in view. SOl wafers are fabricated either by implanting Si wafers with large doses of oxygen (SIMOX wafers) followed by a high temperature anneal that restores crystallinity of the top Si layer and forms buried oxide (BOX), or by wafer bonding (BSOI wafers). Si and BOX thicknesses desired in SIMOX wafers are determined by combination of implant parameters and post implant annealing conditions. They can be further refmed by the post-implant oxidation that 0167-9317/97/$17.00 © Elsevier Science B.'~ All rights reserved. PII: S0167-9317(97)00078-6
increases BOX thickness and consumes part of the top Si layer. BSOI wafers are fabricated by bonding two Si wafers followed by either grinding and seloetive etching, or by cleaving away of the major portion of one of the substrates along the stress line induced by H implant. Buried oxides in BSOI substrates are obtained by employing wafers with at least one oxidized surface; bonding takes place between the oxide and Si or between two oxidized surfaces. Selectivity required for etching of submicron Si layers can be obtained either by application of precision plasma assisted etching or by introduction of an epitaxial layer with high dopant gradient acting as an etch stop. Etching is frequently followed by touch-polish to decrease surface roughness. It is believed that the future mainstream SO1 MOSFETs will require substrates with thin Si active layers and Si - BOX interfaces that remain in close proximity of devices or become their active parts [4]. Therefore, understanding and control of the electrical properties of BOX and Si - BOX interface are some of the major challenges facing SOl technology. Electrically active defects within BOX and at the BOX - Si interface are of primary interest. However, their detection and analysis can present a considerable challenge. It frequently relies on analysis of dedicated test structures that incorporate Si - BOX interracial region. Defects data are obtained at the expense of additional device processing and analysis. They are often convoluted
352
K. Nauka / Microelectronic Engineering 36 (1997) 351-357
SOI wafer
%
Si substrate
,%,
,
A.
.......
q; o~t;~r~ law~r
B.
"
Si active layer
hv
~E~
:~::
~ •.: ................................. . - - ~ F - i I -E, ~
....
7:=
Figure 1. Schematic band diagram of the p-type SOl wafer with thin Si active layer: A.) under equilibrium, B.) under strong illumination (Eg,p < hv). with data related to other properties of the measured test structures [5,6]. This work demonstrates application of the Surface Photovoltage Technique (SPV) as an effective monitoring tool for fast, qualitative, and non-contact imaging of electrical charges present at the Si - BOX interface or in its vicinity.
2. Experimental SPV technique employed in this work was based on previously described Si surface charge measurement [7,8]. The SPV signal was obtained by illuminating front side of the wafer with monochromatic phonon flux (~ = 800 urn), while back side remained in darkness. Non-equilibrium carriers generated by absorbed photons caused a decrease of both the surface and the interface potential barriers (Figure 1.A and B.) giving raise to the SPV signal. At high photon flux densities both potential barriers disappeared, and the SPV signal reached maximum. Under these conditions the measured SPV signal can be expressed as follows:
(1)
Vspv = vs + vi
Qspv : = A * (Q~ + Bl * (Qif+ B2 * Qib)). = m *
Calibration constant A can be calculated from a standard space charge expression [9]. However, in this experiment A was determined by comparing SPV results with the corresponding C-V oxide
charge measurements of the MOS capacitors fabricated using bulk Si wafers (Figure 2). BI describes attenuation of the photon flux before it reaches the Si active layer - BOX interface, Bz represents attenuation within the oxide. Both B1 and B2 were calculated using the known Si and SiO2 absorption and reflection coefficients. Vs and Vi are respective surface photovoltage components due to the Si surface charge (Qs) and to the image charges introduced in the Si active layer (Qif) and in the
10
E
09
=>
-10
¢.~ -20
-30 0
10 C-V: oxide
20
30
40
c h a r g e (x 1010 c~n-2)
Figure 2. Correlation between the interracial charge data obtained by C-V and SPV for bulk Si MOS capacitors.
K. Nauka / Microelectronic Engineering 36 (1997) 351-357 substrate (Qib) by charges present in the BOX. Present experiments were limited to the SO1 wafers with Si active layers much thinner than the buried oxides. Therefore, only a small portion of the photon flux could reach BOX - Si substrate interface, and its contribution to the SPV signal was negligible. Effect exerted by an oxide charge on Qif was inversely proportional to the distance from Si - BOX interface. Thus, SPV measurement was the most sensitive to the Si - BOX interfacial charges. Contribution of Vs to the measured SPV signal was evaluated by applying wafer cleans that affected only the Si surface charges, while interracial charges remained unchanged. It was found that Vs was only a small part of the overall SPV signal, and it was relatively constant throughout the wafer's surface.
353
Thus, variations of the SPV signal on SOl wafer were due to the non-uniform distribution of Qif. Figure 3 demonstrates maps of the QsPv obtained for a SIMOX wafer cleaned using chemical treatments leaving distinctly different types of surface charges. First, mixture of H20, HCI, and H202 was employed (SC2 clean [10]) and the wafer was measured (Figure 3.A); then the wafer was washed with HF and measured again (Figure 3.B). SC2 clean formed thin chemical oxide, while HF dip removed the oxide and left Si surface terminated with H atoms [11,12]. These results are in agreement with the data obtained for bulk Si wafers (Figure 3.C and D) demonstrating that Qs is a small, constant, additive component of the measured Qsvv signal (less than 7 % - 10 % of the measured charge value).
B? (* 101° cm"2) 17.0-19.0 ~ 19.0-21.0 21.0-23.0 23.0-25.0 25.0-27.0 27.0-29.0 29.0-31.0
18.0-22.0 22.0-25.0 25.0-28.0 26.0-28.0 28.0-30.0 30.0-32.0 32.0-35.0
D. (* 101° cm-2)
i <
2.0 2.0 - 5.0 5.0 - 8.0 > 8.0 > 8.0 > 8.0 > 8.0
Figure 3. A.) and B.) Qsvv maps o f a SIMOX wafer after RCA clean (SC2 last) (A.) and after HF dip (B.); top Si layer thickness = 100 nm, BOX thickness = 370 nm. C.) and D.) QsPv maps of a bulk Si wafer after RCA clean (SC2 last) (C.) and after HF dip (D.).
354
K. Nauka / Microelectronic Engineering 36 (1997) 351-357
B.)
A.)
(* 1010 cm .2)
!4,0--!~,0 1&0,21,0 21.0-23,0 23.0-25.0 25.0-28.0 28.0-30.0 30,0-33.0
.<2.0 .2.0:4~0 4,0.-8.0 8,0-30,0 30.0-45.0 45.0-60.0 > 60.0
Figure 4. Qif map of A.) SIMOX wafer (Si active layer thi6l(4~ -- |~09 nm, BOX thickness = 380 nm), B.) BSOI wafer (Si active layer thickness = 160 nm, BOX thickness = 400 nm).
B.) (, 10!° cm-:) 16.0-22.0 22.0-25.0 25.0-28.0 28.0-30.0 30.0-33.0 33,0,36,0 36.0-40.0
3.0-6.0 6.0-10.0 10.0-15.0 15.0-20.0 20.0-25.0 25.0-35.0 >35.0
Figure 5. Qif map of SIMOX wafers with oxygen doses equal: A.) | .8 * 1018 at / cm2, B.) 2.1 * 1017 at / cm 2. SPV measurements were conducted using a commercial SPV system [13] equipped with the surface charge monitor. It did not required any wafer preparation, and facilitated non-contact wafer mapping with resolution of approx. 3 mm (size of the SPV probe). Clean room compatibility and fast operation allowed to employ it for the in-line qualification of incoming SOl wafers. 3. Results and Discussion. 3.1. Characterization of Qif Interfacial Charges Figure 4 demonstrates charge distribution observed for SIMOX (A.) and BSOI (B.) wafers with similar thicknesses of the Si active region and BOX. Non-uniform Qif distribution, similar to the one in Figure 4.A, was observed for all SIMOX
substrates. BSOI wafers exhibited lower and more uniformly distributed Qif charges, except for the areas where interracial voids were present (Figure 4,B). Correlation between the regions of localized and very high Qif and interfacial voids was confirmed by comparing SPV Qif maps and crosssectional TEM images. As expected, localized regions of high Qif in BSOI wafers were seen only in the case of substrates where top interface (Si active layer - BOX) was the fused boundary. They were not observed in the substrates with bottom fused interface (BOX - Si substrate), or in the case of fused boundary buried within the BOX away from the Si active layer - BOX interface. Although pattern of the Qif varied between the SIMOX wafers, the relative magnitude of the variations remained constant for a given O dose. An increase of the O dose caused increase of the average
K. Nauka / Microelectronic Engineering 36 (1997) 351-357
50
• 0
uniformities remain unchanged throughout device processing, and they can have deleterious impact on device yield. Figure 7 compares charge distribution in SIMOX wafer before (A) and after (B) annealing.
00
average value standard deviation
40 0
x (tl J~
3.2. Correlation between SPV results and device properties.
0
o
30 20 10
• 0 le÷17
0
355
0
0 le+18 0 dose (at / cm 2)
Figure 6. Correlation between the O dose and Qif observed in SIMOX wafers. Qif value and of its variation across the wafer as measured by the Qif standard deviation. Figure 5 compares Qif distributions observed for SIMOX substrates with high (A) and low (B) O doses while Figure 6 demonstrates correlation between the Qif and O dose. In order to investigate stability of the Qif charges SOl wafers were subjected to annealing process imitating heat treatment cycle of the 0.25 Ixm CMOS IC manufacturing process. SPV mapping revealed Qif distribution unchanged by the heat treatment. Thus, it can be expected that observed Qif non-
SPV offers an indirect way of imaging electrically active oxide. Measured image charge depends not only on density of the oxide charges but also on their location with respect to the Si - BOX interface. In the case when majority of defects resides at the interface SPV can provide direct image of the charges allowing to eliminate faulty SO1 substrates. Figure 8 demonstrates correlation between the interracial charges and subthreshold leakage obtained by simulating properties of a partially depleted SOl MOSFET [7]. NMOS transistor with 0.25 ~na channel length, Si active layer thickness between 100 nm and 150 nm, BOX thickness equal 400 nm, and retrograde implanted dopant concentration in the channel region were assumed. Modeling data appear to agree with few available experimental results obtained for devices with similar structures. BOX charges located further from the interface cannot be seen with SPV. In the recent study [14] electrically active oxide defects were formed by Si implantation into BOX and high field BOX conductivity was measured as a function of the substrate temperature during implantation. It was found that high implant substrate temperature
A.)
B.)
(, 10~°cm-2) i
15.0-20.0 20.0-22.0 22.0-25.0 25.0-28.0 28.0-30.0 30.0-32.0 32.0-34.0
Figure 7. Qir map of a SIMOX wafer (Si active layer thickness = 105 nm, BOX thickness = 380 run) before (A.) and after (B.) heat treatment corresponding to the 0.25 ~tm CMOS IC process.
K. Nauka/Microelectronic Engineering 36 (1997) 351-357
356 Table 1. (see Ref. 14)
Low implant substrate temperature
High implant substrate temperature
Current Density (A/cm 2)
Current Density (AJcm 2)
SPV (a.u.)
Front 0 injection
Back 2) injection
SPV (a.u.)
Front ]) injection
Back 2) injection
12
3e-9
2e-8
65
2.5e-8
7e-10
o injection across Si active layer - BOX interface, 2) injection across Si substrate - BOX interface. text favored formation of defects in the vicinity of Si active layer - BOX, while low substrate temperature during implantation introduced defects near the BOX - Si substrate interface. Presence of charges in the vicinity of an interface was correlated with increase of a current injected through this interface. Although in both cases overall defect densities were similar, SPV detected large amount of charges in the first case, and failed to detect any significant amount of charges in the second case (Table 1). le-4 E
E
le-5
c
le-6
g 0
•
• 0
Vd = 0.05 V Vd = 2.50 V experiment (Vd = 2,5 V)
I~ •
0
le-7
c~
le-8
~
le-9
N
le-10
~
le-11
N
le-12
were correlated with presence of interfacial voids in BSOI wafers, and with O implant conditions in SIMOX wafers. Interfacial defects appeared to remain unaffected by heat cycle analogous to device processing conditions. Thus, they were likely to have deleterious impact on devices. Device degradation introduced by SPV measured interfacial charges has been confirmed by preliminary device results obtained for the 0.25 micron CMOS SOl transistors, and further elucidated by device modeling. It was proposed that SPV could offer an effective way for screening of the incoming SOl substrates before device fabrication.
References
•
OI
01
• 6
O •
IQ
•
•
le-13 le+11
le+12
Si - B O X Interracial Charges (cm "2)
Figure 8. Subthreshold leakage as a function of Si BOX interfacial charge density. 4. Conclusions.
Surface Photovoltage Technique was employed to image distribution of electrically active oxide defects present at the Si active layer - BOX interface and in its vicinity. Density and distribution of defects
1. G. Shadini, 1993 IEDM Tech Digest, p.813. 2. Y. Yamaguchi, IEEE Trans. Electron. Dev. 40, 179 (1993). 3. J. -P. Colinge "Silicon-on-Insulator Technology: Materials to VLSI", Kluwer Academic Publ., Boston, 1991, chapter 4. 4. D. A. Antoniadis, Proc. of the 1995 IEEE Intemat. SOl Conf., IEEE Publ. #95CH35763, p.1. 5. H. E. Boesch Jr., T. L. Taylor, L. R. Hire, W. E. Bailey, IEEE Trans. Nucl. Sci. 37, 1892 (1990). 6. F. T. Brady, J. T. Chn, S. S. Li, Proc. of the 1990 SOS / SOl Conf., p.158. 7. K. Nauka, M. Cao, F. Assaderaghi, Proc. of the 1995 IEEE Internat. SOI Conf., IEEE Publ. #95CH35763, p.52. 8. K. Nauka, M. Cao, Proc. of DRIP VI, IOP Conf. Ser. No. 149, p.79. 9. P. Edchnan, J. Lagowski, L. Jastrzebski "Surface
Charge Imaging in Semiconductor Wafers by Surface Photovoltage", presented at the 1992
K. Nauka /Microelectronic Engineering 36 (1997) 351-357 Spring Materials Research Meeting, San Francisco, CA, April 1992. 10. W. Kern, D. A. Puotinen, RCA Rev. 31, 187 (1970). 11. G. S. Higashi, Y. J. Chabal, G. W. Trucks, K. Raghavachari, Appl. Phys. Lett. 56, 656 (1990). 12. M. Morita, T. Ohmi, E. Hasegawa, A. Teramoto, Jpn. J. Appl. Phys. 24, L2392 (1990).
357
13. Model CMS A/R, Semiconductor Diagnostics, Inc. Tampa, FL. 14. J. U. Yoon, G. N. Kim, J.-H. Y. Krska, J. E. Chung, L. P. Allen, K. Goodson, O. Kaeding, K. Nauka "Correlation of Electrical and Physical
Properties of SIMOX BOX Affected by Various Implantation Parameters", presented at the 1996 Fall Materials Research Society Meeting, Boston, MA, December 1996.
M~croelectronic Engineering 36 (1997) 351-357
Contactless Measurement of the Si - Buried Oxide lnterfacial Charges in SOl Wafers with Surface Photovoltage Technique. K. Nauka Hewlett-Packard Laboratories, Palo Alto, CA 94304
Surface Photovoltage Technique has been employed to image distribution of the oxide charges present at the Si active layer - buried oxide interface in its vicinity. SOl substrates fabricated by oxygen ion implantation and by wafer bonding have been compared. Oxygen implanted wafers exhibited larger and less uniformly distributed charges than the comparable bonded substrates. Charge density and distribution uniformity was dependent on the oxygen implant dose. Measured charges were not affected by the annealing imitating device processing heat cycle. Demonstrated charge imaging technique could offers an effective way for the SOI substrate screening.
I. Introduction Silicon on Insulator (SO!) subsWates Offer opportunities for extending CMOS IC technology beyond the boundaries imposed by the bulk Si substrates. SOI MOSFETs can consume less power and switch faster than the corresponding bulk Si transistor [1,2]. Additionally, presence of buried oxide can simplify insulation between PMOS and NMOS devices in the CMOS circuit [3]. However, application of SOI substrates in the mainstream CMOS technology requires demonstration of acceptable yields in complex circuits with more than 107 transistors with simultaneous process robustness, scalability, and cost equivalent to the bulk Si processes. Application of the SO1 wafers for sub - 0.25 ~tm CMOS devices requires an in-depth understanding and control of the material properties that might impact the device quality. This is complicated by a variety of competing choices in presently available SOl substrates with no clear winner in view. SOl wafers are fabricated either by implanting Si wafers with large doses of oxygen (SIMOX wafers) followed by a high temperature anneal that restores crystallinity of the top Si layer and forms buried oxide (BOX), or by wafer bonding (BSOI wafers). Si and BOX thicknesses desired in SIMOX wafers are determined by combination of implant parameters and post implant annealing conditions. They can be further refmed by the post-implant oxidation that 0167-9317/97/$17.00 © Elsevier Science B.'~ All rights reserved. PII: S0167-9317(97)00078-6
increases BOX thickness and consumes part of the top Si layer. BSOI wafers are fabricated by bonding two Si wafers followed by either grinding and seloetive etching, or by cleaving away of the major portion of one of the substrates along the stress line induced by H implant. Buried oxides in BSOI substrates are obtained by employing wafers with at least one oxidized surface; bonding takes place between the oxide and Si or between two oxidized surfaces. Selectivity required for etching of submicron Si layers can be obtained either by application of precision plasma assisted etching or by introduction of an epitaxial layer with high dopant gradient acting as an etch stop. Etching is frequently followed by touch-polish to decrease surface roughness. It is believed that the future mainstream SO1 MOSFETs will require substrates with thin Si active layers and Si - BOX interfaces that remain in close proximity of devices or become their active parts [4]. Therefore, understanding and control of the electrical properties of BOX and Si - BOX interface are some of the major challenges facing SOl technology. Electrically active defects within BOX and at the BOX - Si interface are of primary interest. However, their detection and analysis can present a considerable challenge. It frequently relies on analysis of dedicated test structures that incorporate Si - BOX interracial region. Defects data are obtained at the expense of additional device processing and analysis. They are often convoluted
352
K. Nauka / Microelectronic Engineering 36 (1997) 351-357
SOI wafer
%
Si substrate
,%,
,
A.
.......
q; o~t;~r~ law~r
B.
"
Si active layer
hv
~E~
:~::
~ •.: ................................. . - - ~ F - i I -E, ~
....
7:=
Figure 1. Schematic band diagram of the p-type SOl wafer with thin Si active layer: A.) under equilibrium, B.) under strong illumination (Eg,p < hv). with data related to other properties of the measured test structures [5,6]. This work demonstrates application of the Surface Photovoltage Technique (SPV) as an effective monitoring tool for fast, qualitative, and non-contact imaging of electrical charges present at the Si - BOX interface or in its vicinity.
2. Experimental SPV technique employed in this work was based on previously described Si surface charge measurement [7,8]. The SPV signal was obtained by illuminating front side of the wafer with monochromatic phonon flux (~ = 800 urn), while back side remained in darkness. Non-equilibrium carriers generated by absorbed photons caused a decrease of both the surface and the interface potential barriers (Figure 1.A and B.) giving raise to the SPV signal. At high photon flux densities both potential barriers disappeared, and the SPV signal reached maximum. Under these conditions the measured SPV signal can be expressed as follows:
(1)
Vspv = vs + vi
Qspv : = A * (Q~ + Bl * (Qif+ B2 * Qib)). = m *
Calibration constant A can be calculated from a standard space charge expression [9]. However, in this experiment A was determined by comparing SPV results with the corresponding C-V oxide
charge measurements of the MOS capacitors fabricated using bulk Si wafers (Figure 2). BI describes attenuation of the photon flux before it reaches the Si active layer - BOX interface, Bz represents attenuation within the oxide. Both B1 and B2 were calculated using the known Si and SiO2 absorption and reflection coefficients. Vs and Vi are respective surface photovoltage components due to the Si surface charge (Qs) and to the image charges introduced in the Si active layer (Qif) and in the
10
E
09
=>
-10
¢.~ -20
-30 0
10 C-V: oxide
20
30
40
c h a r g e (x 1010 c~n-2)
Figure 2. Correlation between the interracial charge data obtained by C-V and SPV for bulk Si MOS capacitors.
K. Nauka / Microelectronic Engineering 36 (1997) 351-357 substrate (Qib) by charges present in the BOX. Present experiments were limited to the SO1 wafers with Si active layers much thinner than the buried oxides. Therefore, only a small portion of the photon flux could reach BOX - Si substrate interface, and its contribution to the SPV signal was negligible. Effect exerted by an oxide charge on Qif was inversely proportional to the distance from Si - BOX interface. Thus, SPV measurement was the most sensitive to the Si - BOX interfacial charges. Contribution of Vs to the measured SPV signal was evaluated by applying wafer cleans that affected only the Si surface charges, while interracial charges remained unchanged. It was found that Vs was only a small part of the overall SPV signal, and it was relatively constant throughout the wafer's surface.
353
Thus, variations of the SPV signal on SOl wafer were due to the non-uniform distribution of Qif. Figure 3 demonstrates maps of the QsPv obtained for a SIMOX wafer cleaned using chemical treatments leaving distinctly different types of surface charges. First, mixture of H20, HCI, and H202 was employed (SC2 clean [10]) and the wafer was measured (Figure 3.A); then the wafer was washed with HF and measured again (Figure 3.B). SC2 clean formed thin chemical oxide, while HF dip removed the oxide and left Si surface terminated with H atoms [11,12]. These results are in agreement with the data obtained for bulk Si wafers (Figure 3.C and D) demonstrating that Qs is a small, constant, additive component of the measured Qsvv signal (less than 7 % - 10 % of the measured charge value).
B? (* 101° cm"2) 17.0-19.0 ~ 19.0-21.0 21.0-23.0 23.0-25.0 25.0-27.0 27.0-29.0 29.0-31.0
18.0-22.0 22.0-25.0 25.0-28.0 26.0-28.0 28.0-30.0 30.0-32.0 32.0-35.0
D. (* 101° cm-2)
i <
2.0 2.0 - 5.0 5.0 - 8.0 > 8.0 > 8.0 > 8.0 > 8.0
Figure 3. A.) and B.) Qsvv maps o f a SIMOX wafer after RCA clean (SC2 last) (A.) and after HF dip (B.); top Si layer thickness = 100 nm, BOX thickness = 370 nm. C.) and D.) QsPv maps of a bulk Si wafer after RCA clean (SC2 last) (C.) and after HF dip (D.).
354
K. Nauka / Microelectronic Engineering 36 (1997) 351-357
B.)
A.)
(* 1010 cm .2)
!4,0--!~,0 1&0,21,0 21.0-23,0 23.0-25.0 25.0-28.0 28.0-30.0 30,0-33.0
.<2.0 .2.0:4~0 4,0.-8.0 8,0-30,0 30.0-45.0 45.0-60.0 > 60.0
Figure 4. Qif map of A.) SIMOX wafer (Si active layer thi6l(4~ -- |~09 nm, BOX thickness = 380 nm), B.) BSOI wafer (Si active layer thickness = 160 nm, BOX thickness = 400 nm).
B.) (, 10!° cm-:) 16.0-22.0 22.0-25.0 25.0-28.0 28.0-30.0 30.0-33.0 33,0,36,0 36.0-40.0
3.0-6.0 6.0-10.0 10.0-15.0 15.0-20.0 20.0-25.0 25.0-35.0 >35.0
Figure 5. Qif map of SIMOX wafers with oxygen doses equal: A.) | .8 * 1018 at / cm2, B.) 2.1 * 1017 at / cm 2. SPV measurements were conducted using a commercial SPV system [13] equipped with the surface charge monitor. It did not required any wafer preparation, and facilitated non-contact wafer mapping with resolution of approx. 3 mm (size of the SPV probe). Clean room compatibility and fast operation allowed to employ it for the in-line qualification of incoming SOl wafers. 3. Results and Discussion. 3.1. Characterization of Qif Interfacial Charges Figure 4 demonstrates charge distribution observed for SIMOX (A.) and BSOI (B.) wafers with similar thicknesses of the Si active region and BOX. Non-uniform Qif distribution, similar to the one in Figure 4.A, was observed for all SIMOX
substrates. BSOI wafers exhibited lower and more uniformly distributed Qif charges, except for the areas where interracial voids were present (Figure 4,B). Correlation between the regions of localized and very high Qif and interfacial voids was confirmed by comparing SPV Qif maps and crosssectional TEM images. As expected, localized regions of high Qif in BSOI wafers were seen only in the case of substrates where top interface (Si active layer - BOX) was the fused boundary. They were not observed in the substrates with bottom fused interface (BOX - Si substrate), or in the case of fused boundary buried within the BOX away from the Si active layer - BOX interface. Although pattern of the Qif varied between the SIMOX wafers, the relative magnitude of the variations remained constant for a given O dose. An increase of the O dose caused increase of the average
K. Nauka / Microelectronic Engineering 36 (1997) 351-357
50
• 0
uniformities remain unchanged throughout device processing, and they can have deleterious impact on device yield. Figure 7 compares charge distribution in SIMOX wafer before (A) and after (B) annealing.
00
average value standard deviation
40 0
x (tl J~
3.2. Correlation between SPV results and device properties.
0
o
30 20 10
• 0 le÷17
0
355
0
0 le+18 0 dose (at / cm 2)
Figure 6. Correlation between the O dose and Qif observed in SIMOX wafers. Qif value and of its variation across the wafer as measured by the Qif standard deviation. Figure 5 compares Qif distributions observed for SIMOX substrates with high (A) and low (B) O doses while Figure 6 demonstrates correlation between the Qif and O dose. In order to investigate stability of the Qif charges SOl wafers were subjected to annealing process imitating heat treatment cycle of the 0.25 Ixm CMOS IC manufacturing process. SPV mapping revealed Qif distribution unchanged by the heat treatment. Thus, it can be expected that observed Qif non-
SPV offers an indirect way of imaging electrically active oxide. Measured image charge depends not only on density of the oxide charges but also on their location with respect to the Si - BOX interface. In the case when majority of defects resides at the interface SPV can provide direct image of the charges allowing to eliminate faulty SO1 substrates. Figure 8 demonstrates correlation between the interracial charges and subthreshold leakage obtained by simulating properties of a partially depleted SOl MOSFET [7]. NMOS transistor with 0.25 ~na channel length, Si active layer thickness between 100 nm and 150 nm, BOX thickness equal 400 nm, and retrograde implanted dopant concentration in the channel region were assumed. Modeling data appear to agree with few available experimental results obtained for devices with similar structures. BOX charges located further from the interface cannot be seen with SPV. In the recent study [14] electrically active oxide defects were formed by Si implantation into BOX and high field BOX conductivity was measured as a function of the substrate temperature during implantation. It was found that high implant substrate temperature
A.)
B.)
(, 10~°cm-2) i
15.0-20.0 20.0-22.0 22.0-25.0 25.0-28.0 28.0-30.0 30.0-32.0 32.0-34.0
Figure 7. Qir map of a SIMOX wafer (Si active layer thickness = 105 nm, BOX thickness = 380 run) before (A.) and after (B.) heat treatment corresponding to the 0.25 ~tm CMOS IC process.
K. Nauka/Microelectronic Engineering 36 (1997) 351-357
356 Table 1. (see Ref. 14)
Low implant substrate temperature
High implant substrate temperature
Current Density (A/cm 2)
Current Density (AJcm 2)
SPV (a.u.)
Front 0 injection
Back 2) injection
SPV (a.u.)
Front ]) injection
Back 2) injection
12
3e-9
2e-8
65
2.5e-8
7e-10
o injection across Si active layer - BOX interface, 2) injection across Si substrate - BOX interface. text favored formation of defects in the vicinity of Si active layer - BOX, while low substrate temperature during implantation introduced defects near the BOX - Si substrate interface. Presence of charges in the vicinity of an interface was correlated with increase of a current injected through this interface. Although in both cases overall defect densities were similar, SPV detected large amount of charges in the first case, and failed to detect any significant amount of charges in the second case (Table 1). le-4 E
E
le-5
c
le-6
g 0
•
• 0
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were correlated with presence of interfacial voids in BSOI wafers, and with O implant conditions in SIMOX wafers. Interfacial defects appeared to remain unaffected by heat cycle analogous to device processing conditions. Thus, they were likely to have deleterious impact on devices. Device degradation introduced by SPV measured interfacial charges has been confirmed by preliminary device results obtained for the 0.25 micron CMOS SOl transistors, and further elucidated by device modeling. It was proposed that SPV could offer an effective way for screening of the incoming SOl substrates before device fabrication.
References
•
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Si - B O X Interracial Charges (cm "2)
Figure 8. Subthreshold leakage as a function of Si BOX interfacial charge density. 4. Conclusions.
Surface Photovoltage Technique was employed to image distribution of electrically active oxide defects present at the Si active layer - BOX interface and in its vicinity. Density and distribution of defects
1. G. Shadini, 1993 IEDM Tech Digest, p.813. 2. Y. Yamaguchi, IEEE Trans. Electron. Dev. 40, 179 (1993). 3. J. -P. Colinge "Silicon-on-Insulator Technology: Materials to VLSI", Kluwer Academic Publ., Boston, 1991, chapter 4. 4. D. A. Antoniadis, Proc. of the 1995 IEEE Intemat. SOl Conf., IEEE Publ. #95CH35763, p.1. 5. H. E. Boesch Jr., T. L. Taylor, L. R. Hire, W. E. Bailey, IEEE Trans. Nucl. Sci. 37, 1892 (1990). 6. F. T. Brady, J. T. Chn, S. S. Li, Proc. of the 1990 SOS / SOl Conf., p.158. 7. K. Nauka, M. Cao, F. Assaderaghi, Proc. of the 1995 IEEE Internat. SOI Conf., IEEE Publ. #95CH35763, p.52. 8. K. Nauka, M. Cao, Proc. of DRIP VI, IOP Conf. Ser. No. 149, p.79. 9. P. Edchnan, J. Lagowski, L. Jastrzebski "Surface
Charge Imaging in Semiconductor Wafers by Surface Photovoltage", presented at the 1992
K. Nauka /Microelectronic Engineering 36 (1997) 351-357 Spring Materials Research Meeting, San Francisco, CA, April 1992. 10. W. Kern, D. A. Puotinen, RCA Rev. 31, 187 (1970). 11. G. S. Higashi, Y. J. Chabal, G. W. Trucks, K. Raghavachari, Appl. Phys. Lett. 56, 656 (1990). 12. M. Morita, T. Ohmi, E. Hasegawa, A. Teramoto, Jpn. J. Appl. Phys. 24, L2392 (1990).
357
13. Model CMS A/R, Semiconductor Diagnostics, Inc. Tampa, FL. 14. J. U. Yoon, G. N. Kim, J.-H. Y. Krska, J. E. Chung, L. P. Allen, K. Goodson, O. Kaeding, K. Nauka "Correlation of Electrical and Physical
Properties of SIMOX BOX Affected by Various Implantation Parameters", presented at the 1996 Fall Materials Research Society Meeting, Boston, MA, December 1996.