Copper electromigration modeling including barrier layer effect

Solid-State Electronics 45 (2001) 2011±2016

Copper electromigration modeling including barrier layer e€ect W. Wu, J.S. Yuan * Chip Design and Reliability Laboratory, School of Electrical Engineering and Computer Science, College of Engineering, University of Central Florida, Orlando, FL 32816-2450, USA Received 17 April 2001; received in revised form 14 May 2001; accepted 29 May 2001

Abstract Electromigration lifetime considering the barrier layer e€ect under the DC and pulsed DC stress is analyzed numerically. The barrier layer used to stop the copper di€usion also improves the interconnect lifetime. The improvement of lifetime under the DC stress is higher than that under the pulsed DC stress. The lifetime model predictions are also compared with experimental data. Good agreement between the model predictions and experiments is obtained. Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: Copper electromigration; Barrier layer e€ect; Pulse-DC stress; Interconnect lifetime; Continuity equation; Reduced vacancy concentration

1. Introduction Copper interconnects are widely used to replace aluminum lines due to reduced RC time constant from copper's low resistivity. Several challenges occur in integration of copper lines into integrated circuits [1]. However, copper is a more mobile element than aluminum. A barrier layer is needed to inhibit the di€usion of copper into adjacent dielectric layers and the silicon substrate. The barrier layer may provide a path of the vacancy ¯ux to potentially strengthen the interconnect lifetime. The electromigration including the barrier layer is a two-dimensional problem. Although there are lots of e€orts to solving the one-dimensional continuity equation for electromigration study [2±8], few results have been published on the two-dimensional problem due to its complexity and large quantity of calculation. Furthermore, few data on the copper electromigration lifetime are available even numerous publications on the copper interconnects are reported [9±21].

*

Corresponding author. Tel.: +1-407-823-5719; fax: +1-407823-5835. E-mail address: [email protected] (J.S. Yuan).

In this paper, we focus on solving the quasi-twodimensional problem using the one-dimensional equation with appropriate boundary conditions to evaluate the copper interconnect barrier e€ect. The reduced vacancy concentration versus reduced time under both DC and pulse-DC stress is examined. The lifetime model predictions of the copper interconnect are compared with the experimental data using the NIST test structure.

2. Analysis 2.1. Continuity equation Since interconnect atoms migrate via a vacancy exchange mechanism, the ¯ux of metal atoms is equal and opposite to the ¯ux of vacancies. Under an applied electrical ®eld E and the chemical potential gradient rl due to mechanical stress, the net vacancy ¯ux is given by JV ˆ C V

DV …rl ‡ q E† kT

…1†

where CV is the vacancy concentration, DV is the vacancy di€usivity, kT is the thermal energy, and q is the e€ective charge. The e€ective charge q ˆ jZ  je, where e is the electron charge, and Z  is the e€ective charge

0038-1101/01/$ - see front matter Ó 2001 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 1 ) 0 0 2 1 7 - 9

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W. Wu, J.S. Yuan / Solid-State Electronics 45 (2001) 2011±2016

number. Supposing adding or subtracting lattice defects at the grain boundary or interface maintains local equilibrium for vacancies, the chemical potential can be written [9] l ˆ l0

Xr

…2†

where l0 is the chemical potential in the absence of stress, X is the atomic volume, and r is the tensile stress normal to the grain boundary or interface. At equilibrium the relationship between vacancy concentration and mechanical stress is  CV ˆ CV0 exp

Xr kT

 …3†

where CV0 is the equilibrium vacancy concentration in the absence of stress. Therefore, the vacancy ¯ux can be expressed as  JV ˆ

DV

oCV ox

q E CV kT

 …4†

The vacancy concentration as a function of space and time can be obtained by solving the continuity equation oCV oJV ‡ ‡cˆ0 ot ox

…5†

where c is the sink/source term which allows for the recombination or generation of vacancies at sites such as grain boundaries, dislocations, or surfaces. Combining Eqs. (1)±(5) gives oCV ot

Da0

BX CV kT e CV0



o2 CV o2 x

q E oCV kT ox

 ˆ0

…6†

where Da0 is the atomic di€usivity in the absence of stress, B is the appropriate elastic modulus which depends on the properties of the metal and the surrounding material and on the line aspect ratio (thickness to width), and e is the ratio of the line cross-sectional area of the di€usion path.

oCV ot

BX CV kT e CV0 CV BX 0 R …CV C kT e



Da0

o2 CV o2 x

q E oCV kT ox



B CV0 †ˆ0

…7†

where C is the concentration of lattice sites, R0 is a B proportional constant, CV0 is the vacancy concentration in the barrier layer in the absence of stress. There exists a relationship between C; CV ; DV , and Da0 [9] Da0 ˆ DV

CV0 C

…8†

Introducing dimensionless variables for the reduced length n, time s, and vacancy concentration m, x n ; l

 s

BX kT e



Da0 t ; l2

m

CV CV0

…9†

where l is the ®nite line length and rewriting Eq. (7) gives 1 om o ˆ m os on



om on

 am ‡ b…m

s†

…10†

where aˆ

q El ; kT

b ˆ R0

CV0 l2 ; C Da0

sˆ

B CV0 CV0

…11†

The solution of Eq. (10) exists for the vacancy buildup at early time for which the vacancy concentration does not vary signi®cantly from the initial equilibrium condition. In this case dm ˆ d…ln m†  dm m Therefore,  om o om ˆ os on on

 am ‡ b…m

…12†

s†

…13†

2.2. Barrier layer e€ect For the interconnect with barrier layers, assuming that another sink of vacancy exists in interconnect representing the vacancy ¯ux into the barrier layer, the two-dimensional problem may be reduced to a one-dimensional problem using appropriate boundary conditions. If the sink term is proportional to the vacancy concentration di€erence between interconnect and barB rier layer, c ˆ R0 …CV CV0 †, one obtains

Fig. 1. Schematic of the single-blocking boundary condition in the interconnect.

W. Wu, J.S. Yuan / Solid-State Electronics 45 (2001) 2011±2016

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2.3. Boundary conditions For the interconnect con®guration illustrated in Fig. 1, there is a blocking boundary at one end. It means that the vacancy ¯ux goes to zero at the blocking boundary x ˆ 0, that is JV …0; t† ˆ 0

or

om…0; s† ˆ am…0; s† on

…14†

while at the other end (x ˆ 1) the vacancy concentration remains ®xed at its initial zero-stress equilibrium value CV …l; t† ˆ CV0

or m…1; s† ˆ 1

…15†

or m…n; 0† ˆ 1

…16†

and CV …x; 0† ˆ CV0

Fig. 3. Reduced vacancy concentration versus reduced time for di€erent b.

In Fig. 2 the reduced vacancy concentration m versus reduced time s for di€erent values of a are shown. a is the ratio of electrical driving energy to thermal energy and related directly to Blech length [11]. a ˆ 1 means that the electrical driving energy is equal to the thermal energy. The reduced vacancy concentration presented here is at n ˆ 0 position. It is assumed that the vacancy concentration is the highest at n ˆ 0 than that at any other places because of the accumulation e€ect of elec-

tron wind force. From Fig. 2 the reduced vacancy concentration is higher for larger a values due to larger electrical driving force. Larger electrical driving force stems from higher current density. The larger the value of a, the larger the reduced vacancy concentration and the shorter the interconnect lifetime. In Fig. 3 the reduced vacancy concentration versus reduced time for di€erent values of b is shown. b is related to the barrier layer parameters. The normalized vacancy concentration for b > 0 (with the barrier layer e€ect) is much smaller than that at b ˆ 0 (without the barrier layer e€ect). This implies that the barrier layer improves the interconnect lifetime. The smaller normalized vacancy concentration, the smaller probability of wear out of the interconnect and thus the longer lifetime. Using m ˆ 3 as the criteria for the mean time to failure (MTTF), Fig. 4 shows the normalized MTTF versus b. The normalized term is de®ned here as the ratio of MTTF with barrier layer to that without barrier

Fig. 2. Reduced vacancy concentration versus reduced time for di€erent a.

Fig. 4. Normalized MTTF versus b.

3. Numerical solution Using the explicit technique for solving partial differential equation [10], a C ‡‡ program was written to solve the equations numerically. In the calculation the same initial vacancy concentration in metal line and barrier layer s ˆ 1 is used for simplicity. 3.1. DC case

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W. Wu, J.S. Yuan / Solid-State Electronics 45 (2001) 2011±2016

3.2. Pulsed DC case The copper interconnect under the pulse DC stress is also evaluated. The reduced vacancy concentration versus reduced time for DC and pulsed DC stress with and without barrier layer e€ect is displayed in Fig. 5. The duty factor r is equal to 0.5 in the pulsed DC case. It is interesting to note from Fig. 5 that the impact of barrier layer e€ect under the DC condition is much larger than that under the pulsed DC condition.

4. Experiments

Fig. 5. Reduced vacancy concentration versus reduced time for DC and pulsed DC stress with and without barrier layers.

layer. It is clear from Fig. 4 that the MMTF increases with an increase of b.

The arrangement of wafer level electromigration measurement is demonstrated in Fig. 6. The wafer temperature is adjusted via the hot chuck. The probe board set above the wafer can measure 60 interconnect samples at the same time. The measured signals from the probe board are sent to the DUT die wafer interface by

Fig. 6. Arrangement of wafer level electromigration measurement.

W. Wu, J.S. Yuan / Solid-State Electronics 45 (2001) 2011±2016

a general W/L interface. The measured data are then recorded in the MIRA CPU after passing through Data Acquisition Switch Unit (Agilent 34970A). After analyzed by the module integrated reliability analyzer, the resultant data are copied to the MIRA CPU. The electromigration test structure used is the ``NIST'' standard developed by Harry Scha€t at the National Institute of Standards and Technology. There are four terminals in the test structure and all of them have Kelvin connections. The Kelvin connections provide accurate resistance measurement. Four-point method is used in resistance measurement. Two of the four terminals detect current and the other two for voltage. The narrowest test line width depends on layout design rules. If line width is greater than the median grain size, electromigration proceeds via grain boundary di€usion. As line width gets narrower than median grain size, commonly referred to as bamboo grains, electromigration will not be dominated by grain boundary di€usion. When a test line is short, back di€usion of metal ions can slow down or stop electromigration [11]. To ensure that electromigration is being properly assessed, the test line must be suciently long to ensure that no or minimal back di€usion of ions will slow void growth. During the measurement, four curves can be monitored and recorded. The ®rst is obtained from Quickcheck. Quickcheck provides the feedback to identify whether the connections to the DUT are intact without to ramp the oven to temperature. It also serves to ®lter out those DUTs that do not belong to the population under test. After Quickcheck is done, the resistance data are viewed via the ramp resistance versus package number. Other three curves are recorded point by point during the electromigration stress. They are absolute currents versus time, relative degradation versus time, and Lognormal distribution. The relative degradation is de®ned as the percentage of interconnect resistance to its initial resistance of interconnect line. For one interconnect line, the criterion of failure used in the experiment is 10% change from its initial resistance. The Lognormal distribution is the percentage of number of failure interconnects to total number of measuring interconnects versus time. From the Lognormal distribution, one can determine the media time to failure of interconnects, which is the time corresponding to 50% failure percentage. The geometrical parameters of copper interconnect have the length of 800 lm, width of 0.24 lm, and thickness of 0.45 lm. The insulator thicknesses above and below interconnect are 0.4 and 0.65 lm, respectively. Using the thermal model derived in Ref. [22], the model predictions are compared with the experimental data as shown in Fig. 7. The lifetime decreases with current density due to Joule heating e€ect. The agreement between the model predictions and experiments is very good.

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Fig. 7. MTTF versus current density for Cu interconnects at T ˆ 295°C.

5. Summary Modeling of electromigration lifetime considering the copper interconnect barrier layer e€ect is developed. The simulation results suggest that the barrier layer improves the copper interconnect lifetime. It is interesting to note that the improvement of lifetime using the barrier layer is larger under the DC stress than that under the pulsed DC stress. The MTTF decreases with an increase of current density due to Joule heating. Good agreement between the model predictions and experiments is obtained. Acknowledgements The authors are thankful for Dr. S.H. Kang at Agere Systems in Orlando for his assistance for the electromigration measurements. References [1] Lane M, Dauskardt RH. Adhesion and reliability of copper interconnects with Ta and TaN barrier layers. J Mater Res 2000;15(1):203. [2] Rosenberg R, Ohring M. Void formation and growth during electromigration in thin ®lms. J Appl Phys 1971;42(13):5671. [3] Shatzkes M, LIoyd JR. A model for conductor failure considering di€usion concurrently with electromigration resulting in a current exponent of 2. J Appl Phys 1986;59(11):3890. [4] Clement JJ, LIoyd JR. Numerical investigations of the electromigration boundary value problem. J Appl Phys 1992;71(4):1729. [5] Clement JJ. Vacancy supersaturation model for electromigration failure under dc and pulsed dc stress. J Appl Phys 1992;71(9):4264.

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