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Copper phthalocyanine based vertical organic field effect transistor with naturally patterned tin intermediate grid electrode
Organic Electronics 27 (2015) 155e159
Contents lists available at ScienceDirect
Organic Electronics journal homepage: www.elsevier.com/locate/orgel
Copper phthalocyanine based vertical organic field effect transistor with naturally patterned tin intermediate grid electrode Adan Kvitschal, Isidro Cruz-Cruz, Ivo A. Hümmelgen* , Caixa Postal 19044, 81531-980, Curitiba, PR, Brazil Departamento de Física, Universidade Federal do Parana
a r t i c l e i n f o
a b s t r a c t
Article history: Received 17 June 2015 Received in revised form 13 August 2015 Accepted 8 September 2015 Available online xxx
We report on low voltage vertical organic field effect transistors using crosslinked poly(vinyl alcohol) (crPVA) as gate insulator and copper phthalocyanine (CuPc) as channel semiconductor. Al is used as gate and drain electrode. Sn thin films deposited under proper conditions are used as intermediate grid electrode (source), since the Sn film morphology simultaneously shows pinholes and lateral intergrain connectivity, allowing in-plane charge transport. Our Al/cr-PVA/Sn/CuPc/Al VOFET operates at low voltages, presents specific transconductance of ~0.45 S m2 and a linear source-drain current on gate voltage dependence. © 2015 Elsevier B.V. All rights reserved.
Keywords: Vertical field effect transistor Vertical organic transistor Copper phthalocyanine Poly(vinyl alcohol)
1. Introduction The application of organic semiconductors in planar architecture organic field-effect transistors (OFETs) [1] frequently leads to performance limitations as low output current, high operation voltage and low operational frequency. These constraints are mainly imposed by the low charge carrier mobility usually found in organic semiconductors and to particularities of the OFET channel geometry, which implies in long paths for charge carriers flowing from source to drain. Efforts were made by several research groups to overcome these difficulties, e. g., by developing organic transistors in vertical architectures [2e11], also including the use of phthalocyanines [12,13]. One of these vertical architecture devices, the Vertical Organic Field-Effect Transistor (VOFET), has a structure that provides a short channel-length path (as thick as the channel semiconductor film thickness) between the source and drain electrode and a channel with large cross section area, consequently fulfilling the basic conditions for lower operation voltages and higher output currents. In the VOFETs, gate electrode, insulator layer, intermediate electrode, semiconducting layer and top electrode are vertically stacked (see Fig. 1) and the active area S corresponds to the area of superposition of the electrodes. One of the key elements of these * Corresponding author. E-mail address: iah@fisica.ufpr.br (I.A. Hümmelgen). http://dx.doi.org/10.1016/j.orgel.2015.09.010 1566-1199/© 2015 Elsevier B.V. All rights reserved.
devices is the intermediate electrode that must be simultaneously permeable to the electric field and present a high enough in-plane conductivity to allow lateral connections without significant voltage drop along current paths due to in-plane film resistance. The use of an ultra-thin metallic layer deposited through evaporation is one alternative that may fulfil these requirements [14]. Additionally, Rossi et al. [7] and Seidel et al. [8] have shown that the intermediate electrode resistance can be minimized by using additional metallic or polymeric layers, respectively. There are also strategies to produce electrodes with controlled permeability like the use of sphere-lithography [15e17], co-deposition of metal and organic molecules [18], atomic layer deposition assisted nanoimprint lithography [19], random network of metallic nanowires [20], C60-graphene vertical heterostructures [21] or use of blockcopolymer templates [9] to obtain improved ON/OFF ratio and lower operation voltage. However, these strategies may require more complex device production steps, leading to a consequent cost rise and eliminating one of the potential advantages of the VOFETs. In this work we report on a VOFET prepared using a Sn single layer as intermediate electrode in one-step deposition process. The use of Sn, when the optimal deposition conditions are used, simplifies the intermediate electrode preparation procedure due to the characteristics of grain growth of this material, without need of additional structuring.
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Fig. 1. Device structure of Al/cr-PVA/Sn/CuPc/Al VOFET with Sn intermediate grid electrode. The Al/CuPc layers on the top of the device are shown separately, for clarity.
2. Experimental details The devices were prepared depositing an 80 nm thick Al electrode layer (the gate) by evaporation onto previously chemically cleaned glass substrate. In the sequence, the gate insulator was prepared depositing poly(vinyl alcohol), PVA, supplied by SigmaeAldrich (130 kDa), used without further purification. The PVA solution was prepared as described in Ref. [22], dissolving 60 mg/mL PVA in ultrapure deionized water (resistivity > 18.2 MU/cm). The preparation of the cross-linked PVA (cr-PVA) films was made adding 25% w/w ammonium dichromate (AD) to the PVA solution [19]. In the sequence, an AD:PVA layer was deposited by spin coating 65 mL AD:PVA solution at 4000 rpm. The cross-linking of the PVA was achieved via 10 min UV treatment (wavelength of 365 nm, 8 W), resulting a ~350 nm thick cross-linked PVA (cr-PVA) insulating layer. The intermediate electrode (Sn) was deposited maintaining the substrate at room temperature with typical average thicknesses of 40 nm. Several evaporation rates and distances between substrate and evaporation source were tested for this step. In the sequence, we evaporated a 80 nm thick Copper Phthalocyanine (CuPc), supplied by SigmaeAldrich and used as received. Finally, an 80 nm thick Al layer was deposited on top of the CuPc as the top electrode. The final device structure scheme can be seen in Fig. 1. The active area of the transistor, determined by the region where gate, source and drain overlap, is S ¼ 4 mm2. In all cases the evaporated layer geometry was controlled using shadow masks whereas material deposition was monitored using a quartz oscillator. All evaporations were made at a base pressure of 5 106 torr. Film thickness was measured with a Brucker DextakXT surface profiler. In case of the devices whose electrical characteristics are shown in the sequence the Sn evaporation rate and deposition time parameters were adjusted to obtain a resistance of 100 U/sq. Transistor electrical characteristics were determined using a Keithley 2602 dual-source meter. The surface morphology was characterized by using a Shimadzu SPM-9500J3 atomic force microscope (AFM), operating in tapping mode.
3. Results and discussion As mentioned before, one of the key elements in VOFETs is the intermediate electrode, which must be permeable to the electric field to allow affecting the channel current through the action of the gate voltage. The permeability, however, must occur without a severe increase in the in-plane resistivity of the intermediate electrode film. This condition is imposed because in a VOFET the intermediate electrode acts as injection (or in some cases as
collection) electrode and must be able to transport current so efficiently as the top electrode, without suffering too high voltage drop along the film. Voltage drop would lead to an undesired position dependent potential difference between source and drain electrodes and non-uniform source-drain current density distribution. This aspect is relevant because VOFETs could be potentially applied in connection with organic light-emitting pixels where uniformity of current density and consequently of light emission in the pixel area is necessary. The morphology of Sn thin films on cr-PVA is dependent of the particular process parameters used to obtain it (See supplementary material). For our target application, VOFETs, it is important to obtain high lateral connectivity of the grains, in order to have easy in-plane charge transport and consequently, low resistance. Both conditions were obtained placing the sample at a distance of 16 cm from the crucible at evaporation rate of 3 Å/s, with the simultaneous presence of pinholes and enough inter grain connectivity (Fig. 2). It was confirmed by a better performance in VOFETs, as will be discussed later. In case of Fig. 2(a) the deposition was stopped when the resistance of the film started to decrease, whereas in case of Fig. 2(b) the deposition was longer, stopped after the transition to low resistance occurred. Longer percolation paths of connected grains without clear border between them can be observed in case of Fig. 2(b), differently than in Fig. 2(a). But even in Fig. 2(b) free space between some of the grains (pinholes) is still observable. It is important to mention that this was the unique investigated preparation condition which resulted devices with current modulation capability, as detailed in the sequence. Sn thin film grown on Si as intermediate electrode was previously reported [23] in the case of permeable-base transistors (PBTs), showing high permeability to the electric field. In PBTs the permeability of a metallic layer to the electric field can be directly inferred and quantified [24]. PBTs differ from the VOFETs because injection and collection electrodes are the external ones (the base grid is the intermediate electrode, like in triode architecture) and instead of semiconductor and insulator layers as in VOFETs, PBTs use only semiconductor layers between electrodes. The electrical characteristics of the Al/cr-PVA/Sn/CuPc/Al transistor with Sn deposited with crucible-substrate distance of 16 cm and evaporation rate of 3 Å/s (corresponding to Fig. 2) and 80 nm thick CuPc layer are shown in Fig. 3. The polarization condition (Al drain and gate are negatively biased relative to the Sn source grid) corresponds to the intermediate Sn contact acting as hole source (electron drain) and the Al top contact as hole drain (electron source). Considering the work function values of Al (4.3 eV) and Sn (~4.4 eV) [25], the highest occupied molecular orbital (HOMO) energy (~-5.2 eV) and lowest unoccupied molecular orbital (LUMO) energy (~-3.6 eV) of CuPc [26e28] and assuming absence of interface polarization, ambipolar transport through the CuPc film is in principle possible due to similar injection barrier heights for both charge carriers at both electrodes (see Fig. 3). Mobility values for both electron and holes determined in CuPc field-effect transistors are available and widely spread [29e31], the same happening with mobility values measured applying other techniques [32,33]. Phthalocyanine, however, is frequently used as hole injection or transport layer [34], in part because phthalocyanines behave as ptype material due to absorbed oxygen which acts as an acceptor level in the band gap [35]. For this reason, it is more probable that the hole transport is preponderant in our devices when the drain is negatively biased. At higher voltages, however, due to the field enhancement near to the minority carrier (electrons) injection electrode, bipolar injection is also expected to occur [36]. In Fig. 4(a) and (b) we show the drain IDS and gate IGS currents expressed in the corresponding current densities J for drain positively biased, respectively. As shown in Fig. 4(b), the leakage current
A. Kvitschal et al. / Organic Electronics 27 (2015) 155e159
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Fig. 2. AFM image of the Sn thin film with a thickness (a): slightly lower than the threshold for in-plane conductivity and; (b): with a thickness slightly above the threshold for inplane conductivity, optimized for application in vertical field-effect transistors.
(IGS) is significantly lower than IDS, which is a requirement for a transistor effectively working as a three terminal device, because this device effectively works as a diode stacked onto a capacitor, both having in common the intermediate grid electrode. In Fig. 4(a) we show the output characteristics IDS(VDS) of the transistor for different VGS. As can be clearly seen, VGS modulates IDS, JDS being in the Am2 range. Compared to previous results obtained using devices constructed with Al as intermediate electrode and C60 as semiconductor layer [7], the output current of the Al/cr-PVA/Sn/CuPc/Al VOFETs shows an increase by one order of magnitude for the same voltage range and a very low off-state current IDS (VGS ¼ 0), attributed to the high energy barrier at the Sn/CuPc interface. The latter point is important because it results higher modulation capability, representing a substantial performance enhancement. The capability to drive higher current densities is especially demanded in low size high current devices, like organic lightemitting pixels in a display. The higher modulation capability can also be inferred from the transconductance gm ≡vIDS= , which is vVGS presented in Fig. 5 in the form of specific transconductance gmc ≡ gm/S. It is important to observe that gm achieves a plateau for VGS < 4 V, differently than in devices constructed with Al as intermediate electrode and C60 as semiconductor layer [7]. This
plateau corresponds to the voltage range showing linear transfer characteristics. In our transistors the dependence of the drain current on drain voltage for VGS ¼ 0 (OFF state) is similar to the gate leakage current. In the ON state (VGS s 0) the drain current follows exponential dependence on applied voltage above the current threshold (see Fig. 6), which is characteristic for thermionic emission process. The ON condition of the transistor is obtained by simultaneously applying a negative potential to the gate and to the drain, with respect to the source. The exponential behaviour observed in the output characteristic is evidence that the total current circulating through the channel is limited by an interface process, possibly due to the barrier present between source electrode and semiconductor, since it can be modulated by the gate potential. The data can be compared to classic solid state equations for metal-semiconductor junctions [37], ignoring the presence of barrier lowering due to image charge effects (Schottky effect) and including a non-ideality factor that accounts for the deviation of the q/kBT slope (approximately 60 mV per decade at room temperature).
qVDS 1 IDS ¼ I0 exp hkB T
(1)
where I0 is the reverse or saturation current, q is the fundamental charge, kB is the Boltzmann constant, T is the absolute temperature, and h is the non-ideality factor or slope factor. The I0 term can be calculated by using Eq. (2) that assumes ideal thermionic emission of carriers possessing energy greater than the interface barrier potential.
qf I0 ¼ SA0 T 2 exp B kB T
Fig. 3. Energy scheme of the Al/cr-PVA/Sn/CuPc/Al VOFET.
(2)
where A0 is the Richardson constant and fB is the potential barrier value. Equation parameters were extracted by fitting the linear segment of the monolog representation of the experimental data for each gate potential above the threshold drain-source voltage (Fig. 6), where the slope is equal to the q/hkBT term and the extrapolated crossing of the y-axis is equal to the I0 term. The slope factor and barrier height for each case were calculated assuming room temperature and using A0 ¼ 1.20173 106 Am2 K2, the results are listed in Table 1. The slope factor is usually between 1 and 2 for commercial silicon junctions, but our devices have shown much larger values. This phenomenon indicates that there is a strong presence of effects like carrier recombination, interface
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Fig. 5. Specific transconductance of the Al/cr-PVA/Sn/CuPc/Al VOFET at VDS ¼ 5 V.
Fig. 6. Output characteristics of the of the Al/cr-PVA/Sn/CuPc/Al VOFET, showing the fitted linear behaviour in the monolog graph.
authors use patterned electrodes with controlled perforations whereas in our case, the pinholes naturally occur in the intermediate electrode, but the conclusions apply equally. The injection limited mechanism dominance at moderately low VDS is expected before the complete formation of the vertical channels in the pinholes, because except in this region, the charge carrier injection into the CuPc is limited by the high energy barrier at the interface, in our case of ca. 0.7e0.9 eV. Like in our case, they predict increase of the source-drain current when drain and gate polarity with respect to source is the same. Fig. 4. (a) Output characteristics; (b) gate leakage current and; (c) transfer characteristics (VDS ¼ 5 V) of the Al/cr-PVA/Sn/CuPc/Al VOFET. VT is the threshold voltage.
polarization and/or quantum effects [38]. Modelling of the slope factor variation with respect to gate potential is beyond the scope of this work, but it is worth noting that similar variation with respect to temperature has been observed in rectifying devices with a large density of interface states [39]. Ben-Sasson and Tessler [40] proposed a model that describes the electrical behaviour of VOFETs in which the current modulation characteristics are obtained through the formation of virtual contacts at the intermediate electrode pinholes under gate bias, which lead to the formation of vertical channels under drain bias. These
4. Conclusion In summary, we investigated how to properly prepare tin grids for the preparation of VOFETs in which the Sn grid concomitantly
Table 1 Numerical values calculated fitting Eqs. (1) and (2) to the data of Fig. 6. VGS [V] 2 4 6
I0/S [Am2] 5
9.3 10 9.1 103 8.1 102
h
4B [mV]
35.2 57.7 76.6
925 752 698
A. Kvitschal et al. / Organic Electronics 27 (2015) 155e159
presents permeability to the electric field and in plane conductance. Applying the optimized parameters we demonstrated VOFET operation at low voltage using CuPc as semiconductor material. The advantage of these devices is the simplicity of the intermediate electrode preparation, which is a single metal evaporation step that does not require more sophisticated electrode patterning strategies, as well as the compatibility with flexible substrates, due to the polymeric gate insulator, cr-PVA. Because of the high energy barrier at the Sn/CuPc interface, these devices show low off-state current. Acknowledgements The authors thank CAPES and CNPq for research grants and fellowships and CME-UFPR for AFM facilities. Appendix A. Supplementary data Supplementary data related to this article can be found at http:// dx.doi.org/10.1016/j.orgel.2015.09.010. References [1] G. Horowitz, F. Deloffre, F. Garnier, R. Hajlaoui, M. Hmyene, A. Yassar, Synth. Met. 54 (1993) 435. [2] Y. Yang, A. Heeger, Nature 372 (1994) 344; a J. McElvain, M. Keshavarz, H. Wang, F. Wudl, A. J. Heeger, J. Appl. Phys. 81 (1997) 6468. [3] L. Ma, Y. Yang, Appl. Phys. Lett. 85 (2004) 5084. [4] S. Fujimoto, K. Nakayama, M. Yokoyama, Appl. Phys. Lett. 87 (2005) 133503. [5] Y.C. Chao, S.L. Yang, H.F. Meng, S.F. Horng, Appl. Phys. Lett. 87 (2005) 253508. [6] J.P.M. Serbena, J.Y. Huang, D. Ma, Z.Y. Wang, I.A. Hümmelgen, Org. Electron. 10 (2009) 357. [7] L. Rossi, K.F. Seidel, W.S. Machado, I.A. Hümmelgen, J. Appl. Phys. 110 (2011) 94508. [8] K.F. Seidel, L. Rossi, R.M.Q. Mello, I.A. Hümmelgen, J. Mater. Sci. Mater. Electron. 24 (2013) 1052. [9] A.J. Ben-Sasson, E. Avnon, E. Ploshnik, O. Globerman, R. Shenhar, G.L. Frey, N. Tessler, Appl. Phys. Lett. 95 (2009) 213301. [10] A.C.B. Tavares, J.P.M. Serbena, I.A. Hümmelgen, M.S. Meruvia, Org. Electron. 15 (2014) 738.
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[11] J.H. Kim, H. Yu, R. Liu, D.Y. Kim, F. So, Small 10 (2014) 3650; a H. Yu, J. J. Kim, W. Chen, D. Y. Kim, J. Guo, F. So, Adv. Funct. Mater. 24 (2014) 6056. [12] K. Kudo, D.X. Wang, M. Iizuka, S. Kuniyoshi, K. Tanaka, Thin Solid Films 331 (1998) 51. [13] K. Kudo, M. Iizuka, S. Kuniyoshi, K. Tanaka, Thin Solid Films 393 (2001) 362. [14] A. Fischer, R. Scholz, K. Leo, B. Lüssem, Appl. Phys. Lett. 101 (2012) 213303. [15] Y.C. Chao, H.F. Meng, Chiao Tung, S.F. Horng, Appl. Phys. Lett. 88 (2006) 223510. [16] L. Rossi, J.P.M. Serbena, M.S. Meruvia, I.A. Hümmelgen, E.M. Sartori, C.K. Saul, Z.Y. Wang, J. Nanosci. Nanotechno. 10 (2010) 2389. [17] K. Fujimoto, T. Hiroi, K. Kudo, M. Nakamura, Adv. Mater. 19 (2007) 525. [18] K. Zhao, J.C. Deng, X.M. Wu, X.M. Cheng, J. Wei, S.G. Yin, Org. Electron. 12 (2011) 1003. [19] Y. Hsu, X. Fang, L.A. Wang, H.W. Zan, H.F. Meng, S.H. Yang, Org. Electron. 15 (2014) 3609. [20] A.J. Ben-Sasson, D. Azulai, H. Gilon, A. Facchetti, G. Markovich, N. Tessler, ACS Appl. Mater. Interfaces 7 (2015) 2149. [21] K. Kim, T.H. Lee, E.J.G. Santos, P.S. Jo, A. Salleo, Y. Nishi, Z. Bao, ACS Nano 9 (2015) 5922. [22] W.S. Machado, I.A. Hümmelgen, IEEE Trans. Electron. Dev. 59 (2012) 1529. [23] J.P.M. Serbena, I.A. Hümmelgen, T. Hadizad, Z.Y. Wang, Small 2 (2006) 372. [24] M.S. Meruvia, I.A. Hümmelgen, Adv. Funct. Mater. 16 (2006) 459. [25] D.R. Lide, CRC Handbook of Chemistry and Physics, CRC, Boca Raton, 1995. [26] C.S. Xia, K. Seki, H. Inokuchi, S. Zurong, Q. Renyuan, Bull. Chem. Soc. Jpn. 56 (1983) 2565. [27] I.G. Hill, A. Kahn, J. Appl. Phys. 84 (1998) 5583. [28] L. Zhu, H. Tang, Y. Harima, Y. Kunugi, K. Yamashita, J. Ohshita, A. Kunai, Thin Solid Films 396 (2001) 214. [29] R.W.I. de Boer, A.F. Stassen, M.F. Craucin, C.L. Mulder, A. Molinari, S. Rogge, A.F. Morpugo, Appl. Phys. Lett. 86 (2005) 262109. [30] M. Kraus, S. Richter, A. Opitz, W. Brütting, S. Haas, T. Hasegawa, A. Hinderhofer, F. Schreiber, J. Appl. Phys. 107 (2010) 094503. [31] A. Opitz, M. Bronner, W. Brütting, J. Phys. C Conf. Ser. 100 (2008) 082043. [32] R.D. Gould, Coord. Chem. Rev. 156 (1996) 237. [33] A.K. Hassan, R.D. Gould, J. Phys. D. Appl. Phys. 22 (1989) 1162. [34] K.S. Yook, S.O. Jeon, C.W. Joo, J.Y. Lee, J. Ind. Eng. Chem. 15 (2009) 907. [35] H.S. Soliman, A.M.A. El-Barry, N.M. Khosifan, M.M. El Nahass, Eur. Phys. J. Appl. Phys. 37 (2007) 1. [36] M. Koehler, M.G.E. da Luz, I.A. Hümmelgen, J. Phys. D. Appl. Phys. 33 (2000) 2096. [37] S.M. Sze, Physics of Semiconductor Devices, Wiley, 1981. [38] S. Rajaputra, S. Vallurupalli, V.P. Singh, J. Mater. Sci. Mater. Electron. 18 (2007) 1147. [39] K. Alfaramawi, Optoelectron. Adv. Mater. Rapid Commun. 2 (2008) 763. [40] A.J. Ben-Sasson, N. Tessler, J. Appl. Phys. 110 (2011) 044501.
Contents lists available at ScienceDirect
Organic Electronics journal homepage: www.elsevier.com/locate/orgel
Copper phthalocyanine based vertical organic field effect transistor with naturally patterned tin intermediate grid electrode Adan Kvitschal, Isidro Cruz-Cruz, Ivo A. Hümmelgen* , Caixa Postal 19044, 81531-980, Curitiba, PR, Brazil Departamento de Física, Universidade Federal do Parana
a r t i c l e i n f o
a b s t r a c t
Article history: Received 17 June 2015 Received in revised form 13 August 2015 Accepted 8 September 2015 Available online xxx
We report on low voltage vertical organic field effect transistors using crosslinked poly(vinyl alcohol) (crPVA) as gate insulator and copper phthalocyanine (CuPc) as channel semiconductor. Al is used as gate and drain electrode. Sn thin films deposited under proper conditions are used as intermediate grid electrode (source), since the Sn film morphology simultaneously shows pinholes and lateral intergrain connectivity, allowing in-plane charge transport. Our Al/cr-PVA/Sn/CuPc/Al VOFET operates at low voltages, presents specific transconductance of ~0.45 S m2 and a linear source-drain current on gate voltage dependence. © 2015 Elsevier B.V. All rights reserved.
Keywords: Vertical field effect transistor Vertical organic transistor Copper phthalocyanine Poly(vinyl alcohol)
1. Introduction The application of organic semiconductors in planar architecture organic field-effect transistors (OFETs) [1] frequently leads to performance limitations as low output current, high operation voltage and low operational frequency. These constraints are mainly imposed by the low charge carrier mobility usually found in organic semiconductors and to particularities of the OFET channel geometry, which implies in long paths for charge carriers flowing from source to drain. Efforts were made by several research groups to overcome these difficulties, e. g., by developing organic transistors in vertical architectures [2e11], also including the use of phthalocyanines [12,13]. One of these vertical architecture devices, the Vertical Organic Field-Effect Transistor (VOFET), has a structure that provides a short channel-length path (as thick as the channel semiconductor film thickness) between the source and drain electrode and a channel with large cross section area, consequently fulfilling the basic conditions for lower operation voltages and higher output currents. In the VOFETs, gate electrode, insulator layer, intermediate electrode, semiconducting layer and top electrode are vertically stacked (see Fig. 1) and the active area S corresponds to the area of superposition of the electrodes. One of the key elements of these * Corresponding author. E-mail address: iah@fisica.ufpr.br (I.A. Hümmelgen). http://dx.doi.org/10.1016/j.orgel.2015.09.010 1566-1199/© 2015 Elsevier B.V. All rights reserved.
devices is the intermediate electrode that must be simultaneously permeable to the electric field and present a high enough in-plane conductivity to allow lateral connections without significant voltage drop along current paths due to in-plane film resistance. The use of an ultra-thin metallic layer deposited through evaporation is one alternative that may fulfil these requirements [14]. Additionally, Rossi et al. [7] and Seidel et al. [8] have shown that the intermediate electrode resistance can be minimized by using additional metallic or polymeric layers, respectively. There are also strategies to produce electrodes with controlled permeability like the use of sphere-lithography [15e17], co-deposition of metal and organic molecules [18], atomic layer deposition assisted nanoimprint lithography [19], random network of metallic nanowires [20], C60-graphene vertical heterostructures [21] or use of blockcopolymer templates [9] to obtain improved ON/OFF ratio and lower operation voltage. However, these strategies may require more complex device production steps, leading to a consequent cost rise and eliminating one of the potential advantages of the VOFETs. In this work we report on a VOFET prepared using a Sn single layer as intermediate electrode in one-step deposition process. The use of Sn, when the optimal deposition conditions are used, simplifies the intermediate electrode preparation procedure due to the characteristics of grain growth of this material, without need of additional structuring.
156
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Fig. 1. Device structure of Al/cr-PVA/Sn/CuPc/Al VOFET with Sn intermediate grid electrode. The Al/CuPc layers on the top of the device are shown separately, for clarity.
2. Experimental details The devices were prepared depositing an 80 nm thick Al electrode layer (the gate) by evaporation onto previously chemically cleaned glass substrate. In the sequence, the gate insulator was prepared depositing poly(vinyl alcohol), PVA, supplied by SigmaeAldrich (130 kDa), used without further purification. The PVA solution was prepared as described in Ref. [22], dissolving 60 mg/mL PVA in ultrapure deionized water (resistivity > 18.2 MU/cm). The preparation of the cross-linked PVA (cr-PVA) films was made adding 25% w/w ammonium dichromate (AD) to the PVA solution [19]. In the sequence, an AD:PVA layer was deposited by spin coating 65 mL AD:PVA solution at 4000 rpm. The cross-linking of the PVA was achieved via 10 min UV treatment (wavelength of 365 nm, 8 W), resulting a ~350 nm thick cross-linked PVA (cr-PVA) insulating layer. The intermediate electrode (Sn) was deposited maintaining the substrate at room temperature with typical average thicknesses of 40 nm. Several evaporation rates and distances between substrate and evaporation source were tested for this step. In the sequence, we evaporated a 80 nm thick Copper Phthalocyanine (CuPc), supplied by SigmaeAldrich and used as received. Finally, an 80 nm thick Al layer was deposited on top of the CuPc as the top electrode. The final device structure scheme can be seen in Fig. 1. The active area of the transistor, determined by the region where gate, source and drain overlap, is S ¼ 4 mm2. In all cases the evaporated layer geometry was controlled using shadow masks whereas material deposition was monitored using a quartz oscillator. All evaporations were made at a base pressure of 5 106 torr. Film thickness was measured with a Brucker DextakXT surface profiler. In case of the devices whose electrical characteristics are shown in the sequence the Sn evaporation rate and deposition time parameters were adjusted to obtain a resistance of 100 U/sq. Transistor electrical characteristics were determined using a Keithley 2602 dual-source meter. The surface morphology was characterized by using a Shimadzu SPM-9500J3 atomic force microscope (AFM), operating in tapping mode.
3. Results and discussion As mentioned before, one of the key elements in VOFETs is the intermediate electrode, which must be permeable to the electric field to allow affecting the channel current through the action of the gate voltage. The permeability, however, must occur without a severe increase in the in-plane resistivity of the intermediate electrode film. This condition is imposed because in a VOFET the intermediate electrode acts as injection (or in some cases as
collection) electrode and must be able to transport current so efficiently as the top electrode, without suffering too high voltage drop along the film. Voltage drop would lead to an undesired position dependent potential difference between source and drain electrodes and non-uniform source-drain current density distribution. This aspect is relevant because VOFETs could be potentially applied in connection with organic light-emitting pixels where uniformity of current density and consequently of light emission in the pixel area is necessary. The morphology of Sn thin films on cr-PVA is dependent of the particular process parameters used to obtain it (See supplementary material). For our target application, VOFETs, it is important to obtain high lateral connectivity of the grains, in order to have easy in-plane charge transport and consequently, low resistance. Both conditions were obtained placing the sample at a distance of 16 cm from the crucible at evaporation rate of 3 Å/s, with the simultaneous presence of pinholes and enough inter grain connectivity (Fig. 2). It was confirmed by a better performance in VOFETs, as will be discussed later. In case of Fig. 2(a) the deposition was stopped when the resistance of the film started to decrease, whereas in case of Fig. 2(b) the deposition was longer, stopped after the transition to low resistance occurred. Longer percolation paths of connected grains without clear border between them can be observed in case of Fig. 2(b), differently than in Fig. 2(a). But even in Fig. 2(b) free space between some of the grains (pinholes) is still observable. It is important to mention that this was the unique investigated preparation condition which resulted devices with current modulation capability, as detailed in the sequence. Sn thin film grown on Si as intermediate electrode was previously reported [23] in the case of permeable-base transistors (PBTs), showing high permeability to the electric field. In PBTs the permeability of a metallic layer to the electric field can be directly inferred and quantified [24]. PBTs differ from the VOFETs because injection and collection electrodes are the external ones (the base grid is the intermediate electrode, like in triode architecture) and instead of semiconductor and insulator layers as in VOFETs, PBTs use only semiconductor layers between electrodes. The electrical characteristics of the Al/cr-PVA/Sn/CuPc/Al transistor with Sn deposited with crucible-substrate distance of 16 cm and evaporation rate of 3 Å/s (corresponding to Fig. 2) and 80 nm thick CuPc layer are shown in Fig. 3. The polarization condition (Al drain and gate are negatively biased relative to the Sn source grid) corresponds to the intermediate Sn contact acting as hole source (electron drain) and the Al top contact as hole drain (electron source). Considering the work function values of Al (4.3 eV) and Sn (~4.4 eV) [25], the highest occupied molecular orbital (HOMO) energy (~-5.2 eV) and lowest unoccupied molecular orbital (LUMO) energy (~-3.6 eV) of CuPc [26e28] and assuming absence of interface polarization, ambipolar transport through the CuPc film is in principle possible due to similar injection barrier heights for both charge carriers at both electrodes (see Fig. 3). Mobility values for both electron and holes determined in CuPc field-effect transistors are available and widely spread [29e31], the same happening with mobility values measured applying other techniques [32,33]. Phthalocyanine, however, is frequently used as hole injection or transport layer [34], in part because phthalocyanines behave as ptype material due to absorbed oxygen which acts as an acceptor level in the band gap [35]. For this reason, it is more probable that the hole transport is preponderant in our devices when the drain is negatively biased. At higher voltages, however, due to the field enhancement near to the minority carrier (electrons) injection electrode, bipolar injection is also expected to occur [36]. In Fig. 4(a) and (b) we show the drain IDS and gate IGS currents expressed in the corresponding current densities J for drain positively biased, respectively. As shown in Fig. 4(b), the leakage current
A. Kvitschal et al. / Organic Electronics 27 (2015) 155e159
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Fig. 2. AFM image of the Sn thin film with a thickness (a): slightly lower than the threshold for in-plane conductivity and; (b): with a thickness slightly above the threshold for inplane conductivity, optimized for application in vertical field-effect transistors.
(IGS) is significantly lower than IDS, which is a requirement for a transistor effectively working as a three terminal device, because this device effectively works as a diode stacked onto a capacitor, both having in common the intermediate grid electrode. In Fig. 4(a) we show the output characteristics IDS(VDS) of the transistor for different VGS. As can be clearly seen, VGS modulates IDS, JDS being in the Am2 range. Compared to previous results obtained using devices constructed with Al as intermediate electrode and C60 as semiconductor layer [7], the output current of the Al/cr-PVA/Sn/CuPc/Al VOFETs shows an increase by one order of magnitude for the same voltage range and a very low off-state current IDS (VGS ¼ 0), attributed to the high energy barrier at the Sn/CuPc interface. The latter point is important because it results higher modulation capability, representing a substantial performance enhancement. The capability to drive higher current densities is especially demanded in low size high current devices, like organic lightemitting pixels in a display. The higher modulation capability can also be inferred from the transconductance gm ≡vIDS= , which is vVGS presented in Fig. 5 in the form of specific transconductance gmc ≡ gm/S. It is important to observe that gm achieves a plateau for VGS < 4 V, differently than in devices constructed with Al as intermediate electrode and C60 as semiconductor layer [7]. This
plateau corresponds to the voltage range showing linear transfer characteristics. In our transistors the dependence of the drain current on drain voltage for VGS ¼ 0 (OFF state) is similar to the gate leakage current. In the ON state (VGS s 0) the drain current follows exponential dependence on applied voltage above the current threshold (see Fig. 6), which is characteristic for thermionic emission process. The ON condition of the transistor is obtained by simultaneously applying a negative potential to the gate and to the drain, with respect to the source. The exponential behaviour observed in the output characteristic is evidence that the total current circulating through the channel is limited by an interface process, possibly due to the barrier present between source electrode and semiconductor, since it can be modulated by the gate potential. The data can be compared to classic solid state equations for metal-semiconductor junctions [37], ignoring the presence of barrier lowering due to image charge effects (Schottky effect) and including a non-ideality factor that accounts for the deviation of the q/kBT slope (approximately 60 mV per decade at room temperature).
qVDS 1 IDS ¼ I0 exp hkB T
(1)
where I0 is the reverse or saturation current, q is the fundamental charge, kB is the Boltzmann constant, T is the absolute temperature, and h is the non-ideality factor or slope factor. The I0 term can be calculated by using Eq. (2) that assumes ideal thermionic emission of carriers possessing energy greater than the interface barrier potential.
qf I0 ¼ SA0 T 2 exp B kB T
Fig. 3. Energy scheme of the Al/cr-PVA/Sn/CuPc/Al VOFET.
(2)
where A0 is the Richardson constant and fB is the potential barrier value. Equation parameters were extracted by fitting the linear segment of the monolog representation of the experimental data for each gate potential above the threshold drain-source voltage (Fig. 6), where the slope is equal to the q/hkBT term and the extrapolated crossing of the y-axis is equal to the I0 term. The slope factor and barrier height for each case were calculated assuming room temperature and using A0 ¼ 1.20173 106 Am2 K2, the results are listed in Table 1. The slope factor is usually between 1 and 2 for commercial silicon junctions, but our devices have shown much larger values. This phenomenon indicates that there is a strong presence of effects like carrier recombination, interface
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Fig. 5. Specific transconductance of the Al/cr-PVA/Sn/CuPc/Al VOFET at VDS ¼ 5 V.
Fig. 6. Output characteristics of the of the Al/cr-PVA/Sn/CuPc/Al VOFET, showing the fitted linear behaviour in the monolog graph.
authors use patterned electrodes with controlled perforations whereas in our case, the pinholes naturally occur in the intermediate electrode, but the conclusions apply equally. The injection limited mechanism dominance at moderately low VDS is expected before the complete formation of the vertical channels in the pinholes, because except in this region, the charge carrier injection into the CuPc is limited by the high energy barrier at the interface, in our case of ca. 0.7e0.9 eV. Like in our case, they predict increase of the source-drain current when drain and gate polarity with respect to source is the same. Fig. 4. (a) Output characteristics; (b) gate leakage current and; (c) transfer characteristics (VDS ¼ 5 V) of the Al/cr-PVA/Sn/CuPc/Al VOFET. VT is the threshold voltage.
polarization and/or quantum effects [38]. Modelling of the slope factor variation with respect to gate potential is beyond the scope of this work, but it is worth noting that similar variation with respect to temperature has been observed in rectifying devices with a large density of interface states [39]. Ben-Sasson and Tessler [40] proposed a model that describes the electrical behaviour of VOFETs in which the current modulation characteristics are obtained through the formation of virtual contacts at the intermediate electrode pinholes under gate bias, which lead to the formation of vertical channels under drain bias. These
4. Conclusion In summary, we investigated how to properly prepare tin grids for the preparation of VOFETs in which the Sn grid concomitantly
Table 1 Numerical values calculated fitting Eqs. (1) and (2) to the data of Fig. 6. VGS [V] 2 4 6
I0/S [Am2] 5
9.3 10 9.1 103 8.1 102
h
4B [mV]
35.2 57.7 76.6
925 752 698
A. Kvitschal et al. / Organic Electronics 27 (2015) 155e159
presents permeability to the electric field and in plane conductance. Applying the optimized parameters we demonstrated VOFET operation at low voltage using CuPc as semiconductor material. The advantage of these devices is the simplicity of the intermediate electrode preparation, which is a single metal evaporation step that does not require more sophisticated electrode patterning strategies, as well as the compatibility with flexible substrates, due to the polymeric gate insulator, cr-PVA. Because of the high energy barrier at the Sn/CuPc interface, these devices show low off-state current. Acknowledgements The authors thank CAPES and CNPq for research grants and fellowships and CME-UFPR for AFM facilities. Appendix A. Supplementary data Supplementary data related to this article can be found at http:// dx.doi.org/10.1016/j.orgel.2015.09.010. References [1] G. Horowitz, F. Deloffre, F. Garnier, R. Hajlaoui, M. Hmyene, A. Yassar, Synth. Met. 54 (1993) 435. [2] Y. Yang, A. Heeger, Nature 372 (1994) 344; a J. McElvain, M. Keshavarz, H. Wang, F. Wudl, A. J. Heeger, J. Appl. Phys. 81 (1997) 6468. [3] L. Ma, Y. Yang, Appl. Phys. Lett. 85 (2004) 5084. [4] S. Fujimoto, K. Nakayama, M. Yokoyama, Appl. Phys. Lett. 87 (2005) 133503. [5] Y.C. Chao, S.L. Yang, H.F. Meng, S.F. Horng, Appl. Phys. Lett. 87 (2005) 253508. [6] J.P.M. Serbena, J.Y. Huang, D. Ma, Z.Y. Wang, I.A. Hümmelgen, Org. Electron. 10 (2009) 357. [7] L. Rossi, K.F. Seidel, W.S. Machado, I.A. Hümmelgen, J. Appl. Phys. 110 (2011) 94508. [8] K.F. Seidel, L. Rossi, R.M.Q. Mello, I.A. Hümmelgen, J. Mater. Sci. Mater. Electron. 24 (2013) 1052. [9] A.J. Ben-Sasson, E. Avnon, E. Ploshnik, O. Globerman, R. Shenhar, G.L. Frey, N. Tessler, Appl. Phys. Lett. 95 (2009) 213301. [10] A.C.B. Tavares, J.P.M. Serbena, I.A. Hümmelgen, M.S. Meruvia, Org. Electron. 15 (2014) 738.
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