Covering and connectivity constraints in loop-based formulation of material flow network design in facility layout

Accepted Manuscript

Covering and Connectivity Constraints in Loop-Based Formulation of Material Flow Network Design in Facility Layout Ardavan Asef-Vaziri, Morteza Kazemi PII: DOI: Reference:

S0377-2217(17)30646-X 10.1016/j.ejor.2017.07.019 EOR 14569

To appear in:

European Journal of Operational Research

Received date: Revised date: Accepted date:

21 January 2016 30 April 2017 2 July 2017

Please cite this article as: Ardavan Asef-Vaziri, Morteza Kazemi, Covering and Connectivity Constraints in Loop-Based Formulation of Material Flow Network Design in Facility Layout, European Journal of Operational Research (2017), doi: 10.1016/j.ejor.2017.07.019

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Highlights • A comprehensive review on loop-based material flow system design. • Review and unify covering constraints in Loop formulation. • Provide new insight into connectivity constraints, and report new findings.

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• Report extensive computational results on the properties discussed.

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Covering and Connectivity Constraints in Loop-Based Formulation of Material Flow Network Design in Facility Layout

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Ardavan Asef-Vaziri ** Corresponding Author Department of Systems and Operations Management College of Business and Economics, California State University, Northridge 18111 Nordhoff Street, Northridge, CA 91330–8245, USA Tel: 818-677-3637, FAX: 818-677-6079, email: [email protected] Morteza Kazemi Department of Industrial Engineering Shiraz University of Technology, Shiraz, Iran email: [email protected]

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August 11, 2017 Abstract

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The shortest loop covering at least one edge of each workcenter in a manufacturing facility layout is an instance of the generalized traveling salesman problem. The optimal solution to this problem is a promising design for non-vehicle-based material handling, typical of most types of conveyors and power-and-free systems, where the length of the path is the main driver of the total investment costs. The loop formulation is usually embedded within a larger problem of the concurrent design of the loop and the input/output stations for vehicle-based material handling typical of automatically guided vehicles and autonomous delivery robots. In these systems, it is not the length, but the total flow of the loaded and empty vehicles that drives the objective function. It has been shown that the shortest loop provides an effective heuristic scheme to achieve prosperous and robust solutions for the concurrent design of the loop and input/output stations. We review and compare covering constraints formulations, provide new insight into connectivity constraints, improve the model formulation and its solution procedure, and report computational results.

Key Words and Phrases : block layout shortest loop, loop based material handling, generalized traveling salesman problem, covering constraints, automatic guided vehicle systems.

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1

Introduction

A block layout is a graphical representation of a set of rectilinear, but not necessarily convex, polygons each representing a cell (e.g., a manufacturing or service workcenter, a department, or a group of machines, etc.). Since Montreuil (1990), there has been a trend towards

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integrating the block layout with a material flow network. Due to the complexity of the concurrent design of the two components, the design of the material flow network commonly follows that of the block layout.

One measure of effectiveness when implementing non-vehicle-based material handling systems is the minimization of the total length of the flow network. This objective function

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is a surrogate for costs that are directly proportional to the length of the network, including the one-time initial construction and installation costs, the recurring cost for the shop-floor space, and the ongoing operations and maintenance costs.

Compared to a general flow network formed by all the edges defining the boundaries of

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the cells in a block layout, a loop covering at least one edge of each cell requires a shorter length to connect all cells, occupies a smaller portion of the shop floor, and requires a lower

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initial investment and lower operating cost. Such a configuration is a specific instance of the generalized traveling salesman problem (GTSP, Fischetti, Salazar-Gonzalez, and Toth, 1997). The shortest loop obtained for this instance of GTSP yields a promising solution

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for non-vehicle-based material handling systems such as belt and roller ground conveyors, overhead trolleys, automated monorails, and power-and-free systems.

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A loop flow system offers simplicity, flexibility, and expandability. Designing a loop on a block layout can be embedded within a larger problem of concurrent design of a unidirectional

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loop and input (I) and output (O) stations for vehicle-based material handling, such as automatically guided vehicle and autonomous delivery robot systems. In this more complex problem, it is not the length of the loop, but the total loaded and empty flow that drives the objective function. The total loaded and empty flow is the main determinant of the fleet size of the vehicles, which in turn is a substitute for the total investment and operating costs. Asef-Vaziri and Ortiz (2008) showed that the shortest loop provides an effective heuristic scheme that achieves prosperous and robust solutions for the concurrent design of the loop

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and I/O stations. The remainder of this paper is organized as follows. A literature review on loop-based material flow systems is provided in Section 2. Alternative covering constraints for loop-based network formulations on block layouts are reviewed, compared, and unified in Section 3.

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New insights into connectivity constraints as well as improved formulations are presented in Section 4. Solution procedures along with extensive computational experiments are reported in Section 5. Conclusions follow in Section 6.

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Literature Review

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The trace of loop flow network in material handling dates back to Muth (1972, 1974, and 1975) studies of conveyor systems. The loop flow system was then recognized among the widely implemented flow networks in industry (Apple, 1977). Recently, there has been a surge in the research on the loop-based flow system (Montoya-Torres et al., 2006, De Koster and Yu, 2008, and Ventura and Rieksts, 2009). This accrued interest is paralleled in industry.

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For example, flow networks at Daifuku training facilities in Salt Lake City are loop-based for all types of their automated vehicles (Asef-Vaziri and Laporte, 2009). This trend may

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have roots in the continual increase witnessed in the development of one-way streets, as well as of loop-based routes in public transportation.

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Laporte, Asef-Vaziri, and Sriskandarajah (1996) demonstrate that the problem of designing a loop on a block layout is an instance of the GTSP. The NP-hardness of the block layout

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loop design problem is proved by De Guzman Prabhu, and Tanchoco (1997). Tanchoco and Sinriech (1992), Asef-Vaziri, Laporte, and Sriskandarajah (2000), Farahani, Laporte, Shar-

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ifyazdi (2005), Asef-Vaziri and Ortiz (2008), and Ahmadijavid and Ramshe (2013) develop integer programming formulations and solution procedures for this problem. We will review these formulations in subsequent sections. Sinriech and Tanchoco (1993), Eshghi and Kazemi (2006), Hamzeei and Farahani (2007),

Hojabri et al. (2010), and Jahandideh, Asef-Vaziri, and Modarres (2013) develop heuristic procedures for this problem. Sinriech and Tanchoco (1993) provide a conventional heuristic by starting from a single cell and adding new cells until a loop covering all cells is identified. The branches of the search space leading to a cell being surrounded by other cells, such that 4

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it has no edge on the loop, are fathomed. Hojabri et al. (2010) approach the problem in an opposite direction. They start with the boundary of the block layout containing all the cells (a usually infeasible loop), and then move towards feasibility in an elimination process. Relying on the intuition that the shortest loop usually does not cover a large portion of

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the boundary of the layout, Jahandideh, Asef-Vaziri, and Modarres (2013) start from an interior loop containing all the cells excluding those on the boundary of the block layout. Eshghi and Kazemi (2006) provide an ant colony system heuristic procedure based on the necessary and sufficient condition of feasible loops in the dual graph. Hamzeei and Farahani (2007) and Hamzeei, Farahani, and Rashidi-Bajgan (2013) develop heuristic procedures for

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the shortest path (relaxing the two ends of the loop to be connected). The extension of the loop formulation to path formulation is straightforward. However, it is achieved at the expense of weaker linear programming relaxation in the modeling world, and operational difficulties in the real world.

Embedding the loop formulation within a larger problem of the concurrent design of the

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loop and the I/O stations for vehicle-based material handling was first conceptualized and modeled by Tanchoco and Sinriech (1992) and Sinriech and Tanchoco (1993). Asef-Vaziri,

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Dessouky, and Sriskandarajah (2001), Farahani, Karimi, and Tamadon (2007), Farahani, Pourakbar, and Miandoabchi (2007), Caricato and Grieco (2005), Caricato et al. (2007),

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and Asef-Vaziri et al. (2010) develop optimization models and heuristic solution procedures for the same problem. The objective function of all these models is to minimize the total

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loaded flow. Asef-Vaziri, Hall, and George (2008) demonstrate that ignoring the empty flow leads to designs that are far from optimal when both loaded and empty flow are taken into

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account.

Empty vehicle dispatching policies, as discussed in the literature, are partitioned into

three major classes of first-come-first-served (FCFS), shortest-trip-distance-first (STDF), and first-encountered-first-served (FEFS). In FCFS dispatching and its variations (Goetschalckx and Palliyil, 1994, Srinivasan, Bozer, and Cho, 1994, Al-Sultan and Bozer, 1998, Johnson, 2001, and Benjaafar, 2002) an empty vehicle is routed to the longest waiting load. In STDF dispatching (Maxwell and Muckstadt, 1982, Kouvelis and Kim, 1992, Malmborg and Shen, 1994, Goetschalckx and Palliyil, 1994, Sun and Tchernev, 1996, Asef-Vaziri, Hall 5

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and George, 2008, Asef-Vaziri and Ortiz, 2008, Asef-Vaziri and Goetschalckx, 2008, and Asef-Vaziri and Laporte, 2009) an empty vehicle is dispatched to the closest waiting load. The FEFS dispatching (Bartholdi and Platzman, 1989) is specifically designed for loop flow systems, where an empty vehicle continually circulates along a unidirectional loop, looking

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for a load to pick up and deliver. Through computational experiments, Asef-Vaziri and Ortiz (2008) show that under the FCFS dispatching policy, the shortest loop coincides with the optimal total loaded and empty flow solution for all their test problems. The shortest loop also provided near-optimal solutions when empty vehicles were following the STDF dispatching. Asef-Vaziri and Laporte

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(2009) show that the FEFS dispatching policy supports the design obtained under STDF policy, and leads to a better performance on the shortest loop.

In the facility design algorithms, it is generally assumed that the required number of loaded flows is known for the planning horizon. This is a simplification since the volume of the loaded flow is stochastic. An optimization model for the design of the loop and station

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locations can be extended to a stochastic design through the use of scenarios, albeit with a significant increase in problem size and computational cost (Asef-Vaziri and Goetschalckx,

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2008). Asef-Vaziri and Ortiz (2008) computationally show that, given a set of material flow scenarios, the shortest loop heuristic provides a close-to-optimal solution for all scenarios.

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Since the shortest loop always remains feasible, it provides a robust solution for stochastic loop design problems. In a dynamic loop design problem, the material flow matrix changes

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from one period to the next. Following the same line of reasoning, these authors show that the shortest loop is a promising heuristic for the dynamic loop design problem.

Covering Constraints

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The GTSP is a variant of the Traveling Salesman Problem (TSP, Ball, 1934) where the nodes are partitioned into a set of non-overlapping clusters. A solution is a cycle passing all clusters, where each cluster is visited exactly once through one of its nodes. These constraints are relaxed in the block layout loop design problem, where at least one edge of each cluster is visited, clusters overlap, and therefore, more than one edge of a cell (cluster) may be visited by a feasible loop. 6

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The block layout is embedded in the plane, and its edges are typically either horizontal or vertical, while few are L-shaped. The degree of a node is typically 3 (at the intersection of three edges), and less frequently 4. Degree-2 nodes (on L-shaped edges) have no structural meaning and their incident edges are considered to be a single edge. Two governing require-

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ments of this problem are (i) covering constraints, enforcing the loop to cover at least one edge of each cell, and (ii) connectivity constraints, enforcing a single loop (i.e., no subtour). In this section, we review and unify the alternative covering constraints for loop formulation on block layouts. Connectivity constraints are postponed to the next section.

Let us define C as the set of cells, E as the set of edges defining pairs of adjacent cells,

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and N as the set of nodes (intersections of the edges). The layout of our prototype example containing |C| = 11 cells, |N | = 19 nodes, and therefore, |E| = 29 edges is depicted in Figure 1. The labels of the cells and nodes, as well as the edge weights, defined as the rectilinear distance between the defining nodes, are also shown. A feasible loop is defined by the boundary of a not necessarily convex polygon formed by a set of fully connected cells.

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Each cell inside the loop is connected to at least one cell outside of the loop, and vice versa.

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2 C11

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C4 4

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Figure 1: The 11-cell prototype example with 11 cells (faces), 19 nodes, and 29 edges where the edge weights are defined by the rectilinear distance between their two end nodes. Several variants of this problem can be defined by adding or relaxing some constraints. One constraint may require the loop to pass on at least one edge on the boundary of the block layout (the external face of the block layout planar graph) to allow access to the receiving and shipping facilities. Examples of relaxations include allowing the loop to cover at least a 7

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node (not an edge) of each cell, allowing for a configuration where the loop may cross itself at the degree-4 nodes, or relaxing the loop to a path with two loose ends. While all of these variations can be easily incorporated into our formulation, we will stay with the original definition.

Degree-2 Configuration

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3.1

Degree-2 constraints ensure that the loop has either zero or two edges incident to each node. They do not ensure a connected single loop. The connectivity constraints discussed in the next section force the merging of subtours into a tour.

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1. Arc Formulation. Tanchoco and Sinriech (1992) define two binary variables of xmn , xnm , where m 6= n, for the two directions of each edge on the block layout. These variables are equal to 1 if the directed arc is on the loop, and are equal to 0 otherwise. Given a set E of undirected edges, Constraints (1) enforce unidirectional arcs. Constraints (2) restrict at most one incoming arc for each node. Constraints (3) enforce the equality of the number of

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incoming and outgoing arcs for each node.

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xmn + xnm ≤ X xmn ≤

1

∀mn ∈ E, m < n

(1)

1

∀n ∈ N

(2)

∀n ∈ N.

(3)

m,n

m6=n

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X

xmn =

m,n

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xnm

m,n

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m6=n

The integrality constraints of xmn , xnm ∈ {0, 1} for all mn ∈ E are also included.

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2. Node-Edge Formulation. Laporte and Nobert (1983) have developed the following formulation for the GTSP. Since the matrix representing the distances between pairs of nodes is symmetric, only one binary variable is required for the corresponding undirected edge. The binary variable ymn : m < n is 1 if the undirected edge mn is on the loop, and is 0 otherwise.

The binary variable vn is 1 if node n is on the loop, and is 0 otherwise. Constraints (4) ensure that the loop has either zero or two edges incident to each node. X

m
ymn +

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ynk = 2vn

n
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∀n ∈ N.

(4)

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The integrality constraints of ymn ∈ {0, 1} for all mn ∈ E, and vn ∈ {0, 1} for all n ∈ N are also included. 3.

Edge Formulation. Asef-Vaziri, Laporte, and Sriskandarajah (2000) drop the vn

variables. Constraints (5) state that at most two edges incident to a node are on the loop.

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Constraints (6) ensure that no node has only one edge on the loop. In other words, for each degree-k node, the summation of the binary variables associated with each combination of the k − 1 edges incident to the node, is greater than or equal to the value of the binary variable associated with the remaining edge. These constraints are written on both nodes of

ymn +

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X

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ykm +

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X k6=n

k>m

ykn +

k6=m

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∀n ∈ N

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ymk ≥ ymn

X k>n

ynk ≤ 2

ynk ≥ ymn

∀mn ∈ E.

(6)

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each edge,

The ymn variables have the same definition as in Node-Edge formulation, and their integrality

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constraints are also included.

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4. Cell Formulation. Farahani, Laporte, and Sharifyazdi (2005) define a binary variable for each cell. The binary variable zc is 1 if cell c is inside the loop, and 0 otherwise. The

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variable z0 associated to the external face of the block layout is set to 0 in order to ensure it is always outside the loop. This formulation cannot be directly embedded into larger formulations for the concurrent design of the loop and I/O stations, where the arcs on the

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loop have to be explicitly defined. 5. Cell-Edge Formulation. This formulation was developed by Asef-Vaziri and Ortiz (2008). Without loss of generality, suppose cells c and k are on the opposite sides of edge mn. Edge mn is on the loop if one of the cells c or k is inside the loop and the other is outside. The variable z0 is always set to 0. The constraints are stated as follows ymn = |zc − zk |. 9

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and are linearized as zc + zk ≥ ymn zc + ymn ≥ zk zk + ymn ≥ zc ∀mn ∈ E.

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zc + zk + ymn ≤ 2

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The integrality constraints of ymn ∈ {0, 1} for all mn ∈ E, and zc ∈ {0, 1} for all c ∈ C are also included.

It worth to note that the Edge-formulation can also be viewed in an absolute value form,

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as with the Cell-Edge-formulation. Without loss of generality, consider the edges mn, rn, and qn, where m, r, q < n are incident to the degree-3 node n. The degree-2 constraints can then be stated as ymn = |yrn − yqn |. For degree-4 nodes, the ymn on the left-hand-side will be replaced by the absolute value of the difference between ymn and the variable associated

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with the fourth edge.

At Least One Edge Constraints

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The loop must cover at least one edge of each cell. In the Node-Edge, Edge, and Cell-Edgeformulations this is stated as Constraints (8), where Ec is the set of edges on cell c ∈ C. In

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the Arc-formulation, ymn is replaced with xmn + xnm . In the Cell-formulation, it is applied

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mn∈Ec

ymn ≥ 1

∀c ∈ C

(8)

Objective Functions

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3.3

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through subtour elimination constraints, as will be discussed later.

The objective function in the Node-Edge, Edge, and Cell-Edge-formulations is stated as (9), where lmn is the length of edge mn, Minimize

LLoop =

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lmn ymn .

(9)

mn∈E

In the Arc-formulation ymn is replaced by xmn + xnm . Given Lc as the perimeter of cell c, the objective function of the Cell-formulation is defined as the summation of the perimeters 10

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of all cells inside the loop, minus twice the length of their common edges, Minimize

LLoop =

X c∈C

L c xc − 2

X X

lmn zc zk .

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c∈C k>c∈C

A set of classical constraints are then added to replace the non-linear terms of zc zk by a real

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variable qck .

Connectivity Constraints

The boundary of a polygon formed by a set of fully connected cells is a feasible loop if it covers at least one edge of every cell in the layout. Subtours emerge whenever covering at

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least one edge of each cell does not encompass a single set of fully connected cells. The optimal solution for the prototype example, where only (i) degree-2 constraints and (ii) at least one edge constraints are included, is shown in Figure 2. Under these constraints, a 1cell subtour of C6 and a 2-cell subtour of C4-C10 have emerged. The solution satisfies both the degree-2, as well as at least one edge constraints, but is not connected. The formulation

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needs connectivity (subtour elimination) constraints.

In this section, we provide new insight into the subtour elimination constraints (SECs)

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for the loop formulation on block layouts. We first provide a better adaptation of the Miller, Tucker, and Zemlin (1960) SECs originally developed for the TSP. It has been recognized

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that these constraints would require more than one run of an integer programming solver to obtain the shortest loop on a block layout. By exploiting a property usually observed in

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block layouts, we show that, in most cases these constraints can lead to an optimal solution 18

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Figure 2: Examples of 1-cell and 2-cell subtours. 11

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in a single run. We then discuss two adaptations of Dantzig, Fulkerson, and Johnson (1954) SECs, also originally developed for the TSP. On the foundations of the equivalence of the two adaptations, we identify and drop several families of dominated subtour elimination

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Miller, Tucker, and Zemlin SECs

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constraints.

Miller, Tucker, and Zemlin (1960) derived the following subtour elimination constraints (MTZ-SECs) for the TSP:

∀mn ∈ A,

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um − un + |N |xmn ≤ |N | − 1

where A is the set of directed arcs (|A| = 2|E|). The binary variable xmn has the same meaning as it does in the Arc-formulation; xmn = 1 if directed arc mn is on the loop, and 0 otherwise. The real variable um , emerging integer in the optimal solution to the LPrelaxation, is the rank of node m in the sequence of the tour. The constraints require a

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node to be duplicated. This node is assumed as the first and the last node of the loop. For example, node 4 in Figure 2 is duplicated and is also labeled as node 20 (there are 19 nodes

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in this layout). Node 20 is virtually connected to nodes 1, 3, and 8. Node 4 is considered as the first and node 20 as the last node in the tour; u4 = 1 and u20 = 20. MTZ-SECs can

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be directly implemented in the Arc-formulation. In order to implement MTZ-SECs in the

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three formulations of Node-Edge, Edge, and Cell-Edge, we modify Constraints (1) as xmn + xnm = ymn

∀mn : m < n ∈ E.

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Constraints (3) are also included to enforce the equality of incoming and outgoing arcs,

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leading to a directed loop. The MTZ-SECs cannot be used in the Cell-formulation since the edges are not explicitly defined. Finding the Loop in a Single Run. Tanchoco and Sinriech (1992) argue that since the

node to be duplicated is assumed as the first and the last node on the loop, it is included in any feasible solution, including the optimal solution. This inclusion does not damage optimality in the TSP because all the nodes are included in all feasible and optimal solutions. However, in the block layout shortest loop design problem, it is not known in advance which 12

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nodes are covered by the optimal loop. Forcing any node to be in the feasible solutions will cut a portion of the feasible region that may contain the optimal solution. According to Asef-Vaziri, Laporte, and Sriskandarajah (2000), if a cluster c has the smallest set of nodes (Nc ), the formulation must be repeated |Nc | times. The overall optimal solution is then

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identified by comparing the optimal solutions of |Nc | separate runs of the IP solver. Property 1 Node duplication in MTZ-SECs does not necessarily cut a portion of the feasible region.

Proof. First, in block layouts we do not require |Nc |, but |Nc | − 1 repetitions of MTZ-SECs.

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The last node on cell c does not need to be duplicated and examined because at least one edge (two adjacent nodes) of each cell is covered by a feasible solution. If the last node on cell c belongs to an optimal solution, it has already been covered through duplication of one of its two adjacent nodes. Second, if cell c has three nodes, as could be the case at one of the corners of the block layout, then the node at the intersection of the two shorter edges will

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always be covered by the optimal loop. Its duplication does not cut a portion of the feasible region.

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First, consider cell C6 with 5 nodes in Figure 2. If all the nodes except node 4 have already been duplicated, then node 4 does not need duplication. Even if node 4 must be on the

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optimal solution, the loop will have the opportunity to pass it through duplication of either node 3 or node 8 duplications. Second, consider cell C1 in Figure 2. Node 4 will always be

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covered if one of the edges (1,4) or (3,4) is covered by an optimal loop. In the case where none of these edges are covered, then edge (1,3) must be covered by the loop. Nevertheless,

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edge (1,3) can always be replaced by the two edges of (1,4) and (3,4) due to equality of their lengths. This substitution does not damage optimality, since in the presence of nodes 1 and 3, node 4 cannot also be on the loop because it contradicts degree-2 constraints. Accordingly, node 4 will always be on the optimal solution, and its duplication does not cut a portion of the feasible region; the optimal solution can be identified in a single run. Improving the MTZ-SECs. The number of constraints is the main advantage of the MTZ-SECs since it is linear in the number of nodes. However, the shortcoming is in their 13

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weak LP-relaxation (Langevin, Soumis, and Desrosiers, 1990). The MTZ-SECs have been lifted to the following stronger form (Desrochers and Laporte, 1991). um − un + |N |(xmn + xnm ) − 2xnm ≤ |N | − 1

mn ∈ A.

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Nevertheless, the LP-relaxation is still weak (Desrochers and Laporte, 1991).

Dantzig, Fulkerson, and Johnson SECs

Dantzig, Fulkerson, and Johnson (1954) developed the following constraints (DFJ-SECs) for X

m,n∈U

ymn ≤ |U | − 1

∀ U ⊂ N.

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the TSP,

where N is the set of nodes. Only subtours of sizes up to b|N |/2c nodes require explicit SECs. Formation of a subtour U 0 : |U 0 | > b|N |/2c leads to formation of one or more complementary

subtours U of a size not exceeding b|N |/2c. If the SECs of the latter subtours are already included in the formulation, the SECs of larger subtours are not needed. Zero, one, or two

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nodes may not form a subtour in a symmetric TSP since the binary variable ymn is only

k=3

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defined for m < n. The number of subtours to be considered is therefore reduced to  b|N |/2c  X |N | = 2|N |−1 − |N |(|N | − 1)/2 − |N | − 1. k

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While no other SECs for TSP yield a stronger LP-relaxation than DFJ-SECs (Oncan, Altinel, and Laporte, 2009), the number of constraints grows exponentially in the number of nodes.

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Adapting the DFJ-SECs. Asef-Vaziri, Dessouky, and Sriskandarajah (2001) adapt a slight modification of the DFJ-SECs for the block layout loop design problem. The modified

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constraints do not allow the emergence of subtours on the boundary of the polygons formed by subsets of adjacent cells. They enforce at least two edges, each with one node on the polygon and the other node not on the polygon, to be on the loop. X ymn ≥ 2, ∀ S ∈ R,

(12)

mn∈E(S,C\S)

where R is the set of potential subtours S: |S| ≤ b|C|/2c, and E(S, C\S) 6= ∅ is the set of edges having one node in S and the other node not in S. Since 1- and 2-cell subtours can emerge in a block layout, the upper bound for the number of subtours is 2|C|−1 − 1. 14

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Constraints (12) were first introduced in Asef-Vaziri, Dessouky, and Sriskandarajah (2001), and were later implemented in Asef-Vaziri, Laporte, Ortiz (2007), Asef-Vaziri and Ortiz (2008), and Ahmadijavid and Ramshe (2013). The SEC to eliminate the 1-cell subtour of C6 in Figure 2 is

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y1,3 + y12,18 + y13,14 + y8,9 + y1,4 ≥ 2.

The SEC to eliminate the 2-cell subtour of C4-C10 in Figure 2 is y2,5 + y6,7 + y16,17 + y15,19 + y9,10 ≥ 2. Similar SECs are applied on larger subtours.

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It is worth noting that the 1-cell SECs ensure that at least one node of each cell is on the loop. Therefore, one may drop Constraints (8) and consider a variant of the problem where the loop must cover at least one node of each cell. Nevertheless, with the exception of the degree-4 nodes, such as node 10 in Figure 2, a loop covering one node of a cell will also cover one edge of that cell.

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In a symmetric TSP and the GTSP, subsets of 3 to b|N |/2c vertices require explicit SECs. This relationship remains valid for the number of nodes in the block layout loop

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design problem; only subtours with at most b|N |/2c nodes require an explicit SEC. For example, no constraint is required to eliminate subtour S = C5-C7-C9 in Figure 4a. The

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number of the nodes on this subtour (11) is greater than half of the number of the nodes in the layout (18). Furthermore, since we have defined subtours in terms of the cells but not

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nodes, there are more simplifications to follow. In the remainder of this section, we provide a stronger adaptation of the DFJ-SECs. We

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show that a class of potential subtours, such as the 1-cell subtour of C6, as well as the 2-cell subtour of C4-C10 in Figure 2, are redundant (their SECs are dominated by other SECs). We also show that the SECs for the a family of subtours, such as those in Figures 3 and 4 argued in Ahmadijavid and Ramshe (2013), have stronger covering inequalities. In the framework of our definition, a component S ⊂ C, formed by a set of adjacent cells as a subtour, creates two other components in the block layout. The first is the full-complement S, which includes the set of cells in C having no node in common with S. The second is S = C\(S ∪ S). 15

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Stronger Adaptation of the DFJ-SECs. The Asef-Vaziri, Laporte, and Sriskandarajah (2000) adaptation of the DFJ-SECs is stated as X

mn∈E(S,S)

ymn ≥ 2,

∀ S ∈ S,

S 6= ∅,

(13)

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where E(S, S) is the set of edges with one node in S and the other node in S. We complete Constraints (13) by stating that the set of potential subtours R in the context of Constraints (12) is replaced by the set of non-redundant subtours S ⊆ R. In the rest of this manuscript we refer to Constraints (12) and (13) as DFJ1-SECs and DFJ2-SECs, respectively.

In the school of DFJ2-SECs, the subtour S = C9 in Figure 3a is redundant; it does not

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belong to S ⊆ R. The SEC of this subtour in the context of DFJ1-SECs is stated as y16,17 + y15,16 + y3,14 + y12,13 + y12,18 ≥ 2.

(12’)

A solution of y15,16 + y16,17 = 2 satisfies this constraint and leads to the formation of one of the subtours C8 or C8-C9. Since none of the edges (15,16) and (16,17) are directly connected

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to S, this constraint may not lead to a single connected loop. These two variables can play a role towards connectivity only if y15,16 + y16,17 = y5,16 = 1. Similarly, y12,13 + y12,18 = 2

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will form subtours C10 or C9-C10. These two variables can play a role in connectivity only if y12,13 + y12,18 = y11,12 = 1. Four variables appear on the left-hand-side of Constraint (12’)

(a)

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7

1

AC

6

C4

4 C7 15

16

17

C4

3

C6

C5

13

12

4 C7 15

16

17

18

3 13

14 C9

C8

C10

12 C10

18

Figure 3: An instance of dominated forms of DFJ1-SECs. 16

11

10 2

5

C9

C8

1

6 C6

14

C3

7

C1

2

5

9 C2

11

10

C5

8

C3

C2

C1

(b)

9

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8

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while none of them could connect S to S and lead to a single loop. Even y16,17 + y15,16 + y12,13 + y12,18 = 4 does not play a role towards connectivity. Theorem 1 A subtour S having one or more cells S ⊂ S that are not adjacent to any cell ∼

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. in S is redundant. S is lifted to S ∪ S ∼ Proof. The SEC of such a subtour S still allows for the formation of S plus a subset of S ∼ as a new subtour since no element of S is connected to S. The SEC of S ∪ S will definitely ∼ ∼ connect S to S. Lifting a constraint does not cut any feasible portion of the search space. The lifted subtour may not become a feasible loop because it does not cover an edge of S.

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Subtour S = C9 in Figure 3 is lifted to S = C8-C9-C10 because S = {C8,C10} ⊂ S does ∼ not have an edge in common with S and may lead to a new subtour still unconnected to the cells not covered by the loop. Constraint (12’) is lifted to

(13’)

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y5,16 + y3,14 + y11,12 ≥ 2.

Constraint (13’) is stronger than Constraint (12’) since according to Constraints (6), y16,17 +

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y15,16 ≥ y5,16 and y12,13 + y12,18 ≥ y11,12 . Standing on the same platform, five of the 1-cell subtours in Figure 3 are lifted as: C2→C2-C3, C5→C4-C5, C6→C2-C3-C6-C10, C7→C7-

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C8, and C9→C8-C9-C10. On the same line of reasoning, SECs of subtours C6 and C4-C10 in Figure 2 are dominated by the SECs of subtours C1-C6 and C3-C4-C5-C10-C11, respectively.

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This class of lifts is especially important in a branch-and-cut procedure, since redundant cuts in the subsequent nodes could lead to new infeasible solutions which could be avoided.

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Theorem 2 A class of subtours having a unique full-complement require a single SEC. Proof.

Given subtour S with some supersets (S plus one or more cells adjacent to it),

and some subsets (S excluding one or more cells), all with the same full-complement of S. Suppose S” is the largest superset of S, and S 0 is an arbitrary subset or superset of S,

both having the same full-complement of S. Any cell c ∈ S” should be also adjacent to S 0 , otherwise it belongs to S 0 . This is a contradiction to both S” and S 0 having the same full

complement. Furthermore, cell c should be adjacent to S. Otherwise, according to Theorem 17

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1, by adding cell c to S”, a larger superset with the same full complement will appear. This contradicts the definition of S”. Therefore, all cells in S” are adjacent to both S 0 and S. Accordingly, the single SEC of S” will eliminate all the subsets and supersets of S having the same S.

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DFJ1-SEC when applied on subtour S = C5-C7-C9 in Figure 4a appears as y12,18 + y12,13 + y2,7 + y1,6 + y5,6 + y16,17 ≥ 2.

(12”)

This constraint even includes y16,17 , while y16,17 = 1 plays no role in connectivity. The SEC

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of S = C5-C7-C9 is dominated by the SEC of S = C4-C5-C7-C8-C9-C10 as y6,8 + y2,7 + y11,12 ≥ 2.

(13”)

Constraint (13”) sufficiently eliminates all the subtours formed by combinations of (i) C7C9, (ii) one, or both (but not none) of C4 and C5, and (iii) none, one or both of C8 and

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C10. These are polygons formed by 3 to 6 cells, creating a total of 12 potential subtours, where 11 of them do not need an SEC.

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As the final look at DFJ1- and DFJ2-SECs, we further implement them in the context of Cell-formulation (Farahani, Laporte, Sharifyazdi, 2005) or Cell-Edge-formulation (Asef-

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Vaziri and Ortiz, 2008). According to Farahani, Laporte, and Sharifyazdi (2005), to eliminate (a)

8

CE

C2

7

C1 1

AC

6

C4

16

C6

17

1 C4

3

C6

C5 4 C7 15

16

12

18

3 13

14 C9

C8

C10

17

11

10 2

5

13

C3

7

C1 6

C9

C8

9 C2

11

10

C5

14

8

C3

2

5

4 C7 15

(b)

9

12 C10

18

Figure 4: A second instance of dominated forms of DFJ1-SECs. 18

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S = C9 in Figure 3a, the constraint z6 + z7 + z8 + z10 ≥ 1

z6 + z7 ≥ 1.

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is added in the formulation. In the context of DFJ2-SECs, this constraint is lifted to

Similarly, the SEC of S = C5-C7-C9 in Figure 4a, will benefit a lift from z1 + z4 + z6 + z8 + z10 ≥ 1, to

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z1 + z6 ≥ 1.

Theorem 3 DFJ1-SECs and DFJ2-SECs are identical for non-redundant subtours. Proof. Set C\S in DFJ1-SECs is identical to the set S ∪ S. Consequently, DFJ1-SECs can X

mn∈E(S,S∪S)

Given

X

ED

X

ymn ≥ 2,

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be rewritten as

ymn =

∀S ∈ S,

ymn +

mn∈E(S,S)

mn∈E(S,S∪S)

S 6= ∅.

X

ymn .

mn∈E(S,S)

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According to Theorem 1, any cell in S without an edge in common with S has already been

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added to S, i.e., S is a non-dominated subtour. It follows that E(S, S) = ∅

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and all the edges incident to S are also incident to S. Figures 3b and 4b are pictorial representations of this property. DFJ1- and DFJ2-SECs are identical for S = C8-C9-C10 as well as for S = C4-C5-C7-C8-C9-C10. Finally, in the case of loops within other loop, S ∈ S may have its S = ∅, Constraint (14) is added,

X

mn∈bES

Emn ≤ |bES | − 1.

(14)

when bES is the set of the edges on the boundary of the polygons forming the subtours. 19

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5

Computational Considerations

In this section, we report computational results for branch-and-bound (B&B) and branchand-cut (B&C) solution procedures. Layouts of sizes 60-, 80-, 100-, 150-, 200-, 250-, and 300-cells are examined in our computational experiments.

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We partition block layouts into two categories of generally structured (GS) and rectangularly structured (RS) layouts. A GS layout, Figure 5a, is formed by a set of not necessarily convex rectilinear polygons. All the polygons are rectangular in an RS layout. We report our computational experiments on three types of RS layouts: slicing structure (SLS, Tam, 1992), flexible bay structure (FBS, Donaghey, 1987), and non-slicing structure (NSS, Kim

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and Goetschalckx, 2005). A block layout has a slicing structure, Figure 5b, if the cells are formed by adding a horizontal or vertical line to a rectangle in the block layout, thereby dividing it into two. Partitioning the rectangles horizontally/vertically will continue until all cells are formed. A FBS layout, Figure 5c, is a special case of SLS layout where it is

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partitioned into a set of parallel bays. Cells in the same bay have the same size in the direction perpendicular to the bays. Their two parallel sides in that direction have only one

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edge. The other two sides usually contain more than one edge. A NSS layout, Figure 1, is a SLS/FBS layout with some relaxations to allow for more practical cell shapes. The NSS layout test problems of this study were designed by Kim and Goetschalckx

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(2005), the FBS layout test problems were provided by Professor Hitchum Kamoun, and the

AC

CE

SLS layout test problems (SLS) were generated by the authors of this study.

Figure 5: Three layout representations for an 11-cell example; (a) GS, (b) SLS, and (c) FBS layouts.

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5.1

B&B Experiments

In a B&B solution procedure, for subtour elimination, we accompany stronger form MTZSECs with DFJ2-SECs on 1-cell subtours to improve the performance of the MTZ-SECs. All the B&B computations were experimented using CPLEX 12.1 on a virtual machine with

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an Intel Xeon X5650 2.67 GHz and 12GB of memory, running on HyperV on a Windows 2008 R2 Server.

As it is shown in Table 1, the optimal solutions for 60-cell NSS layouts were obtained between 0.3 and 2.4 seconds with an average of 1.1 seconds. The optimal solutions for 60-cell FBS layouts were obtained between 0.1 and 1.2 seconds with an average of 0.6 seconds. The

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optimal solutions for three of the 80-cell NSS layouts were obtained under one second, while two instances took 3.4 and 11.4 seconds. The optimal solutions for three instances of 8060-cell non-slicing structure test problems T

I

N

NSS61

0.5

909

0

893.5 916

0.98

NSS62

1.2 11288 271 813.6 830

0.98

NSS63

2.4 38279 792 833 844

NSS64

1.2 12406 200 859.6 878

NSS65

0.3

677

0

Min

0.3

677

0

Max

2.4 38279 792

Z* Zlp/Z* Instance

T

I

N

NSS81

0.4

1110

0

1160.3 1166

1.00

NSS82

0.6

894

0

988.4

990

1.00

0.99

NSS83

0.7

1570

0

1034.4 1048

0.99

0.98

NSS84

11.4

206676

4531 1109.6 1134

0.98

1.00

NSS85

3.4

44011

898

0.98

ED

882 884

I

N

CE

T

Z*

Zlp/Z*

1057.0 1076

-

0.98

Min

0.4

894

0

-

-

0.98

-

-

1.00

Max

11.4

206676

4531

-

-

1.00

-

-

0.98

Average

5.4

91965

1992

-

-

0.99

60-cell flexible bay structure test problems Instance

Zlp

-

PT

Average 1.1 12712 253

Zlp

M

Instance

80-cell non-slicing structure test problems

Zlp

80-cell flexible bay structure test problems

Z* Zlp/Z* Instance

T

I

N

Zlp

Z*

Zlp/Z*

692

125.5

134

0.94

FBS61

1.2 15421 203 85.35 90

0.95

FBS81

4.5

73120

FBS62

0.7 2367

0

97.2 102

0.95

FBS82

49.6

16733

16733 141.3

154

0.92

FBS63

0.1

499

100 100

1.00

FBS83

8.1

122515

1642

138.1

146

0.95

0.1

532

0

100 100

1.00

FBS84

5.1

90664

864

141.4

148

0.96

FBS65

0.9 2972

7

105.6 110

0.96

FBS85

116.2 1912650 34091 148.9

162

0.92

Min

0.1

0

-

-

0.92

Max

1.2 15421 203

AC

0

FBS64

499

Average 0.6 4358

42

-

-

0.95

Min

4.5

16733

692

-

-

1.00

Max

116.2 1912650 34091

-

-

0.96

-

-

0.97

Average

50.0

-

-

0.93

811042 14276

Table 1: Performance of the B&B solution procedure on 60 and 80 cell FBS and NSS layouts. T: solution time in seconds, I: number of LP iterations, N: number of IP nodes, Zlp: value of the LP objective function at the root node, and Z*: optimal IP objective function value.

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cell FBS layouts were obtained under 8.1 seconds, while two instances took 49.6 and 116.2 seconds. The solution times for 80-cell FBS layouts are longer than those of NSS layouts. This is perhaps due to greater symmetry in FBS layouts. While the solution times are longer compared to the times that we will report later for our B&C procedure on a slower computer,

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they are the most favorable results reported for a B&B procedure to find the shortest loop in a block layout. The ratio of the LP optimal solution value at the root node compared to the optimal IP value at the end of the B&B solution procedure was more than 92% in all instances. This ratio for 80-cell FBS layouts was lower than the other three sets of layouts.

B&C Experiments

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5.2

Our B&C model includes Constraints (5) and (6) to enforce a degree-2 flow pattern, and Constraints (8) to enforce at least one edge of each cell to be on the loop. The B&C computational experiments were conducted using CPLEX 12.6 on an Intel i3-3240 3.4 GHz with 2 GB memory running on Windows 7.

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In one set of runs we applied DFJ1-SECs, and in another we applied DFJ2-SECs on 100 to 250 cell SLS layouts. The results are shown in Figure 6. The average number of cuts when

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DFJ1-SECs were applied was 4.05 times of that of DFJ2-SECs. The gap became greater for the larger problems. The 95% confidence interval was 2.76-5.34 times. The average number

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of constraints per cut were 3.2 for DFJ1-SECs and 3.8 for DFJ2-SECs. Both the smaller number of cuts and the larger number of constraints per cut support DFJ2-SECs. The

AC

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average solution time when DFJ1-SECs were applied was 2.67 times of that of DFJ2-SECs.

Figure 6: Comparison of (a) the number of cuts and (b) solution times in seconds for DFJ1and DFJ2-SECs.

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The gap increased for the larger problems. The 95% confidence interval was 1.46-3.89 times. The IP solution at the root node and the optimal IP solution after the last cut of the B&C solution procedure for a 250-cell instance of SLS test problems are shown in Figure 7a and 7c, respectively. Instantiations of the difference between DFJ1- and DFJ2-SECs can be

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observed in Figure 7a and 7b, where some cells in S are not adjacent to any cell in S. The darkened cells in Figure 7b are the cells that can be added to the subtours in Figure 7a, and lift their SECs significantly.

The algorithms for our computational experiments were coded in Visual C#. At the subsequent nodes of the B&C process, DFJ2-SECs, or Constraints (14) when needed, were

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applied on the emerged subtours by using LazyConstraintCallback class of CPLEX. Whenever CPLEX finds a candidate integer solution in a node of B&B tree, the solution is sent to the LazyConstraintCallback to check if it contains one or more subtours. If the candidate solution contains no subtour, then the solution is accepted and the node is fathomed. Since the lazy constraints are generated along with the DFJ2-SECs or Constraint (14), if required,

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our B&C approach has an integrated nature; the optimal solution is obtained in a single run of the IP solver.

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As shown in Table 2, the solution times for 60-cell NSS layouts were between 0.001 and 0.194 second with an average of 0.077 second. These numbers for 60-cell FBS layouts were

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CE

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0.001, 0.003, and 0.002 seconds, respectively. The solution times for 80-cell NSS layouts

Figure 7: Comparison of DFJ1- and DFJ2-SECs for an instance of SLS 250-cell test problems: (a)the IP solution at the root node, (b) lifting the SECs, and (c) the optimal IP solution.

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were between 0.001 and 0.426 second with an average of 0.088 second. These numbers for 80-cell FBS layouts were 0.45, 3.61, and 1.55 seconds, respectively. Parallel to the size of the problems, the solution times were affected by the layout structures. The number of constraints applied during the B&C cuts for the 60-cell problems was 4.5 on average, with

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a minimum of 2 and a maximum of 9. These numbers for the 80-cell problems were 16.4, 0, and 45, respectively. The average number of cuts generated in LazyConstraintCallback for the 60-cell problems was 2.2, with a minimum of 1 and a maximum of 4. These numbers for the 80-cell problems were 5.8, 0, and 14, respectively.

The optimal integer solutions for some of the test problems were obtained at the root

‘

AC

CE

PT

ED

M

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60-cell non-slicing structure test problems 80-cell non-slicing structure test problems Instance T N I C S Zlp/Z* Instance T N I C S Zlp/Z* NSS61 0.185 52 1304 3 7 0.96 NSS81 0.001 0 109 1 2 0.99 NSS62 0.001 0 219 3 6 0.98 NSS82 0.001 0 4 1 2 1 NSS63 0.002 0 98 2 4 0.99 NSS83 0.009 5 428 0 0 0.99 NSS64 0.194 19 508 4 9 0.98 NSS84 0.426 30 961 9 27 0.98 NSS65 0.002 0 0 2 4 1 NSS85 0.001 0 221 9 28 0.98 Mean 0.077 14.2 426 2.8 6.0 0.98 Mean 0.088 7.0 345 4 11.8 0.99 Min 0.001 0 0 2 4 0.96 Min 0.001 0 4 0 0 0.98 Max 0.194 52 1304 4 9 1 Max 0.426 30 961 9 28 1 60-cell flexible bay structure test problems 80-cell flexible bay structure test problems Instance T N I C S Zlp/Z* Instance T N I C S Zlp/Z* ‘ FBS61 0.001 0 372 3 6 0.95 FBS81 0.561 133 6076 6 15 0.94 FBS62 0.003 0 297 1 2 0.96 FBS82 1.772 898 34664 9 23 0.89 FBS63 0.003 0 24 1 2 0.97 FBS83 1.381 802 21213 5 13 0.92 FBS64 0.001 0 71 2 4 0.89 FBS84 0.446 122 5102 4 10 0.93 FBS65 0.001 0 487 1 2 0.96 FBS85 3.612 1829 53468 14 45 0.89 Mean 0.002 0 250 1.6 3 0.95 Mean 1.55 757 24105 7.6 21 0.91 Min 0.001 0 24 1 2 0.89 Min 0.45 122 5102 4 10 0.89 Max 0.003 0 487 3 6 0.97 Max 3.61 1829 53468 14 45 0.94 Combined NSS&FBS Mean 0.040 7.1 338 2.2 4.5 0.97 Mean 0.819 381.9 12225 5.8 16.4 0.95 Min 0.001 0 0 1 2 0.89 Min 0.001 0 4 0 0 0.89 Max 0.194 52 1304 4 9 1 Max 3.612 1829 53468 14 45 1.00

Table 2: Performance of the B&C solution procedure on 60- and 80-cell NSS and FBS layouts. T: solution time in seconds, N: Number of B&B nodes, C: number of B&C cuts, S: number of constraints applied in C cuts, Zlp/Z*: the ratio of the LP objective function value at the root node to the optimal IP objective function value.

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node. It does not necessarily mean that the optimal solution to the root node LP-relaxation had all integer values for the integer restricted variables. CPLEX has two other capabilities to solve a model at the root node. First, while the initial LP-relaxation solution does not have all integer values, CPLEX adds cuts at the root node, and one of the subsequent root

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nodes of the LP-relaxations has a solution with no integer infeasibility. Second, while neither the initial nor the subsequent root nodes after CPLEX cuts have all integer values, one of CPLEX’s heuristics finds an integer solution that matches the objective of the most recent root node LP-relaxations.

The results for larger SLS problems are reported in Table 3. The optimal solutions for

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100-cell SLS layouts were obtained between 0.4 and 1.7 seconds, with an average of 1 second. These numbers for 150-cell layouts were 1, 94.5, and 21.4 seconds, respectively. The optimal solutions for 200-cell layouts were obtained between 12.2 and 192.1 seconds with an average of 78.5 seconds. These numbers for 250-cell SLS layouts were 82.7, 463.8, and 269.5 seconds, respectively.

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The ratio of the LP objective function at the root node to the optimal objective function value for 100- to 250-cell SLS problems were between 89% and 97%. Our model has a

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compact set of covering constraints, since each node of the primal graph representing the block layout is connected to ≤ 4 other nodes. More importantly, compared to a TSP, the

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number of binary variables on the left-hand-side of these constraints is much smaller in the block layout loop design problem. In a TSP, the number of binary variables on the left-

CE

hand-side of a constraint to eliminate a k-node subtour is k(N − k). Summation of these binary variables needs to be ≥ 2. We have defined subtours in terms of the cells but not

AC

nodes. The number of binary variables on the left-hand-side of each 1-cell SEC is limited to the number of edges connected to each cell in the planar dual graph associated with the block layout. That is why 1-cell SECs in particular, and the SECs of small-size subtours in general, have a profound impact on lifting the LP-relaxation. Performance of the CPLEX LP/IP routines experienced throughout the computational considerations, both in B&B and B&C, were as follows. The steepest edge pricing performed better than all other dual gradient pricing rules. Although the depth-first search immediately identifies a feasible integer solution and continuously improves it, the quality of the 25

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100-cell slicing structure test problems

150-cell slicing structure test problems

T

C

S

S/C

ZLP/Z*

Instance

T

C

S

S/C

ZLP/Z*

SLS101

1.2

11

38

3.5

0.95

SLS151

94.5

38

133

3.5

0.89

SLS102

0.4

3

13

4.3

0.95

SLS152

5.9

11

47

4.3

0.95

SLS103

1.7

16

44

2.8

0.94

SLS153

3.2

26

85

3.3

0.93

SLS104

0.7

5

14

2.8

0.97

SLS154

1

14

41

2.9

0.95

SLS105

1.1

18

57

3.2

0.95

SLS155

2.3

13

54

4.2

0.96

Min

0.4

3

13

2.8

0.94

Min

1

11

41

2.9

0.89

Max

1.7

18

57

4.3

0.97

Max

94.5

38

133

4.3

0.96

10.6 33.2 3.3

0.95

Average

21.4 20.4

72

3.6

0.94

Average

1

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Instance

200-cell slicing structure layout test problems 250-cell slicing structure layout test problems T

C

S

S/C

ZLP/Z*

Instance

SLS201

12.2

6

28

4.7

0.96

SLS251

SLS202

129.8 36

140

3.9

0.95

SLS203

25.3

18

72

4

SLS204

33

38

174

SLS205

192.1 61

Min

12.2

T

C

S

S/C

ZLP/Z*

463.8 43

182

4.2

0.95

SLS252

82.7

25

97

3.9

0.95

0.94

SLS253

345.6 35

157

4.5

0.95

4.6

0.95

SLS254

239.1 43

154

3.6

0.93

245

4

0.95

SLS255

216.4 29

127

4.4

0.96

6

28

3.9

0.94

Min

82.7

25

97

3.6

0.93

Max

192.1 61

245

4.7

0.96

Max

463.8 43

182

4.5

0.96

Average

78.5 31.8 131.8 4.2

Average 269.5 35 143.4 4.1

0.95

ED

M

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Instance

0.95

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Table 3: Performance of the B&C solution procedure on the instances of the 100-, 150-, 200-, and 250-cell slicing structure test problems. T: solution time in seconds, C: number of cuts,

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S: number of constraints applied in all cuts, Zlp: value of the LP objective function at the root node of the B&C, and Z*: the optimal IP objective function value.

subsequent solutions are worse than that of other backtracking strategies. The depth-first

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search routine was dominated by both best linear lower bound and best estimated integer objective function when all integer infeasibilities are removed. The node selection strategy of best linear lower bound and variable selection strategy of pseudo-reduced costs is recommended when the user expects to stop the solution procedure before it finds the optimal solution. Finally, we examined a set of 300-cell problems. The results are shown in Table 4. The solution times were between 153 and 1270 seconds, with an average of 487 and a 95%

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Instance SLS301 SLS302 SLS303 SLS304 SLS305 SLS306 SLS307 SLS308 SLS309 SLS310 Mean Min Max 95%CM

300-cell slicing structure test problems T N I/N Zlp/Z* TfZ*/T C S S/C NFtm/N 483 40363 69.4 0.98 0.16 40 181 4.5 0.43 217 27198 43.6 0.98 0.24 42 199 4.7 0.41 546 60151 49.5 0.98 0.87 32 131 4.1 0.42 727 85039 51.1 0.98 0.74 23 119 5.2 0.31 497 59725 48.3 0.97 0.22 17 82 4.8 0.47 360 58221 36.1 0.98 0.08 16 81 5.1 0.47 1270 113539 56.7 0.98 0.53 64 298 4.7 0.33 439 38542 60.4 0.97 0.65 56 270 4.8 0.32 180 23123 45.2 0.98 0.13 36 174 4.8 0.46 153 18288 49.1 0.98 0.79 36 134 3.7 0.36 487 52419 50.9 1.0 0.44 36.2 166.9 4.64 0.40 153 18288 36.1 0.97 0.08 16 81 3.7 0.31 1270 113539 69.4 0.98 0.87 64 298 5.2 0.47 235 21253 6.7 0.004 0.22 11.1 52.4 0.32 0.05

Table 4: Performance of the B&C solution procedure on the instances of the 300 cell slicing structure test problems. T: solution time in seconds, N: Number of B&B nodes, I: number of iterations,

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Zlp/Z*: the ratio of the LP objective function value at the root node to the optimal IP objective function value, TfZ*/T: the ratio of the time spent to find the optimal solution for the first time to the total solution time , C: number of B&C cuts applied by the user (some Gomory cuts and Zero-half cuts are automatically applied by CPLEX), S: number of constraints applied in C cuts, Nftm: number of fathomed nodes, and 95%CM: 95% confidence margin.

confidence margin of 235 seconds. The number of B&B nodes were between 18288 and

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113539, with an average of 52419, and a 95% confidence margin of 21253. The number of iterations per node were between 36.1 and 69.4, with an average of 50.9, and a 95% confidence

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margin of 6.7. The ratio of the LP objective function value at the root node to the optimal IP objective function value, were between 97% and 98%. The ratio of the time spent to

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find the optimal solution for the first time (an IP solution with the same objective function value as the proven optimal solution at the end of the computations) to the total solution time, were between 8% and 87%, with an average of 44%, and a 95% confidence margin of 22%. The number of B&C cuts applied by the user (some Gomory cuts and Zero-half cuts are automatically applied by CPLEX), were between 16 and 64, with an average of 36.2, and a 95% confidence margin of 11.1. The number of constraints applied in these cuts were between 3.7 and 5.2, with an average of 6.6, and a 95% confidence margin of 0.3. The ratio of the fathomed nodes to total number of nodes were between 31% and 47%, with an average 27

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of 40%, and a 95% confidence margin of 5%.

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Conclusion

In this study, we reviewed the mathematical model to design a loop on a block layout.

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We had an in-depth discussion on two forms of subtour elimination constraints. On these foundations, we showed that a family of subtour elimination constraints are dominated by stronger SECs. We also showed that two forms of connectivity constraints are unified when applied on non-redundant subtours. Finally, we reported extensive computational results, and solved large instances not reported before. One direction of our future research is

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to develop heuristics to reconfigure the shortest loop towards the integrated design of the loop and I/O station locations to minimize the total loaded and empty flow in vehicle-based material handling. Another direction is integration of the loop with a loop-based FBS layout design. In this direction we develop an evolutionary algorithm based on intuitions on how a loop may cover the workcenters. We then design the shortest loop and place the I/O stations

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along it. Finally, through a set of improvement algorithms, we move towards better layout,

Acknowledgments

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loop, and I/O station integrated designs.

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Thanks are due to Gilbert Laporte, Csaba Toth, the two anonymous reviewers and the department editor for their constructive comments improving our work significantly. This work

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was partially supported by a summer grant from David Nazarian College of Business and Economics, California State University, Northridge. This support is gratefully acknowledged.

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