- Email: [email protected]
Crosstalk Aware Bandwidth Modelling for VLSI RC Global Interconnects using 2-π Model
Available online at www.sciencedirect.com
Procedia Technology 6 (2012) 832 – 839
2nd International Conference on Communication, Computing & Security [ICCCS-2012]
Crosstalk Aware Bandwidth Modelling for VLSI RC Global Interconnects using 2V. Maheshwaria, A. Bansala, S. K. Chhotrayb, R. Karb,*, D. Mandalb, A. K. Bhattacharjeeb a
Deptt of ECE, Anand Engineering College, Keetham, Agra, U.P., INDIA-282007 b Deptt of ECE, National Institute of Technology, Durgapur, W.B., INDIA
Abstract In this paper, a closed-form bandwidth and delay expressions are derived based on the effective lumped element resistance and capacitance approximation of distributed RC lines using 2. Scarcity of bandwidth demands the efficient use of it for high speed and high data rate transmission systems in VLSI Design and hence, an accurate estimation of bandwidth of on-chip VLSI interconnects has become a crucial and an important issue. The proposed method derives the analytic expressions for delay and the bandwidth using 2- equivalent circuit. Our estimation method is evaluated and justified in 180 nm technology. © 2012 The Authors. Published by Elsevier Ltd. © 2012 Elsevier Ltd...Selection and/or peer-review under responsibility of the Department of Computer Science & Selection and/or peer-review under responsibility of the Department of Computer Science & Engineering, National Engineering, National Institute of Technology Rourkela Institute of Technology Rourkela Keyword: Crosstalk Noise; 2-
odel; Elmore Delay; Delay Estimation; Bandwidth
1. Introduction As integrated circuit feature sizes continue to scale well below 0.18 microns, active device counts are reaching hundreds of millions [1]. The rapid advances in deep sub-micro metre (DSM) technology have resulted in the reduction of feature size which affects the crosstalk noise problem. Crosstalk noise has become a critical problem in DSM VLSI design. Due to the reduction in chip size there is unwanted coupling voltage between two adjacent wires. _____________ * Corresponding author. Tel.:+91-9434788056; fax: +91-343-2547375. E-mail address: [email protected]
2212-0173 © 2012 Elsevier Ltd...Selection and/or peer-review under responsibility of the Department of Computer Science & Engineering, National Institute of Technology Rourkela doi:10.1016/j.protcy.2012.10.101
V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
Several factors bound to the technology contribute to the increase of crosstalk problems: the increase of the number of metal layers [2], the increase of the line thickness, the density of integration and the reduction of the spacing between lines. In [3-4], the aggressive wire and the victim wire are transformed into the L-type RC circuit, and the closed-form expressions of peak noise are obtained. In DSM technology, the wire resistance is not negligible and therefore, cannot be neglected and the coupling location becomes one of important factor for crosstalk noise estimation. The model shown in [5] assumes that the input signal is step function, which results in overestimation of noise voltage. Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. A global communication architecture based on a global mesochronous, local synchronous approach allows very high data-rate per wire and therefore, very high bandwidth in buses of limited width. For the estimation method that can handle distributed RC network [6-9], moment matching technique is utilised for deriving the transfer function. Various crosstalk noise models deal with fully coupled structures [10-11] not for partially coupled lines or lines or RC lines. The work in [12] presents a closed form crosstalk noise modelling for on-chip VLSI RC . This paper proposes an estimation method of crosstalk delay and bandwidth for RC circuits. We use an improved aggressor modelling to develop a 2- noise model. The 2- noise model is first proposed in [13]. The Elmore-like derivation method of aggressive waveform is devised. We developed a transformation method that can be applied to all types of RC circuits to the 2- noise model considering the resistive shielding effect. Due to this advancement, the proposed method can estimate the crosstalk noise analytically for any RC circuit. 2. Crosstalk Noise Modelling for Two Partially Coupled Interconnects This section explains the crosstalk modelling. The interconnect structure where two interconnects are partially coupled is shown in Figure 1. The partially coupled interconnects in Figure 1 are modelled as an equivalent circuit as shown in Figure 2.
Fig. 1. Two Coupled Interconnects
Fig. 2.
An Equivalent Circuit of Two Partially Coupled Interconnects for Crosstalk Estimation
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V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
Fig. 3.
Fig. 4.
Model of Aggressive Wire
Model of Victim Wire
Rv1 is the effective driver resistance of the victim net. The node N v2 corresponds to the middle of the coupling interconnects. Rv2 is the resistance between the source and Nv2, and Rv3 is the resistance between Nv2 and the sink. Cc is the coupling capacitance between the victim and the aggressor. The capacitance C v1, Cv2 and Cv3 are represented as C1/2, (C1+C2)/2 and C2/2+Cl, respectively, where C1 is the wire capacitance from the source to Nv2, C2 is wire capacitance from Nv2 to the sink, and C1 is the capacitance of the receiver. The parameters of the aggressive wire, Ra1, Ra2, Ra3, Ca1, Ca2, Ca3, are determined similarly. The proposed estimation method separates the victim net and the aggressive net into two equivalent circuits as one of approximate solutions. The aggressor is modelled as shown in Figure 3. Even without this approximation, we can obtain closed-form waveform expressions, but derived expression is prohibitively complicated and no intuitive information can be extracted. At the victim wire (Figure 4), the aggressive wire is replaced as a voltage source. 2.1.
Aggressor Waveform
In the proposed crosstalk noise model, the voltage source of V agg is assumed to be saturated ramp function. Vagg is expressed as follows:
t Vagg (t )
Vdd 0 t
a
a
Vdd
t
(1)
a
It can be expressed in S-domain as
Vagg ( s)
1 s
Vdd
2
(2)
a
where a is time constant at node na2 as shown in Figure 3. In Elmore delay model, the delay time between is represented as follows [8]: node na1 and node na2, D
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V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
D1
Ra1 Ca1
2
Ca 2
Cc
Ca 3
Ra 2 Ca 2
Cc
Ca 3
(3)
In lumped RC networks, RC product means the transition time that a signal changes from 0% to 63%. Therefore, D corresponds to the time constant at node na2, i.e., a can be expressed as
Ra1 Ca1 Ca 2
a
Cc
Ca3
Ra 2 Ca 2
Cc
Ca3
(4)
The relative inaccuracy of (4) increases as Ra3 becomes large compared to Ra1 and Ra2. This is because the capacitance of Ca3 becomes small due to shielding by the resistance Ra3. In [9], a method to calculate an effective capacitance of RC network is proposed. Using this method, the downstream network from node na2 can be replaced by an effective capacitance Ca3eff. The effective capacitance Ca3eff is derived such that the amount of charge accumulated in Ca3 and the amount of charge of accumulated Ca3eff become the same until a time T, where T is the Elmore delay time from node na1 to node na2. The effective capacitance Ca3eff is given by
Ca 3eff
Ca 3 1 e
T
(5)
Tdjj
where
T
Tdj
Ra1 Ca1 Ca 2
Cc
Ca3
Ra 2 Ca 2
Cc
(6)
Ca3
Ra 3Ca 3
(7)
Hence, (4) becomes a
Ra1 Ca1 Ca 2
Cc
Ca3eff
Ra 2 Ca 2
Cc
Ca3eff
(8)
2.2. Analytical Waveform on Victim Interconnect The analytic voltage waveform at the end of the victim net, i.e., the waveform of crosstalk noise is derived in the 2- victim wire model. In the circuit shown in Figure 4, Vnoise is represented in s domain as follows:
Vnoise( s)
Rv1 Rv 2Cv1s Rv1 Rv 2 Cc s Vagg ( s) as 3 bs 2 ds 1
a
Rv1Rv 2 Rv3Cv1 Cv1 Cc Cv3
b
Rv1Cv1 Rv 2 Cv 2 CC
d
Rv1 Cv1 Cv 2
Cc
Cv3
Cv3
(9) (10)
Rv3Cv3
Rv 2 Cv 2
Rv3Cv3 Cv 2 Cc Rv1
Cc
Cv3
Rv3Cv3
Rv 2
(11) (12)
Equation (9) can be written as
Vnoise( s)
K1 s s1
K2 s s2
K3 Vagg ( s) s s3
(13)
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V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
where poles s1, s2 and s3 are roots are of as 3 the most dominant pole s3
Rv1 s
Vnoise( s)
v
bs 2
ds 1 0 . When relationship of s1< s2<< s3 is satisfied,
Rv 2 Cc Vdd 1 a
v.
Vnoise(s) can also be written as (14). (14)
After solving with partial fractions
Rv1
Vnoise( s)
Rv 2
CcVdd
a
1 s
v vs 1
(15)
Taking inverse Laplace transform, Vnoise (t) is represented as
Rv1 Rv 2
Vnoise(t )
t
CcVdd 1 e tv
(16)
a
2.3.
Estimation of Delay
For calculation of the delay expression, we consider the 50% rise time when vnoise (t) =0.5 Vdd. From (16) we can get the delay expression
Rv1
0.5Vdd
Rv 2
C cVdd 1 e
t tv
a
After simplification of the above equation, we can write
t50% 2.4.
1 v a Cc 2 Rv1 Rv 2
(17)
Estimation of Bandwidth
From (4), we can write the expression for transfer function as
H ( s)
Vnoise( s) Vagg ( s)
Rv1 Rv 2 sCc vs 1 a
(18)
Rearranging (18)
H ( s)
Rv1
Rv 2 a
Cc
s vs 1
(19)
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V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
j
Replacing s by
Rv1
H ( s)
Rv 2
in (19) yields to (20).
j
Cc
j
a
(20)
1
v
After simplification we get
Cc
H( j )
Rv1 a
Rv 2 j 2
1
v
(21)
2 v
Apply modulus on both side and equate to 1
2
1 2
H j
C c Rv1
So, 1 2
Rv 2
(22) 2
1
v
2 v
After simplification we get 3-dB bandwidth in Hz
f
3 dB
a
2
2 c
2C Rv1
Rv 2
2
2
(23)
a v
The above equations (17) and (23) are our proposed delay and bandwidth expressions, respectively, for distributed RC coupled interconnect line. 3. Simulation Results and Discussions In order to verify the accuracy of proposed model, it is compared with the effective lumped model using SPICE. The results are based on (17) and (23) for 0.18 μm process with interconnect resistance (Rt) and capacitance (Ct) varied fr and 100fF to 2pF, respectively. Other pertinent parameters are defined as follows: Rs L =50 pf and RL From Figure 5, we can analyze that with the increase in RC, the bandwidth decreases. This indicates bandwidth dependency on length of a interconnect line. Figure 5 signifies that the bandwidth of an interconnect line for single exponential function approximation exhibits higher accuracy compared to effective lumped element model. Comparison of bandwidth for single exponent approximation and effective lumped model for typical values of RL is shown in Table 1. From Table 1, we find that our model provides the accurate bandwidth estimation compared to other approaches. Our approach could result an error of as low as 5% from SPICE compared to as high as 40-50% error in case of lumped effective model. In the Table 2, the 50% delay of interconnect line are calculated under the different source impedance and load admittance and compared with SPICE.
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V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
Fig. 5. Bandwidth of a distributed line for different values of RC
Table 1: Bandwidth for different values of RL
RC(ns) 0.5 1.0 1.5 2.0 RC(ns) 0.5 1.0 1.5 2.0 RC(ns) 0.5 1.0 1.5 2.0
RL L=50pf Proposed Model 2.21 1.44 1.11 0.92 RL L=50pf Proposed Model 1.36 0.870 0.668 0.554 RL L=50pf Proposed Model 0.813 0.478 0.350 0.282
SPICE 2.21 1.443 1.117 0.93 SPICE 1.361 0.875 0.673 0.570 SPICE 0.82 0..49 0.371 0.322
Table 2: Comparison of Proposed 50% delay with SPICE at different source and load
Source RS 25 50 75 100 125
Load CL (pF) 0.175 0.175 0.175 1.75 1.75
New model Td (ps) 29.65 59.89 95.39 173.23 191.67
SPICE TS (ps) 28.54 57.92 98.89 181.32 190.34
% Error 3.89 3.40 3.53 4.46 0.698
4. Conclusion This paper presents an analytical technique for the estimation of the crosstalk delay and bandwidth model for RC coupled interconnects. The expressions are modelled in such a way that bandwidth and delay of a
V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
distributed line can be estimated accurately. To verify the accuracy of our approach, we have compared our results with the SPICE. Error presented by this model is less than 5% on average compared with HSPICE simulation, for both delay and bandwidth estimation. In this paper we taken unit step input for aggressor which is present near the victim net. We verify the accuracy of the proposed model in 180 nm technology. The proposed model explained above will be useful in much other application at various levels to guide noise aware DSM circuit. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
Wu Shien-Yang, Liew Boon-Khim, Young K.L., Yu, C.H., and Sun, S.C., 1999. Analysis of Interconnect Delay for 0.18μm Technology and Beyond, IEEE International Conference on Interconnect Technology, pp. 68 70. Delmas, S., Caignet, F., Sicard, E., 2000. On Chip Crosstalk Characterization of Deep Submicron Buses, IEEE International Caracas Conference on Devices, Circuits and Systems. Vittal, A., Marek, M., 1997. Crosstalk Reduction for VLSI, IEEE Trans. Computer Aided Design. Integrated Circuits System, Vol. 16. No. 3, pp. 290-298. Rubio, A., Zu, N. Itazaki, X., Kinoshita, K., 1994. An Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits, IEEE Trans. Computer Aided Design, Vol. 13, No. 3. pp. 387-394. Devgan, A., 1997. Efficient Coupled Noise Estimation for On-Chip Interconnects, Proc. ICCAD, pp.147-151,. Sheehan, B. N., 2000, Predicting Coupled Noise in RC Circuits By Matching 1, 2, and 3 Moments, Proc. DAC. pp. 532-535. Kar, R., Maheshwari, V., Mal, A. K., Bhattacharjee, A. K., 2010. Delay Analysis for On-Chip VLSI Interconnect using Gamma Distribution Function, International Journal of Computer Application, vol. 1, no. 3, Article 11, pp. 65-68. Kar, R., Maheshwari, V., Maqbool, Mohd., Mal, A. K., Bhattacharjee, A. K., 2010. A Closed form Delay Evaluation Approach Speed On-Chip RC Interconnects, IEEE 2nd International Advance Computing Conference (IACC 2010), Patiala, India, pp. 129-133. Kar, R., Maheshwari, V., Reddy, M. S. K., Agarwal, V., Mal, A. K., Bhattacharjee, A. K., 2010. An Accurate Delay Metric for Global On-Chip VLSI RC Interconnects using First Three Circuit Moments, 14th VLSI Design And Test Symposium (VDAT 2010), July 7-9, , India. Kawaguchi, H., Sakuraai, T., 1998. Delay and noise formulas for capacitive coupled distributed RC lines, in Proc. AsiaPacific Design Automation conf., pp. 35-43. IEEE Trans. on Sakurai, T., 1993. Closed form expression for interconnection Delay, coupling Electron devices, vol. 40, no1, pp. 118-124. Cong, J., Pan, D. Z., and Srinivas, P. V., 2001. Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization, Proc. ASP -DAC, pp.373-378.
839
Procedia Technology 6 (2012) 832 – 839
2nd International Conference on Communication, Computing & Security [ICCCS-2012]
Crosstalk Aware Bandwidth Modelling for VLSI RC Global Interconnects using 2V. Maheshwaria, A. Bansala, S. K. Chhotrayb, R. Karb,*, D. Mandalb, A. K. Bhattacharjeeb a
Deptt of ECE, Anand Engineering College, Keetham, Agra, U.P., INDIA-282007 b Deptt of ECE, National Institute of Technology, Durgapur, W.B., INDIA
Abstract In this paper, a closed-form bandwidth and delay expressions are derived based on the effective lumped element resistance and capacitance approximation of distributed RC lines using 2. Scarcity of bandwidth demands the efficient use of it for high speed and high data rate transmission systems in VLSI Design and hence, an accurate estimation of bandwidth of on-chip VLSI interconnects has become a crucial and an important issue. The proposed method derives the analytic expressions for delay and the bandwidth using 2- equivalent circuit. Our estimation method is evaluated and justified in 180 nm technology. © 2012 The Authors. Published by Elsevier Ltd. © 2012 Elsevier Ltd...Selection and/or peer-review under responsibility of the Department of Computer Science & Selection and/or peer-review under responsibility of the Department of Computer Science & Engineering, National Engineering, National Institute of Technology Rourkela Institute of Technology Rourkela Keyword: Crosstalk Noise; 2-
odel; Elmore Delay; Delay Estimation; Bandwidth
1. Introduction As integrated circuit feature sizes continue to scale well below 0.18 microns, active device counts are reaching hundreds of millions [1]. The rapid advances in deep sub-micro metre (DSM) technology have resulted in the reduction of feature size which affects the crosstalk noise problem. Crosstalk noise has become a critical problem in DSM VLSI design. Due to the reduction in chip size there is unwanted coupling voltage between two adjacent wires. _____________ * Corresponding author. Tel.:+91-9434788056; fax: +91-343-2547375. E-mail address: [email protected]
2212-0173 © 2012 Elsevier Ltd...Selection and/or peer-review under responsibility of the Department of Computer Science & Engineering, National Institute of Technology Rourkela doi:10.1016/j.protcy.2012.10.101
V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
Several factors bound to the technology contribute to the increase of crosstalk problems: the increase of the number of metal layers [2], the increase of the line thickness, the density of integration and the reduction of the spacing between lines. In [3-4], the aggressive wire and the victim wire are transformed into the L-type RC circuit, and the closed-form expressions of peak noise are obtained. In DSM technology, the wire resistance is not negligible and therefore, cannot be neglected and the coupling location becomes one of important factor for crosstalk noise estimation. The model shown in [5] assumes that the input signal is step function, which results in overestimation of noise voltage. Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. A global communication architecture based on a global mesochronous, local synchronous approach allows very high data-rate per wire and therefore, very high bandwidth in buses of limited width. For the estimation method that can handle distributed RC network [6-9], moment matching technique is utilised for deriving the transfer function. Various crosstalk noise models deal with fully coupled structures [10-11] not for partially coupled lines or lines or RC lines. The work in [12] presents a closed form crosstalk noise modelling for on-chip VLSI RC . This paper proposes an estimation method of crosstalk delay and bandwidth for RC circuits. We use an improved aggressor modelling to develop a 2- noise model. The 2- noise model is first proposed in [13]. The Elmore-like derivation method of aggressive waveform is devised. We developed a transformation method that can be applied to all types of RC circuits to the 2- noise model considering the resistive shielding effect. Due to this advancement, the proposed method can estimate the crosstalk noise analytically for any RC circuit. 2. Crosstalk Noise Modelling for Two Partially Coupled Interconnects This section explains the crosstalk modelling. The interconnect structure where two interconnects are partially coupled is shown in Figure 1. The partially coupled interconnects in Figure 1 are modelled as an equivalent circuit as shown in Figure 2.
Fig. 1. Two Coupled Interconnects
Fig. 2.
An Equivalent Circuit of Two Partially Coupled Interconnects for Crosstalk Estimation
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V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
Fig. 3.
Fig. 4.
Model of Aggressive Wire
Model of Victim Wire
Rv1 is the effective driver resistance of the victim net. The node N v2 corresponds to the middle of the coupling interconnects. Rv2 is the resistance between the source and Nv2, and Rv3 is the resistance between Nv2 and the sink. Cc is the coupling capacitance between the victim and the aggressor. The capacitance C v1, Cv2 and Cv3 are represented as C1/2, (C1+C2)/2 and C2/2+Cl, respectively, where C1 is the wire capacitance from the source to Nv2, C2 is wire capacitance from Nv2 to the sink, and C1 is the capacitance of the receiver. The parameters of the aggressive wire, Ra1, Ra2, Ra3, Ca1, Ca2, Ca3, are determined similarly. The proposed estimation method separates the victim net and the aggressive net into two equivalent circuits as one of approximate solutions. The aggressor is modelled as shown in Figure 3. Even without this approximation, we can obtain closed-form waveform expressions, but derived expression is prohibitively complicated and no intuitive information can be extracted. At the victim wire (Figure 4), the aggressive wire is replaced as a voltage source. 2.1.
Aggressor Waveform
In the proposed crosstalk noise model, the voltage source of V agg is assumed to be saturated ramp function. Vagg is expressed as follows:
t Vagg (t )
Vdd 0 t
a
a
Vdd
t
(1)
a
It can be expressed in S-domain as
Vagg ( s)
1 s
Vdd
2
(2)
a
where a is time constant at node na2 as shown in Figure 3. In Elmore delay model, the delay time between is represented as follows [8]: node na1 and node na2, D
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V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
D1
Ra1 Ca1
2
Ca 2
Cc
Ca 3
Ra 2 Ca 2
Cc
Ca 3
(3)
In lumped RC networks, RC product means the transition time that a signal changes from 0% to 63%. Therefore, D corresponds to the time constant at node na2, i.e., a can be expressed as
Ra1 Ca1 Ca 2
a
Cc
Ca3
Ra 2 Ca 2
Cc
Ca3
(4)
The relative inaccuracy of (4) increases as Ra3 becomes large compared to Ra1 and Ra2. This is because the capacitance of Ca3 becomes small due to shielding by the resistance Ra3. In [9], a method to calculate an effective capacitance of RC network is proposed. Using this method, the downstream network from node na2 can be replaced by an effective capacitance Ca3eff. The effective capacitance Ca3eff is derived such that the amount of charge accumulated in Ca3 and the amount of charge of accumulated Ca3eff become the same until a time T, where T is the Elmore delay time from node na1 to node na2. The effective capacitance Ca3eff is given by
Ca 3eff
Ca 3 1 e
T
(5)
Tdjj
where
T
Tdj
Ra1 Ca1 Ca 2
Cc
Ca3
Ra 2 Ca 2
Cc
(6)
Ca3
Ra 3Ca 3
(7)
Hence, (4) becomes a
Ra1 Ca1 Ca 2
Cc
Ca3eff
Ra 2 Ca 2
Cc
Ca3eff
(8)
2.2. Analytical Waveform on Victim Interconnect The analytic voltage waveform at the end of the victim net, i.e., the waveform of crosstalk noise is derived in the 2- victim wire model. In the circuit shown in Figure 4, Vnoise is represented in s domain as follows:
Vnoise( s)
Rv1 Rv 2Cv1s Rv1 Rv 2 Cc s Vagg ( s) as 3 bs 2 ds 1
a
Rv1Rv 2 Rv3Cv1 Cv1 Cc Cv3
b
Rv1Cv1 Rv 2 Cv 2 CC
d
Rv1 Cv1 Cv 2
Cc
Cv3
Cv3
(9) (10)
Rv3Cv3
Rv 2 Cv 2
Rv3Cv3 Cv 2 Cc Rv1
Cc
Cv3
Rv3Cv3
Rv 2
(11) (12)
Equation (9) can be written as
Vnoise( s)
K1 s s1
K2 s s2
K3 Vagg ( s) s s3
(13)
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V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
where poles s1, s2 and s3 are roots are of as 3 the most dominant pole s3
Rv1 s
Vnoise( s)
v
bs 2
ds 1 0 . When relationship of s1< s2<< s3 is satisfied,
Rv 2 Cc Vdd 1 a
v.
Vnoise(s) can also be written as (14). (14)
After solving with partial fractions
Rv1
Vnoise( s)
Rv 2
CcVdd
a
1 s
v vs 1
(15)
Taking inverse Laplace transform, Vnoise (t) is represented as
Rv1 Rv 2
Vnoise(t )
t
CcVdd 1 e tv
(16)
a
2.3.
Estimation of Delay
For calculation of the delay expression, we consider the 50% rise time when vnoise (t) =0.5 Vdd. From (16) we can get the delay expression
Rv1
0.5Vdd
Rv 2
C cVdd 1 e
t tv
a
After simplification of the above equation, we can write
t50% 2.4.
1 v a Cc 2 Rv1 Rv 2
(17)
Estimation of Bandwidth
From (4), we can write the expression for transfer function as
H ( s)
Vnoise( s) Vagg ( s)
Rv1 Rv 2 sCc vs 1 a
(18)
Rearranging (18)
H ( s)
Rv1
Rv 2 a
Cc
s vs 1
(19)
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V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
j
Replacing s by
Rv1
H ( s)
Rv 2
in (19) yields to (20).
j
Cc
j
a
(20)
1
v
After simplification we get
Cc
H( j )
Rv1 a
Rv 2 j 2
1
v
(21)
2 v
Apply modulus on both side and equate to 1
2
1 2
H j
C c Rv1
So, 1 2
Rv 2
(22) 2
1
v
2 v
After simplification we get 3-dB bandwidth in Hz
f
3 dB
a
2
2 c
2C Rv1
Rv 2
2
2
(23)
a v
The above equations (17) and (23) are our proposed delay and bandwidth expressions, respectively, for distributed RC coupled interconnect line. 3. Simulation Results and Discussions In order to verify the accuracy of proposed model, it is compared with the effective lumped model using SPICE. The results are based on (17) and (23) for 0.18 μm process with interconnect resistance (Rt) and capacitance (Ct) varied fr and 100fF to 2pF, respectively. Other pertinent parameters are defined as follows: Rs L =50 pf and RL From Figure 5, we can analyze that with the increase in RC, the bandwidth decreases. This indicates bandwidth dependency on length of a interconnect line. Figure 5 signifies that the bandwidth of an interconnect line for single exponential function approximation exhibits higher accuracy compared to effective lumped element model. Comparison of bandwidth for single exponent approximation and effective lumped model for typical values of RL is shown in Table 1. From Table 1, we find that our model provides the accurate bandwidth estimation compared to other approaches. Our approach could result an error of as low as 5% from SPICE compared to as high as 40-50% error in case of lumped effective model. In the Table 2, the 50% delay of interconnect line are calculated under the different source impedance and load admittance and compared with SPICE.
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V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
Fig. 5. Bandwidth of a distributed line for different values of RC
Table 1: Bandwidth for different values of RL
RC(ns) 0.5 1.0 1.5 2.0 RC(ns) 0.5 1.0 1.5 2.0 RC(ns) 0.5 1.0 1.5 2.0
RL L=50pf Proposed Model 2.21 1.44 1.11 0.92 RL L=50pf Proposed Model 1.36 0.870 0.668 0.554 RL L=50pf Proposed Model 0.813 0.478 0.350 0.282
SPICE 2.21 1.443 1.117 0.93 SPICE 1.361 0.875 0.673 0.570 SPICE 0.82 0..49 0.371 0.322
Table 2: Comparison of Proposed 50% delay with SPICE at different source and load
Source RS 25 50 75 100 125
Load CL (pF) 0.175 0.175 0.175 1.75 1.75
New model Td (ps) 29.65 59.89 95.39 173.23 191.67
SPICE TS (ps) 28.54 57.92 98.89 181.32 190.34
% Error 3.89 3.40 3.53 4.46 0.698
4. Conclusion This paper presents an analytical technique for the estimation of the crosstalk delay and bandwidth model for RC coupled interconnects. The expressions are modelled in such a way that bandwidth and delay of a
V. Maheshwari et al. / Procedia Technology 6 (2012) 832 – 839
distributed line can be estimated accurately. To verify the accuracy of our approach, we have compared our results with the SPICE. Error presented by this model is less than 5% on average compared with HSPICE simulation, for both delay and bandwidth estimation. In this paper we taken unit step input for aggressor which is present near the victim net. We verify the accuracy of the proposed model in 180 nm technology. The proposed model explained above will be useful in much other application at various levels to guide noise aware DSM circuit. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
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