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Cryogenic etching of nano-scale silicon trenches with resist masks
Microelectronic Engineering 88 (2011) 2785–2789
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Cryogenic etching of nano-scale silicon trenches with resist masks Y. Wu a,b,⇑, D.L. Olynick b,⇑, A. Goodyear a, C. Peroz c,b, S. Dhuey b, X. Liang b, S. Cabrini b a
Oxford Instruments America, Inc., 300 Baker Avenue, Suite 150, Concord, MA 01742, USA The Molecular Foundry, Lawrence Berkeley National Laboratory, Berkeley, CA 94720, USA c aBeam Technologies, 5286 Dunnigan Ct., Castro Valley, CA 94546, USA b
a r t i c l e
i n f o
Article history: Received 19 September 2010 Accepted 25 November 2010 Available online 30 November 2010 Keywords: Plasma etching Nanofabrication Nano-imprint lithography Electron beam lithography Nano-scale pattern transfer
a b s t r a c t Cryogenic silicon etching using SF6–O2 at the sub-50 nm scale has been developed for nano-electromechanical systems (NEMS) and nano-photonics systems where high aspect ratio trenches are desired. It was found that the SF6–O2 chemistry at cryogenic temperatures (100 to 130 °C) provides the best combination of etch rate, selectivity, and profile control for the smallest trenches etched. The profile can be well controlled with aspect ratios on the order of 8:1 for 20 nm wide trenches. The various etch parameter trends will be discussed along with methods to achieve the optimal profiles and etch rates. Ó 2010 Elsevier B.V. All rights reserved.
1. Introduction Cryogenic silicon etching has been used frequently in MEMS to etch high aspect ratio structures and deep, large features in silicon [1–4]. It is often compared with the ‘‘Bosch’’ or ‘‘Gas-Chopping’’ process and the ‘‘pseudo-Bosch’’ or ‘‘Mixed mode’’ process when choosing the etch for a specific application [5,6]. Cryogenic silicon etching offers several advantages over SF6-flurocarbon based processes, including the fact that it is an inherently ‘‘clean’’ process, with no polymer deposition to the chamber walls, it also has a very thin passivant layer, and therefore only a low energy ion bombardment is required to remove the passivation layer from the bottom and continue the vertical component of the etch. The low energy ion bombardment allows soft masks such as photoresist to be used with a selectivity of greater than 10:1 while maintaining a fast etch rate of up to several hundred nanometers/minute. The continuous process and thin passivation layer also eliminates sidewall scalloping, leading to a smooth sidewall. The cryogenic silicon etch processes utilize a SF6–O2 chemistry to passivate and etch the silicon. A SiOxFy passivation layer is formed by injecting small amounts of oxygen gas, O2, along with the SF6 while holding the wafer at temperatures of 100 to 130 °C. Studies on the formation and destruction of the SiOxFy passivation layer have shown that the temperature and oxygen flow are key in controlling the ⇑ Corresponding authors. Address: The Molecular Foundry, Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720, USA. Tel.: +1 510 4867340 (Y. Wu), +1 510 4867268 (D.L. Olynick). E-mail addresses: [email protected], [email protected] (Y. Wu), [email protected] (D.L. Olynick). 0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.11.055
thickness of the passivant and the profile of the etch [7,8]. Numerous methods and guidelines have been previously developed for cryo-etching for large MEMS structures [9–11]. In this paper, strategies are discussed to apply these methods to features in the sub50 nm regime. 2. Experimental parameters The cryo etching was carried out in an Oxford Instruments Plasmalab System 100 with a Cobra inductively coupled plasma (ICP) source and liquid nitrogen cryogenically cooled stage. Fig. 1 is a schematic diagram of the ICP source showing the main components. The patterns were generated via electron beam lithography (EBL) and nano-imprint lithography (NIL) on whole 4- and 8-inch wafers, respectively, and were diced into smaller 1 inch 1 inch square samples for etching. The patterns generated with EBL were 400 lm long lines and ranged from 100 to 20 nm in width with varying pitch densities. Trenches were chosen to be etched due to their applications to grating structures in nano-photonics and NIL templates [12,13]. The electron beam resist was ZEP-520A with a thickness of approximately 40 nm. The patterns produced from NIL were similar in dimension, with a 50 nm thick resist mask. A more detailed discussion of the pattern transfer using NIL and cryo etching can be found in [14]. After dicing, the samples were bonded onto a 4-inch silicon wafer carrier using Fomblin oil; this prevented the sample from sliding on the carrier wafer and improved the thermal conductivity between the sample and carrier. After etching, the oil can be removed with isopropyl alcohol (IPA). The wafers were loaded into the main etch chamber through the load lock chamber and mechanically clamped onto the lower
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Y. Wu et al. / Microelectronic Engineering 88 (2011) 2785–2789
Fig. 1. Schematic of the Oxford Instruments Plasmalab ICP used for etching.
Table 1 Summary of the different etch parameters as they are affected by an increase in different hardware etch controls. "
Etch Rate
Selectivity
Sidewall rrofile
Aspect ratio
ICP Power
Increases
Decreases
Increases
RF Power Temperature
Slight increase Increases
Undercut/bowing
Decreases
Pressure SF6: O2 ratio Feature Size
Increases Increases Increases
Large decrease Slight decrease Increases Increases N/A
More negative taper More vertical
Undercut/bowing Undercut/bowing More positive taper
Increases Increases Decreases
Increases
electrode. The lower electrode was cooled with liquid nitrogen and helium gas was used as the thermal conducting medium between the wafer and electrode. The bottom electrode was powered by a RF frequency of 13.56 MHz with a power of 630 W for this process; this generates a self DC bias which provides the ion energy and directionality. The process gases are introduced to the chamber with a pressure of around 5–20 mTorr. The ICP source is powered by a solenoidal coil at a frequency of 2 MHz with powers of 700– 1000 W to generate a high density plasma. This provides independent control of the ion energy and ion density. The whole chamber is pumped by a turbo molecular pump backed by a mechanical pump and the etch products are removed. The results of the silicon etch were measured by scanning electron microscopy (SEM). 3. Results It was found that 20 nm trenches could be etched with a thin resist mask to aspect ratios of over 8:1 using the cryo etching
technique with minimal visible sidewall roughness. The process used for the etch was with a pressure of 6 mTorr, temperature of 130 °C, ICP power of 700 W, RF bias power of 10 W, SF6 flow rate of 34 sccm and O2 flow rate of 16 sccm. Table 1 shows how an increase in each of the plasma etch controls affects the various measurable etch parameters. Figs. 2 and 3 show 20 nm features of different pitch etched to a depth of 155 and 170 nm. This process gives a selectivity of 9:1 for ZEP-520A and an etch rate of 200 nm/min. It was found that the etch rate and the sidewall profile are dependent on the trench opening. For wider trenches, the etch depth was greater and the profile was also more positively tapered. The increase in etch rate for larger features is known as lag and is commonly seen in reactive ion etching [15–16], and is more of an aspect ratio dependent effect rather than a trench opening dependency.
3.1. Sidewall profile dependency on trench size Aside from the etch rate, the sidewall angle of the trenches from cryo etch also varies with trench width. The main suspected reason is that the oxygen transport is limited for smaller trenches, and a higher flow of oxygen is needed to form the SiOxFy passivation layer for trenches with decreased openings. For a constant SF6 to O2 ratio which produces a vertical sidewall at a specific trench size, as the trench size increases, the profile will become more positive as more oxygen is available to form the passivant. As the trench size decreases, the profile will be undercut or bowed out since there is not enough oxygen reaching the trench sidewalls to form the passivant. Fig. 4 shows the profile difference for the same process between a 100 nm trench and a 20 nm trench. This effect is not dependent on the aspect ratio as Fig. 5 shows 400 and 45 nm trenches both etched with the same process to the same aspect
Fig. 2. 22 nm wide trenches etched to a depth of 155 nm with a pitch of 120 nm.
Y. Wu et al. / Microelectronic Engineering 88 (2011) 2785–2789
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Fig. 3. 22 nm wide trenches etched to a depth of 170 nm with a pitch of 60 nm.
Fig. 4. 100 nm (a) and 20 nm (b) trench openings on the same sample etched with the same process. The 100 nm trench is over-passivated and the 20 nm trench is slightly under-passivated.
Fig. 5. 400 nm wide trenches (a) and 45 nm wide trenches (b) etched to the same aspect ratio (3.33) using the same etch process. The sidewall profiles look vastly different for the two etches.
ratio of 3.33. The larger feature shows a positive slope due to overpassivation and pinch off near the bottom due to ion focusing while the smaller feature is etched vertically. 3.2. Addition of LF bias Both the RIE lag and the profile dependency on the trench opening can be reduced by adding a low frequency (350 kHz) bias
(5–10 W) to the lower electrode. This widens the ion energy distribution function (IEDF) of the ions that reach the wafer, and increases the overall passivation removal from the trench bottom, allowing for a more uniform etch across various feature sizes. However, adding the LF bias also reduces the etch selectivity to resist, thus making it undesirable in some cases where very high aspect ratios are required. Fig. 6 shows the effect of the LF on the profile for a given 100 nm etch; all other parameters remained
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the same. The dependency of the etch rate and profile angle and their dependency on the trench opening can be seen in Fig. 7. It can be seen that the range of the etch rate and profile angle for etches performed with the LF bias is much tighter, thus giving a more uniform etch for different trench sizes.
4. Conclusions For sub-50 nm trenches in NEMS and nano-electronics, a well controlled etch/passivation process which produces vertical sidewalls and smooth surfaces is necessary. However, fluorocarbon chemistry passivated etch processes will require a hardmask due to the poor selectivity to resist, and using hardmasks for nano-scale features is difficult because that will require additional pattern transfer steps, thus increasing the complexity of the processing and increasing the chance for errors and defects. Using the cryogenic SF6–O2 etch, we have achieved nearly 8:1 aspect ratio trenches with widths down to 20 nm. As features shrink, the amount of oxygen that is required to keep the passivation at the required level increases as well. The increase in oxygen flow along with the smaller exposed silicon area can also reduce the etch rate to 100 nm/min or less, making it much easier to control for shallow etches. One thing to note is that in order to etch features which greatly differ in size, the process to produce uniform etching results will be much more complicated. For pattern transfer of sub-25 nm trenches for nano-photonics, nano-fluidics, and nanoimprint lithography templates, the cryogenic silicon etch process is a good option.
Acknowledgements
Fig. 6. 100 nm features etched with (a) and without (b) LF bias. The profile is much straighter in the case where the LF bias is applied.
The authors would like to thank Bruce Harteneck, Erin Wood, Eric Lozano, and all members of the nanofabrication group of The Molecular Foundry as well as Craig Ward and Ian Stuart of Oxford Instruments for their help and support. This project is supported by the Office of Science, Office of Basic Energy Sciences, of the U.S. Department of Energy under Contract No. DE-AC02-05CH11231.
Fig. 7. (a and b) Dependence of the profile angle and etch rate on the trench opening with and without a low frequency bias present.
Y. Wu et al. / Microelectronic Engineering 88 (2011) 2785–2789
References [1] S. Tachi, K. Tsujimoto, S. Okudaira, Appl. Phys. Lett. 52 (1988) 616. [2] A.F. Isakovic, K. Evans-Lutterodt, D. Elliott, A. Stein, J.B. Warren, J. Vac. Sci. Technol. A 26 (5) (2008) 1182. [3] M.D. Henry, S. Walavalkar, A. Homyk, A. Scherer, Nanotechnology 20 (25) (2009) 255305. [4] I.W. Rangelow, J. Vac. Sci. Technol. A 21 (2003) 1550. [5] M.D. Henry, C. Welch, A. Scherer, J. Vac. Sci. Technol. A 27 (5) (2009) 1211. [6] C.C. Welch, A.L. Goodyear, T. Wahlbrink, M.C. Lemme, T. Mollenhauer, Microelectron. Eng. 83 (2006) 1170. [7] X. Mellhaoui, R. Dussart, T. Tillocher, P. Lefaucheux, P. Ranson, M. Boufnichel, L.J. Overzet, J. Appl. Phys. 98 (2005) 104901. [8] R. Dussart, X. Mellhaoui, T. Tillocher, P. Lefaucheux, M. Volatier, C. SocquetClerc, P. Brault, P. Ranson, J. Phys. D 38 (2005) 3395.
2789
[9] M.J. Boer, J.G.E. Gardenies, H.V. Jansen, E. Smulders, M.J. Gilde, G. Roelofs, J.N. Sasserath, M. Elwenspoek, J. Microelectromech. Syst. 11 (4) (2002) 385. [10] M. Boufnichel, S. Aachboun, P. Lefaucheux, P. Ranson, J. Vac. Sci. Technol. B 20 (4) (2002) 1508. [11] H.V. Jansen, M.J. de Boer, S. Unnikrishnan, M.C. Louwerse, M.C. Elwenspoek, J. Micromech. Microeng. 19 (2009) 960. [12] A.L. Goodyear, D. Olynick, et al., J. Vac. Sci. Technol. B 18 (2000) 3471. [13] D.L. Olynick, J.A. Liddle, B.D. Harteneck, S. Cabrini, I.W. Rangelow, Proc. SPIE (2007) 6462. [14] C. Peroz, S. Dhuey, M. Volger, Y. Wu, D. Olynick, S. Cabrini, Nanotechnology 21 (2010) 445301. [15] D. Keil, E. Anderson, J. Vac. Sci. Technol. B 19 (2001) 2082. [16] H. Jansen, M. De Boer, R. Wiegerink, N. Tas, E. Smulders, C. Neagu, M. Elwenspoek, Microelectron. Eng. 35 (1997) 45.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Cryogenic etching of nano-scale silicon trenches with resist masks Y. Wu a,b,⇑, D.L. Olynick b,⇑, A. Goodyear a, C. Peroz c,b, S. Dhuey b, X. Liang b, S. Cabrini b a
Oxford Instruments America, Inc., 300 Baker Avenue, Suite 150, Concord, MA 01742, USA The Molecular Foundry, Lawrence Berkeley National Laboratory, Berkeley, CA 94720, USA c aBeam Technologies, 5286 Dunnigan Ct., Castro Valley, CA 94546, USA b
a r t i c l e
i n f o
Article history: Received 19 September 2010 Accepted 25 November 2010 Available online 30 November 2010 Keywords: Plasma etching Nanofabrication Nano-imprint lithography Electron beam lithography Nano-scale pattern transfer
a b s t r a c t Cryogenic silicon etching using SF6–O2 at the sub-50 nm scale has been developed for nano-electromechanical systems (NEMS) and nano-photonics systems where high aspect ratio trenches are desired. It was found that the SF6–O2 chemistry at cryogenic temperatures (100 to 130 °C) provides the best combination of etch rate, selectivity, and profile control for the smallest trenches etched. The profile can be well controlled with aspect ratios on the order of 8:1 for 20 nm wide trenches. The various etch parameter trends will be discussed along with methods to achieve the optimal profiles and etch rates. Ó 2010 Elsevier B.V. All rights reserved.
1. Introduction Cryogenic silicon etching has been used frequently in MEMS to etch high aspect ratio structures and deep, large features in silicon [1–4]. It is often compared with the ‘‘Bosch’’ or ‘‘Gas-Chopping’’ process and the ‘‘pseudo-Bosch’’ or ‘‘Mixed mode’’ process when choosing the etch for a specific application [5,6]. Cryogenic silicon etching offers several advantages over SF6-flurocarbon based processes, including the fact that it is an inherently ‘‘clean’’ process, with no polymer deposition to the chamber walls, it also has a very thin passivant layer, and therefore only a low energy ion bombardment is required to remove the passivation layer from the bottom and continue the vertical component of the etch. The low energy ion bombardment allows soft masks such as photoresist to be used with a selectivity of greater than 10:1 while maintaining a fast etch rate of up to several hundred nanometers/minute. The continuous process and thin passivation layer also eliminates sidewall scalloping, leading to a smooth sidewall. The cryogenic silicon etch processes utilize a SF6–O2 chemistry to passivate and etch the silicon. A SiOxFy passivation layer is formed by injecting small amounts of oxygen gas, O2, along with the SF6 while holding the wafer at temperatures of 100 to 130 °C. Studies on the formation and destruction of the SiOxFy passivation layer have shown that the temperature and oxygen flow are key in controlling the ⇑ Corresponding authors. Address: The Molecular Foundry, Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720, USA. Tel.: +1 510 4867340 (Y. Wu), +1 510 4867268 (D.L. Olynick). E-mail addresses: [email protected], [email protected] (Y. Wu), [email protected] (D.L. Olynick). 0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.11.055
thickness of the passivant and the profile of the etch [7,8]. Numerous methods and guidelines have been previously developed for cryo-etching for large MEMS structures [9–11]. In this paper, strategies are discussed to apply these methods to features in the sub50 nm regime. 2. Experimental parameters The cryo etching was carried out in an Oxford Instruments Plasmalab System 100 with a Cobra inductively coupled plasma (ICP) source and liquid nitrogen cryogenically cooled stage. Fig. 1 is a schematic diagram of the ICP source showing the main components. The patterns were generated via electron beam lithography (EBL) and nano-imprint lithography (NIL) on whole 4- and 8-inch wafers, respectively, and were diced into smaller 1 inch 1 inch square samples for etching. The patterns generated with EBL were 400 lm long lines and ranged from 100 to 20 nm in width with varying pitch densities. Trenches were chosen to be etched due to their applications to grating structures in nano-photonics and NIL templates [12,13]. The electron beam resist was ZEP-520A with a thickness of approximately 40 nm. The patterns produced from NIL were similar in dimension, with a 50 nm thick resist mask. A more detailed discussion of the pattern transfer using NIL and cryo etching can be found in [14]. After dicing, the samples were bonded onto a 4-inch silicon wafer carrier using Fomblin oil; this prevented the sample from sliding on the carrier wafer and improved the thermal conductivity between the sample and carrier. After etching, the oil can be removed with isopropyl alcohol (IPA). The wafers were loaded into the main etch chamber through the load lock chamber and mechanically clamped onto the lower
2786
Y. Wu et al. / Microelectronic Engineering 88 (2011) 2785–2789
Fig. 1. Schematic of the Oxford Instruments Plasmalab ICP used for etching.
Table 1 Summary of the different etch parameters as they are affected by an increase in different hardware etch controls. "
Etch Rate
Selectivity
Sidewall rrofile
Aspect ratio
ICP Power
Increases
Decreases
Increases
RF Power Temperature
Slight increase Increases
Undercut/bowing
Decreases
Pressure SF6: O2 ratio Feature Size
Increases Increases Increases
Large decrease Slight decrease Increases Increases N/A
More negative taper More vertical
Undercut/bowing Undercut/bowing More positive taper
Increases Increases Decreases
Increases
electrode. The lower electrode was cooled with liquid nitrogen and helium gas was used as the thermal conducting medium between the wafer and electrode. The bottom electrode was powered by a RF frequency of 13.56 MHz with a power of 630 W for this process; this generates a self DC bias which provides the ion energy and directionality. The process gases are introduced to the chamber with a pressure of around 5–20 mTorr. The ICP source is powered by a solenoidal coil at a frequency of 2 MHz with powers of 700– 1000 W to generate a high density plasma. This provides independent control of the ion energy and ion density. The whole chamber is pumped by a turbo molecular pump backed by a mechanical pump and the etch products are removed. The results of the silicon etch were measured by scanning electron microscopy (SEM). 3. Results It was found that 20 nm trenches could be etched with a thin resist mask to aspect ratios of over 8:1 using the cryo etching
technique with minimal visible sidewall roughness. The process used for the etch was with a pressure of 6 mTorr, temperature of 130 °C, ICP power of 700 W, RF bias power of 10 W, SF6 flow rate of 34 sccm and O2 flow rate of 16 sccm. Table 1 shows how an increase in each of the plasma etch controls affects the various measurable etch parameters. Figs. 2 and 3 show 20 nm features of different pitch etched to a depth of 155 and 170 nm. This process gives a selectivity of 9:1 for ZEP-520A and an etch rate of 200 nm/min. It was found that the etch rate and the sidewall profile are dependent on the trench opening. For wider trenches, the etch depth was greater and the profile was also more positively tapered. The increase in etch rate for larger features is known as lag and is commonly seen in reactive ion etching [15–16], and is more of an aspect ratio dependent effect rather than a trench opening dependency.
3.1. Sidewall profile dependency on trench size Aside from the etch rate, the sidewall angle of the trenches from cryo etch also varies with trench width. The main suspected reason is that the oxygen transport is limited for smaller trenches, and a higher flow of oxygen is needed to form the SiOxFy passivation layer for trenches with decreased openings. For a constant SF6 to O2 ratio which produces a vertical sidewall at a specific trench size, as the trench size increases, the profile will become more positive as more oxygen is available to form the passivant. As the trench size decreases, the profile will be undercut or bowed out since there is not enough oxygen reaching the trench sidewalls to form the passivant. Fig. 4 shows the profile difference for the same process between a 100 nm trench and a 20 nm trench. This effect is not dependent on the aspect ratio as Fig. 5 shows 400 and 45 nm trenches both etched with the same process to the same aspect
Fig. 2. 22 nm wide trenches etched to a depth of 155 nm with a pitch of 120 nm.
Y. Wu et al. / Microelectronic Engineering 88 (2011) 2785–2789
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Fig. 3. 22 nm wide trenches etched to a depth of 170 nm with a pitch of 60 nm.
Fig. 4. 100 nm (a) and 20 nm (b) trench openings on the same sample etched with the same process. The 100 nm trench is over-passivated and the 20 nm trench is slightly under-passivated.
Fig. 5. 400 nm wide trenches (a) and 45 nm wide trenches (b) etched to the same aspect ratio (3.33) using the same etch process. The sidewall profiles look vastly different for the two etches.
ratio of 3.33. The larger feature shows a positive slope due to overpassivation and pinch off near the bottom due to ion focusing while the smaller feature is etched vertically. 3.2. Addition of LF bias Both the RIE lag and the profile dependency on the trench opening can be reduced by adding a low frequency (350 kHz) bias
(5–10 W) to the lower electrode. This widens the ion energy distribution function (IEDF) of the ions that reach the wafer, and increases the overall passivation removal from the trench bottom, allowing for a more uniform etch across various feature sizes. However, adding the LF bias also reduces the etch selectivity to resist, thus making it undesirable in some cases where very high aspect ratios are required. Fig. 6 shows the effect of the LF on the profile for a given 100 nm etch; all other parameters remained
2788
Y. Wu et al. / Microelectronic Engineering 88 (2011) 2785–2789
the same. The dependency of the etch rate and profile angle and their dependency on the trench opening can be seen in Fig. 7. It can be seen that the range of the etch rate and profile angle for etches performed with the LF bias is much tighter, thus giving a more uniform etch for different trench sizes.
4. Conclusions For sub-50 nm trenches in NEMS and nano-electronics, a well controlled etch/passivation process which produces vertical sidewalls and smooth surfaces is necessary. However, fluorocarbon chemistry passivated etch processes will require a hardmask due to the poor selectivity to resist, and using hardmasks for nano-scale features is difficult because that will require additional pattern transfer steps, thus increasing the complexity of the processing and increasing the chance for errors and defects. Using the cryogenic SF6–O2 etch, we have achieved nearly 8:1 aspect ratio trenches with widths down to 20 nm. As features shrink, the amount of oxygen that is required to keep the passivation at the required level increases as well. The increase in oxygen flow along with the smaller exposed silicon area can also reduce the etch rate to 100 nm/min or less, making it much easier to control for shallow etches. One thing to note is that in order to etch features which greatly differ in size, the process to produce uniform etching results will be much more complicated. For pattern transfer of sub-25 nm trenches for nano-photonics, nano-fluidics, and nanoimprint lithography templates, the cryogenic silicon etch process is a good option.
Acknowledgements
Fig. 6. 100 nm features etched with (a) and without (b) LF bias. The profile is much straighter in the case where the LF bias is applied.
The authors would like to thank Bruce Harteneck, Erin Wood, Eric Lozano, and all members of the nanofabrication group of The Molecular Foundry as well as Craig Ward and Ian Stuart of Oxford Instruments for their help and support. This project is supported by the Office of Science, Office of Basic Energy Sciences, of the U.S. Department of Energy under Contract No. DE-AC02-05CH11231.
Fig. 7. (a and b) Dependence of the profile angle and etch rate on the trench opening with and without a low frequency bias present.
Y. Wu et al. / Microelectronic Engineering 88 (2011) 2785–2789
References [1] S. Tachi, K. Tsujimoto, S. Okudaira, Appl. Phys. Lett. 52 (1988) 616. [2] A.F. Isakovic, K. Evans-Lutterodt, D. Elliott, A. Stein, J.B. Warren, J. Vac. Sci. Technol. A 26 (5) (2008) 1182. [3] M.D. Henry, S. Walavalkar, A. Homyk, A. Scherer, Nanotechnology 20 (25) (2009) 255305. [4] I.W. Rangelow, J. Vac. Sci. Technol. A 21 (2003) 1550. [5] M.D. Henry, C. Welch, A. Scherer, J. Vac. Sci. Technol. A 27 (5) (2009) 1211. [6] C.C. Welch, A.L. Goodyear, T. Wahlbrink, M.C. Lemme, T. Mollenhauer, Microelectron. Eng. 83 (2006) 1170. [7] X. Mellhaoui, R. Dussart, T. Tillocher, P. Lefaucheux, P. Ranson, M. Boufnichel, L.J. Overzet, J. Appl. Phys. 98 (2005) 104901. [8] R. Dussart, X. Mellhaoui, T. Tillocher, P. Lefaucheux, M. Volatier, C. SocquetClerc, P. Brault, P. Ranson, J. Phys. D 38 (2005) 3395.
2789
[9] M.J. Boer, J.G.E. Gardenies, H.V. Jansen, E. Smulders, M.J. Gilde, G. Roelofs, J.N. Sasserath, M. Elwenspoek, J. Microelectromech. Syst. 11 (4) (2002) 385. [10] M. Boufnichel, S. Aachboun, P. Lefaucheux, P. Ranson, J. Vac. Sci. Technol. B 20 (4) (2002) 1508. [11] H.V. Jansen, M.J. de Boer, S. Unnikrishnan, M.C. Louwerse, M.C. Elwenspoek, J. Micromech. Microeng. 19 (2009) 960. [12] A.L. Goodyear, D. Olynick, et al., J. Vac. Sci. Technol. B 18 (2000) 3471. [13] D.L. Olynick, J.A. Liddle, B.D. Harteneck, S. Cabrini, I.W. Rangelow, Proc. SPIE (2007) 6462. [14] C. Peroz, S. Dhuey, M. Volger, Y. Wu, D. Olynick, S. Cabrini, Nanotechnology 21 (2010) 445301. [15] D. Keil, E. Anderson, J. Vac. Sci. Technol. B 19 (2001) 2082. [16] H. Jansen, M. De Boer, R. Wiegerink, N. Tas, E. Smulders, C. Neagu, M. Elwenspoek, Microelectron. Eng. 35 (1997) 45.